JP2000353380A - Ferroelectric memory and control method for its operation, structure of ferroelectric memory cell and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of erroneous data discrimination caused by variation of a reference potential by storing two bit data using plural ferroelectric capacitors utilizing polarization phenomenon of a ferroelectric substance. SOLUTION: A ferroelectric memory 1 is provided with three ferroelectric capacitors 39-41 connected in series, and a memory cell 2 constituted of two MOS transistors 25, 26 and storing two bit data. Two kinds of state exist in data written in each ferroelectric capacitors 39-41 depending on the direction of residual polarization. For example, data obtained when voltage is applied in a state in which a potential of a bit line side is higher than a potential of a plate line side are assumed as 1, and data obtained when voltage is applied in a state in which a potential of a bit line side is lower than the potential of a plate line side are assumed as 0, data written in each ferroelectric capacitors 39-41 are read out to bit lines BL1A, BL1B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory and an operation control method thereof, and a ferroelectric memory cell structure and a manufacturing method thereof. The present invention relates to a ferroelectric memory in which a memory cell is constituted by a plurality of memory cell transistors, a method of controlling the operation thereof, a ferroelectric memory cell structure, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor memory devices are roughly divided into so-called volatile memories, in which stored data is lost when the power is turned off, and so-called nonvolatile memories, in which the stored data is retained even when the power is turned off. You. The former representative is RA
While known as M (Random Access Memory), the latter representative is known as ROM (Read Only Memory). Most of these memories are constituted by MOS (Metal Oxide Semiconductor) type transistors which are excellent in integration degree.

A RAM is widely applied to various types of storage devices such as data devices because a RAM can make the most of the above-described advantage of high integration as compared with a ROM and can reduce the cost. Further, among the RAMs, a widely used D (Dynamic) RAM uses a capacitance (capacitor) to store data depending on the presence or absence of electric charge of the capacitance. In order to compensate for the decrease in storage capacity due to the restriction on the occupied area of the memory, various ideas have been devised for the structure of the capacitor.

As a kind of RAM, a ferroelectric memory using a ferroelectric material as a dielectric material constituting the above-mentioned capacitor has been developed. By utilizing this phenomenon, the device operates as a nonvolatile RAM in which stored data is not erased even when the power is turned off.

FIG. 12 is a circuit diagram showing a conventional ferroelectric memory disclosed, for example, in Japanese Patent No. 2674775. As shown in FIG. 1, the ferroelectric memory includes a ferroelectric capacitor 102 that retains a memory, and a memory cell transistor 101 that performs a switching operation by connecting the ferroelectric capacitor 102 in series. A memory cell 104 that stores 1-bit data is provided.
The word line WL is connected to the gate electrode of the memory cell transistor 101, and the plate line PL is connected to the electrode of the ferroelectric capacitor 102 opposite to the side to which the memory cell transistor 101 is connected. Further, a bit line BL is connected to an electrode of the memory cell transistor 101 opposite to the side to which the ferroelectric capacitor 102 is connected, and a differential sense amplifier 103 is connected to the bit line BL. . This ferroelectric memory is characterized in that one ferroelectric capacitor 102 and one memory cell transistor 101 constitute a memory cell 104.

FIG. 13 shows another conventional example, and is a circuit diagram showing a ferroelectric memory having two ferroelectric capacitors disclosed in, for example, Japanese Patent No. 2736072. As shown in the figure, a ferroelectric memory has a plurality of memory cells 120, 12 each storing 1-bit data.
2, 124 and 126. Here, one memory cell 120 includes two ferroelectric capacitors 121A and 121B connected in series, and these series-connected capacitors 121A and 121B.
A and 121B are constituted by the memory cell transistor 128 connected in the example.

Similarly, the memory cell 122 is formed by two ferroelectric capacitors 123 A and 123 B connected in series and a memory cell transistor 129.
Reference numeral 24 denotes two ferroelectric capacitors 125A connected in series.
125B and the memory cell transistor 131, and the memory cell 126 is composed of two ferroelectric capacitors 127A and 127B and a memory cell transistor 133 connected in series.

The first word line 130 is connected to the memory cell 12
The second word line 132 is connected to the gate electrode of each of the memory cell transistors 131 and 133 of each of the memory cells 124 and 126, and is connected to the gate electrode of each of the memory cell transistors 128 and 129 of each of the memory cells 0 and 122. Have been. The first bit line 134 and the second bit line 136 are orthogonal to the first word line 130 and the second word line 132, respectively. Further, the common lines 138 and 140 forming the first pair line 141 are connected to one electrode of the ferroelectric capacitors 121A, 123A and 121B and 123B of the memory cells 120 and 122, respectively. The common lines 142 and 144 forming the second pair line 145 are connected to the ferroelectric capacitors 125A, 125A,
It is connected to one of electrodes 27A, 125B and 127B. In the ferroelectric memory, as described above, one memory cell, for example, the memory cell 120 is configured by two ferroelectric capacitors 121A and 121B connected in series and one memory cell transistor 128. Is the feature.

[0009]

By the way, Patent No. 26
In the conventional ferroelectric memory described in Japanese Patent No. 74775, 1
Since a ferroelectric memory is configured using two ferroelectric capacitors, the reference potential is likely to change at the time of reading data, so that there is a problem that a data identification error easily occurs. That is, at the time of data reading, a reference potential as a reference for discriminating between level 1 and level 0 is applied to the bit line. Since the value changes due to the influence, the reference potential deviates from the optimum value. In the worst case, it is difficult to discriminate between 1 and 0, and a data discrimination error occurs. Further, in the conventional ferroelectric memory described in Japanese Patent No. 2736072, a memory cell is formed using two ferroelectric capacitors connected in series, so that the reference potential is fixed in principle. Although the disadvantages described above are prevented,
The area occupied by the memory cell per bit increases.
There is a problem. That is, since two ferroelectric memories are used to store 1-bit data, the memory cell requires an area for two ferroelectric capacitors, and as a result, the area occupied by the memory cell Will increase.

The present invention has been made in view of the above-mentioned circumstances, and has an area occupied by memory cells required to store 1-bit data without causing a data identification error due to a change in reference potential. It is an object of the present invention to provide a ferroelectric memory and a method of controlling the operation thereof, and a ferroelectric memory cell structure and a method of manufacturing the same, which can reduce the number of cells.

[0011]

In order to solve the above-mentioned problems, the invention according to claim 1 relates to a ferroelectric memory for storing data by utilizing the polarization phenomenon of a ferroelectric material. It is characterized in that two-bit data is stored using a ferroelectric capacitor.

According to a second aspect of the present invention, there is provided a ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, comprising three ferroelectric capacitors and two memory cell transistors. Characterized in that the memory cell is provided.

According to a third aspect of the present invention, there is provided a ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, wherein first, second and third three elements are connected in series. A memory cell is formed by the ferroelectric capacitor and the first and second two memory cell transistors. Of the three ferroelectric capacitors, the first and second ferroelectric capacitors are mutually connected. Both connected electrodes are connected to a first bit line via the first memory cell transistor, and both connected electrodes of the second and third ferroelectric capacitors are connected together. The second memory cell transistor is connected to a second bit line via the second memory cell transistor, and the first and second memory cell transistors are connected to a common word line.

According to a fourth aspect of the present invention, there is provided the ferroelectric memory according to the third aspect, wherein a first plate line is provided on an electrode of the first ferroelectric capacitor to which the bit line is not connected. A second plate line is connected to an electrode which is connected and to which the bit line of the third ferroelectric capacitor is not connected.

According to a fifth aspect of the present invention, there is provided the ferroelectric memory according to the third or fourth aspect, wherein a first reference potential applying bit line corresponding to the first bit line and the second bit line are provided. , A second reference potential applying bit line corresponding to the first and second reference potential applying bit lines is provided, and the first bit line and the first reference potential applying bit line are connected to a first differential sense amplifier.
And the second reference potential applying bit line are connected to a second differential sense amplifier.

According to a sixth aspect of the present invention, there is provided a memory cell comprising first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors. And the electrodes of the first and second ferroelectric capacitors, which are connected to each other, are both connected to the first ferroelectric capacitor via the first memory cell transistor. The electrodes connected to the bit line and connected to each other of the second and third ferroelectric capacitors are both connected to the second ferroelectric capacitor.
The first and second memory cell transistors are connected to a common word line, and the bit line of the first ferroelectric capacitor is connected to the second bit line via the memory cell transistor. A ferroelectric memory in which a first plate line is connected to a non-electrode side and a second plate line is connected to an electrode to which the bit line of the third ferroelectric capacitor is not connected. Storing the data read to the first bit line by setting the polarization direction of the first ferroelectric capacitor, and the polarization direction of the third ferroelectric capacitor. , And the step of storing the data to be read out to the second bit line.

According to a seventh aspect of the present invention, there is provided the operation control method of the ferroelectric memory according to the sixth aspect, wherein a voltage for turning on the first and second memory cell transistors is applied to the word line. In the state, the first plate line and the first
The polarization direction of the first and third ferroelectric capacitors is set by applying a voltage between the first and third bit lines and between the second plate line and the second bit line. I have.

The invention according to claim 8 relates to the method of controlling a ferroelectric memory according to claim 6, wherein the first and second memory cell transistors are connected to the word line after performing the data reading. With a voltage that turns off
By applying a voltage between the first plate line and the second plate line in a direction opposite to the direction of data reading, the direction of polarization from the first ferroelectric capacitor to the third ferroelectric capacitor is changed. After the step of changing the size, the polarization directions of the first and third ferroelectric capacitors are set by the method according to claim 7.

According to a ninth aspect of the present invention, there is provided a memory cell comprising first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors. And the electrodes of the three ferroelectric capacitors connected to each other on the side connected to each other of the first and second ferroelectric capacitors are both connected via the first memory cell transistor to the first electrode. The electrodes connected to the bit line and connected to each other of the second and third ferroelectric capacitors are both connected to the second ferroelectric capacitor.
The first and second memory cell transistors are connected to a common word line, and the bit line of the first ferroelectric capacitor is connected to the second bit line via the memory cell transistor. A ferroelectric memory in which a first plate line is connected to a non-electrode, and a second plate line is connected to an electrode to which the bit line of the third ferroelectric capacitor is not connected. In the operation control method of (1), one of the first and second plate lines is grounded, a voltage is applied between the first and second plate lines, and a voltage is applied to the word line. By applying a voltage at which the first and second memory cell transistors are turned on, a voltage change corresponding to the written data is changed by the first memory cell transistor.
And reading the data including the step of causing the data to occur on the second bit line.

According to a tenth aspect of the present invention, there is provided the operation control method for the ferroelectric memory according to the ninth aspect, wherein a voltage change occurring in the first and second bit lines is fixed by a differential sense amplifier. The method is characterized in that it includes a step of detecting a potential difference from another bit line which is precharged to a voltage.

The invention according to claim 11 relates to the method of controlling operation of a ferroelectric memory according to claim 10, wherein a bit used for detecting a potential difference between one of the first and second bit lines is provided. As a voltage value for precharging a line, a bit line used to detect a potential difference between the other bit line and approximately 1/3 of a voltage applied between the first plate line and the second plate line is used. Is characterized in that approximately 2/3 of the voltage applied between the first plate line and the second plate line is used as the voltage value for pre-charging.

According to a twelfth aspect of the present invention, there is provided a memory cell comprising first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors. And the electrodes of the first and second ferroelectric capacitors, which are connected to each other, are both connected to the first ferroelectric capacitor via the first memory cell transistor. The electrodes of the second and third ferroelectric capacitors that are connected to each other are connected to a second bit line via the second memory cell transistor, and the first and third ferroelectric capacitors are connected to a second bit line. And the second memory cell transistor is connected to a common word line, the first plate line is connected to an electrode of the first ferroelectric capacitor on the side to which the bit line is not connected, and the third memory cell transistor is connected to the third word line. The ferroelectric capacitor bit line is not connected. According to a method of controlling operation of a ferroelectric memory in which a second plate line is connected to an electrode on the side of the first or second plate line after the data reading, Making the plate line of the same potential as the plate line that is not grounded, and then grounding the first and second plate lines;
Then, the data is rewritten, including the step of grounding the first and second bit lines.

According to a thirteenth aspect of the present invention, there is provided a memory cell comprising first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors. And the electrodes of the three ferroelectric capacitors connected to each other on the side connected to each other of the first and second ferroelectric capacitors are both connected via the first memory cell transistor to the first electrode. The electrodes of the second and third ferroelectric capacitors that are connected to each other are connected to a second bit line via the second memory cell transistor, and the first and third ferroelectric capacitors are connected to a second bit line. And the second memory cell transistor is connected to a common word line, the first plate line is connected to the electrode of the first ferroelectric capacitor on the side not connected to the bit line, and the third ferroelectric capacitor is connected to the third word line. No bit line of ferroelectric capacitor is connected A method of controlling operation of a ferroelectric memory in which a second plate line is connected to an electrode on the side of the first and second memory cell transistors with respect to the word line after performing the data reading. By applying a voltage between the first plate line and the second plate line in a direction opposite to that at the time of data reading with a voltage to turn off the first ferroelectric capacitor, After changing the polarization direction and the magnitude of the ferroelectric capacitor, the grounded plate line of the first or second plate line is made the same as the non-grounded plate line. Data rewriting is performed, including the steps of setting a potential, then grounding the first and second plate lines, and then grounding the first and second bit lines. I have.

According to a fourteenth aspect of the present invention, there is provided a ferroelectric memory for storing data by utilizing the polarization phenomenon of a ferroelectric, wherein a ferroelectric capacitor which is one more than the number of bits of the stored data is used. Thus, it is characterized in that it is configured to store data of 2 bits or more.

According to a fifteenth aspect of the present invention, there is provided a ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric, and more than one memory cell transistor and one more than the memory cell transistor. A memory cell is formed by the ferroelectric capacitors connected in series, and among the ferroelectric capacitors, the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors are connected to each other. Both electrodes are connected to the k-th bit line via the k-th memory cell transistor, a common word line is connected to the gate electrode of the memory cell transistor, and the bit of the first ferroelectric capacitor is connected. The first plate line is connected to the electrode to which the line is not connected, and the second plate line is connected to the electrode to which the bit line of the final ferroelectric capacitor is not connected. It is characterized in that there.

According to a sixteenth aspect of the present invention, a memory cell comprises a plurality of memory cell transistors and one more ferroelectric capacitor connected in series with the memory cell transistor. Of the electrodes, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitor that are connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. The common word line is connected to the gate electrode of the memory cell transistor, the first plate line is connected to the electrode of the first ferroelectric capacitor to which the bit line is not connected, and the last The present invention relates to a method for controlling the operation of a ferroelectric memory in which a second plate line is connected to an electrode of a ferroelectric capacitor to which a bit line is not connected. By applying a voltage between all the plate lines and the bit lines while applying a voltage to turn on the transistor, data is written by setting the polarization direction of the ferroelectric capacitor. .

According to a seventeenth aspect of the present invention, the memory cell comprises a plurality of memory cell transistors and one more ferroelectric capacitor connected in series with the memory cell transistor. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitor that are connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. A common word line is connected to the gate electrode of the memory cell transistor, a first plate line is connected to the electrode of the first ferroelectric capacitor to which the bit line is not connected, and According to the operation control method of the ferroelectric memory in which the second plate line is connected to the electrode of the ferroelectric capacitor to which the bit line of the ferroelectric capacitor is not connected, after reading the data, By applying a voltage between the first plate line and the second plate line in a direction opposite to that at the time of data reading while applying a voltage to turn off the memory cell transistor to the read line, After the step of changing the direction and magnitude of the polarization of the ferroelectric capacitor, the data is written by setting the polarization direction of the ferroelectric capacitor by the method of claim 16.

According to the invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series with respect to the memory cell transistor. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitor that are connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. A common word line is connected to the gate electrode of the memory cell transistor, a first plate line is connected to the electrode of the first ferroelectric capacitor to which the bit line is not connected, and The first and second embodiments relate to an operation control method for a ferroelectric memory in which a second plate line is connected to an electrode of the ferroelectric capacitor to which the bit line is not connected.
One of the plate wires is grounded and the first
Voltage between the plate line and the second plate line,
By applying a voltage to turn on the first and second memory cell transistors to the word line, data reading is performed including a step of causing a voltage change according to written data to all bit lines. It is characterized by performing.

The invention according to claim 19 relates to the operation control method of the ferroelectric memory according to claim 18, wherein a voltage change occurring in the first and second bit lines is fixed by a differential sense amplifier. The method is characterized in that it includes a step of detecting a potential difference from another bit line which is precharged to a voltage.

According to a twentieth aspect of the present invention, there is provided the operation control method for a ferroelectric memory according to the nineteenth aspect, wherein a bit line used for detecting a potential difference from the k-th second bit line is precharged. As a voltage value, a voltage applied between the first plate line and the second plate line is approximately k / (N +
1) is used.

According to a twenty-first aspect of the present invention, a memory cell comprises a plurality of memory cell transistors and one more ferroelectric capacitor connected in series to the memory cell transistors. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitor that are connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. A common word line is connected to the gate electrode of the memory cell transistor, a first plate line is connected to the electrode of the first ferroelectric capacitor to which the bit line is not connected, and According to the operation control method of the ferroelectric memory in which the second plate line is connected to the electrode of the ferroelectric capacitor to which the bit line is not connected, after reading the data, Bringing the grounded plate line of the first or second plate line to the same potential as the non-grounded plate line, and then grounding the first and second plate lines And thereafter, grounding all the bit lines.

According to a twenty-second aspect of the present invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series with the memory cell transistor. Of the electrodes, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitor that are connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. The common word line is connected to the gate electrode of the memory cell transistor, the first plate line is connected to the electrode of the first ferroelectric capacitor to which the bit line is not connected, and the last According to the operation control method of the ferroelectric memory in which the second plate line is connected to the electrode of the ferroelectric capacitor to which the bit line of the ferroelectric capacitor is not connected, after reading the data, By applying a voltage between the first plate line and the second plate line in a direction opposite to that during data reading in a state where a voltage for turning off the memory cell transistor is applied to the word line, After the step of changing the polarization direction and the size of the ferroelectric capacitor, the grounded plate line of the first or second plate line is set to the same potential as the non-grounded plate line. , And then grounding the first and second plate lines, and then grounding all the bit lines.

According to a twenty-third aspect of the present invention, a memory cell comprising first, second and third ferroelectric capacitors and first and second memory cell transistors is formed on a semiconductor substrate. The first MIS transistor and the second MIS transistor which operate as the first memory cell transistor and which are formed in desired regions on the semiconductor substrate, respectively. The second MIS transistor is covered with a first interlayer insulating film, and the first and second MIS transistors are respectively connected to the element regions of the first and second MIS transistors on the first interlayer insulating film. A bit wiring is formed, a second interlayer insulating film is formed on the first interlayer insulating film so as to cover the first and second bit wirings, and the second interlayer insulating film is formed on the second interlayer insulating film. 1, the ferroelectric capacitor of the second and third are formed, first, is characterized in that the wiring structure for connecting the second and third ferroelectric capacitor in series is formed.

According to a twenty-fourth aspect of the present invention, there is provided the ferroelectric memory cell structure according to the twenty-third aspect, wherein a part of the wiring structure is connected to an element region of the first and second MIS transistors. Is formed.

The invention according to claim 25 relates to the ferroelectric memory cell structure according to claim 23 or 24, wherein
A third interlayer insulating film is formed on the second interlayer insulating film so as to cover the second and third ferroelectric capacitors, and the wiring structure is formed in the third interlayer insulating film. Features.

The invention according to claim 26 is the invention according to claims 23 and 2
24. The ferroelectric memory cell structure according to 4 or 25, wherein the first, second, and third ferroelectric capacitors each have a stacked structure in which an upper electrode and a lower electrode are formed on both surfaces of a ferroelectric film. It is characterized by becoming.

The invention according to claim 27 relates to a method of manufacturing a ferroelectric memory cell structure, wherein a first MIS transistor and a second MIS transistor are formed in a desired region of a semiconductor substrate, and the semiconductor substrate is formed. A transistor forming step of forming a first interlayer insulating film so as to cover the first and second MIS transistors on the first interlayer insulating film so as to be connected to the element regions of the first and second MIS transistors, respectively; Forming a bit wiring, and forming the first
And forming a second interlayer insulating film on the first interlayer insulating film so as to cover the second bit wiring, and then forming first, second and third ferroelectrics on the second interlayer insulating film. Forming a ferroelectric capacitor for forming a body capacitor; and forming a third ferroelectric capacitor on the second interlayer insulating film so as to cover the first, second, and third ferroelectric capacitors.
Forming a wiring structure for connecting the first, second, and third ferroelectric capacitors in series to the third interlayer insulating film after forming the third interlayer insulating film. Features.

According to a twenty-eighth aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory cell structure according to the twenty-seventh aspect, wherein the step of forming the ferroelectric capacitor comprises the steps of: After sequentially forming the conductive films to form a laminated film, the laminated film is patterned into a desired shape.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. The description will be made specifically using an embodiment. FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory according to a first embodiment of the present invention. FIG. 2 is a timing chart for explaining a first operation control method of the ferroelectric memory. FIG. 3 is a timing chart for explaining a second operation control method of the ferroelectric memory,
FIG. 4 is a sectional view showing a ferroelectric memory cell structure used in the ferroelectric memory. FIGS. 5 and 6 are process diagrams showing a method of manufacturing the ferroelectric memory cell in the order of steps.
8 is a sectional view showing another example of a ferroelectric memory cell structure used in the ferroelectric memory. As shown in FIG. 1, the ferroelectric memory 1 of this example includes first to third three ferroelectric capacitors 39 to 41 connected in series and two MOS transistors (memory cell transistors) 2.
And a memory cell 2 configured to store 2-bit data. The gate electrodes of the first MOS transistor 25 and the second MOS transistor 26 of the memory cell 2 are commonly connected to a word line WL1. As will be described later, a drain region 32 serving as one electrode of the first MOS transistor 25
Is connected to the bit line BL1A through the plug conductor 51 and the bit wiring 37, while the source region 31 serving as the other electrode of the transistor 25 is connected to the first ferroelectric capacitor 39 through the plug conductor 57 and the local wiring 42. Commonly connected to the second ferroelectric capacitor 40.

As will be described later, a source region 33 serving as one electrode of the second MOS transistor 26 is connected to a bit line BL through a plug conductor 52 and a bit line 38.
1B, the drain region 34 serving as the other electrode of the transistor 26 is commonly connected to the second ferroelectric capacitor 40 and the third ferroelectric capacitor 41 through the plug conductor 58 and the local wiring 43. It is connected. Further, the first to third ferroelectric capacitors 39 to 41 connected in series
The first ferroelectric capacitor 39 is connected to the plate line PL1A, and the third ferroelectric capacitor 41 is connected to the plate line PL1A.
B.

Similarly, the other memory cells 3 include first to third ferroelectric capacitors 9 to 11 connected in series and 2
MOS transistors (memory cell transistors)
5 and 6 are configured to store 2-bit data. Here, each of the ferroelectric capacitors 9 to 11 and each of the transistors 5 and 6 are substantially the same as the above-described ferroelectric capacitors 39 to 51 and the transistors 25 and 26, respectively. The bit lines BL2B and BL3A are connected to the differential sense amplifier 23.

The bit line BL1A is connected to the differential sense amplifier 2
1 and the bit line BL1B is connected to the differential sense amplifier 22. A reference potential is applied from the differential sense amplifier 21 to the bit line BL1A through the bit line BL0B, and a reference potential is applied from the differential sense amplifier 22 to the bit line BL1B through the bit line BL2A. Here, bit lines BL0B and B
A memory cell connected to the word line WL1 cannot be connected to L2A. For example, as shown in FIG.
The memory cell 3 connected to the bit line BL2A is not connected to the word line WL1, but is connected to the word line WL2.

Next, a first operation control method of the ferroelectric memory of this example will be described with reference to the timing chart of FIG. The description will be made in the order of the data read method and the data rewrite method. In an initial state, the word line WL1, the plate lines PL1A and PL1B, and the bit lines BL0B, BL1A, BL1B and BL2A are each grounded. First, at time t1, the potential of the plate line PL1A is raised to Vcc (power supply potential).
Next, at time t2, the bit lines BL0B and BL1
A potential is increased to Vcc / 3, and at the same time, bit line B
The potentials of L1B and BL2A are precharged to 2 Vcc / 3. Here, before raising the potential of the plate line PL1A, the bit lines BL0B, BL1A, BL1B, and BL2A may be precharged. In this case, the plate line PL1A and the bit lines BL0B, BL1A, BL
1B and BL2A, and when the potential of the plate line PL1A rises, the precharged bit line BL
0B, BL1A, BL1B and BL2A may change, so that the plate line PL1
It is desirable to raise the potential of A first.

Next, at time t3, the word line WL1
Is raised higher than the value obtained by adding the threshold voltage of the memory cell transistor to Vcc. Thereby, according to the data written in the first to third ferroelectric capacitors 39 to 41, the precharged bit lines BL1A and BL1A
Whether the potential of 1B rises as in a and c, respectively,
It descends like b and d. Then, at time t4,
Bit lines BL0B and B0B are provided by differential sense amplifier 21.
The potential difference between L1A is amplified, and the differential sense amplifier 22 amplifies the potential difference between bit lines BL1B and BL2A. As a result, the bit lines BL1A and BL1B
Are tied to either Vcc or ground, respectively. Thus, the data read operation ends.

Next, as described above, each ferroelectric capacitor 3
According to the data written in 9 to 41, the potentials of the precharged bit lines BL1A and BL1B are respectively
The reason for rising as shown by a and c or falling as shown by b and d will be described. The data written in each of the ferroelectric capacitors 39 to 41 has two states depending on the direction of the remanent polarization of each of the ferroelectric capacitors 39 to 41. That is, the bit lines BL1A and BL1B and the plate line P
When a voltage is applied to each of the ferroelectric capacitors 39 to 41 connected in series using the L1A and PL1B and the voltage is removed, each of the ferroelectric capacitors 3 to 3 is applied according to the principle of the ferroelectric memory.
Remanent polarization occurs in 9 to 41. Here, for example, data obtained when a voltage is applied in a state where the bit line side has a higher potential than the plate line side is 1, and conversely, a case where a voltage is applied in a state where the bit line side has a lower potential than the plate line side The potential obtained on the bit lines BL1A and BL1B according to the data written in the ferroelectric capacitors 39 to 41 is described assuming that the obtained data is 0.

(1) Data 1 is written in the first ferroelectric capacitor 39 and data 1 is written in the third ferroelectric capacitor 41. In this case, the potential of the plate line PL1A is raised. A voltage is applied to the first to third ferroelectric capacitors 39 to 41, and the direction of the voltage is applied to the third ferroelectric capacitor 41 in a direction opposite to that at the time of writing. The direction is the same for the dielectric capacitor 39. by the way,
The ferroelectric capacitor has a property that when a voltage is applied in a direction opposite to that in which remanent polarization is generated, the amount of polarization change is larger than when a voltage is applied in the same direction. That is, when a voltage is applied in the opposite direction, the effective capacitance value becomes larger than when a voltage is applied in the same direction. Therefore, the third ferroelectric capacitor 41 is connected to the first ferroelectric capacitor 39.
It can be considered that the effective capacitance value is larger than. Second
Since no voltage is applied at the time of writing, the effective capacitance value cannot be specified for the ferroelectric capacitor 40 of the third ferroelectric capacitor 40. Can only take values less than the capacitance value of.

When a voltage is applied to the first to third ferroelectric capacitors 39 to 41 connected in series, the voltage applied to one of the ferroelectric capacitors decreases as the capacitance value increases. Therefore, the first to third ferroelectric capacitors 39 to
The voltage applied to the third ferroelectric capacitor 41 is lower and the voltage applied to the first ferroelectric capacitor 39 is higher than when all 41 have the same effective capacitance value.
When Vcc is applied between the plate lines PL1A and PL1B, if the effective capacitance values of the first to third ferroelectric capacitors 39 to 41 are equal, a voltage of Vcc / 3 is applied to each. In this case, a voltage lower than Vcc / 3 is applied to the third ferroelectric capacitor 41, and a voltage higher than Vcc / 3 is applied to the first ferroelectric capacitor 39. Therefore, the potential read to the bit line BL1A becomes higher than Vcc / 3 as shown by a, and the potential read to the bit line BL1B becomes 2Vcc as shown by c.
/ 3.

(2) When data 0 is written to the first ferroelectric capacitor 39 and data 1 is written to the third ferroelectric capacitor 41 In this case, the data is stored in the second ferroelectric capacitor 40 during writing. Also, a voltage is applied, and the direction of the voltage is reversed in the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41. Therefore, by increasing the potential of the plate line PL1A, the direction of the voltage applied from the third ferroelectric capacitor 41 to the first ferroelectric capacitor 39 is changed to the third ferroelectric capacitor 41.
To the second ferroelectric capacitor 40 in the same direction, and to the second ferroelectric capacitor 40 in the same direction.
9 is in the opposite direction. Therefore, the effective capacitance value is determined by the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41.
Are equal to each other, and from these values, the second ferroelectric capacitor 4
Since the value of 0 becomes smaller, the voltage applied to the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41 becomes lower than Vcc / 3. Therefore, the potential read to the bit line BL1A becomes lower than Vcc / 3 as shown by b, and the potential read to the bit line BL1B becomes 2Vcc as shown by c.
/ 3.

(3) Data 1 is written to the first ferroelectric capacitor 39 and data 0 is written to the third ferroelectric capacitor 41. In this case, the second ferroelectric capacitor 40 is written at the time of writing. Also, a voltage is applied, and the direction of the voltage is reversed in the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41. Therefore, by increasing the potential of the plate line PL1A, the direction of the voltage applied from the third ferroelectric capacitor 41 to the first ferroelectric capacitor 39 is changed to the third ferroelectric capacitor 41.
In the same direction as that during writing, in the same direction as the second ferroelectric capacitor 40, and in the first direction.
9 is in the same direction. Therefore, the effective capacitance value is determined by the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41.
Are equal to each other, and from these values, the second ferroelectric capacitor 4
Since the value of 0 becomes larger, the voltage applied to the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41 becomes higher than Vcc / 3. Therefore, the potential read to the bit line BL1A becomes higher than Vcc / 3 as shown by a, and the potential read to the bit line BL1B becomes 2Vcc as shown by d.
/ 3.

(4) Data 0 is written in the first ferroelectric capacitor 39 and data 0 is written in the third ferroelectric capacitor 41. In this case, the data is written to the second ferroelectric capacitor 40 at the time of writing. No voltage is applied. Therefore, by increasing the potential of the plate line PL1A, the third ferroelectric capacitor 41
, The direction of the voltage applied to the first ferroelectric capacitor 39 is in the same direction as that during writing to the third ferroelectric capacitor 41 and in the opposite direction to the first ferroelectric capacitor 39. become.
Therefore, the effective capacitance value is the first ferroelectric capacitance 39
The third ferroelectric capacitor 41 is smaller than the first ferroelectric capacitor 39, and the value of the second ferroelectric capacitor 40 is lower than the capacitance value of the first ferroelectric capacitor 39. Since the voltage becomes higher than the capacitance value, the voltage applied to the first ferroelectric capacitor 39 becomes lower than Vcc / 3, and the third ferroelectric capacitor 41
Is higher than Vcc / 3. for that reason,
The potential read to the bit line BL1A is Vc like b.
The potential becomes lower than c / 3, and the potential read to the bit line BL1B becomes lower than 2 Vcc / 3 as shown by d.

Next, a data rewriting method will be described. In order to rewrite data in the first to third ferroelectric capacitors 39 to 41, the potential of the plate line PL1B is raised to Vcc at time t5, and then the plate lines PL1A and PL1B are grounded at time t7. I do. Next, at time t8, the bit lines BL0B, BL1A,
BL1B and BL2A are grounded. As a result, the time t
5 to time t7 or from time t7 to time t
8 between the plate line PL1A and the bit line BL1A and between the plate line PL1B and the bit line BL1B, that is, the first ferroelectric capacitor 39 and the third ferroelectric capacitor 39 in accordance with the data to be rewritten. Vcc is applied between the ferroelectric capacitors 41.

Therefore, at time t8, V is applied between the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41.
Since cc is not added, data retained by the remanent polarization is written. That is, when the read data is 1, the bit line potential is Vc
Therefore, no voltage is applied to the ferroelectric capacitor from time t5 to time t7, and the ferroelectric capacitor is kept in a state where the potential on the bit line side is high from time t7 to time t8. And the voltage is removed at time t8, so that data 1 is written.

When the read data is 0, the bit line potential is at the ground, so that the time t5
From time t7 to time t7, a voltage is applied to the ferroelectric capacitor in a state where the potential on the plate line side is high, and the voltage is removed at time t7, so that data 0 is written. Finally, at time t9, the word line WL1
Is grounded, the data rewrite operation ends.

When writing data,
At time t6, the potential corresponding to the data is set to bit line BL.
1A and BL1B, the same operation as data rewriting is performed after time t7.

Next, a second operation control method of the ferroelectric memory of this example will be described with reference to the timing chart of FIG. Note that the data read operation performed up to time t4 is substantially the same as the first operation control method of FIG. Thereafter, when no voltage is applied to the second ferroelectric capacitor 40 at the time of writing, in order to make the effective capacitance value of the second ferroelectric capacitor 40 closer to the optimum value, the word The line WL1 is grounded. Next, at time t6, the plate line PL1A is grounded, the potential of the plate line PL1B is raised to Vcc, and a voltage is applied to the first to third ferroelectric capacitors 39 to 41. Next, at time t7, the plate line PL1
After the potential of A is raised to Vcc, the voltage is not applied to each of the ferroelectric capacitors 39 to 41, at time t8, the potential of the word line WL1 is changed to Vcc, and the threshold voltage of the memory cell transistor is changed to Vcc. Raise higher than the added value.

Thereafter, from time t9 to time t12, substantially the same operation as the operation from time t6 to time t9 in the first operation control method of FIG. 2 is performed, thereby completing the data rewriting or data writing operation. I do.

As described above, according to the ferroelectric memory of this example, the bit line potential at the time of data reading is higher or lower than Vcc / 3 on one bit line BL1A according to data, Since the value of the other bit line BL1B is higher or lower than 2Vcc / 3, the reference potential for the bit line BL1A is set to Vcc / 3, and the reference potential for the bit line BL1B is set to 2Vcc / 3. Since the reference potential can be fixed, the reference potential always fixed to the optimum value can be used. Therefore, a data identification error due to a change in the reference potential does not occur. Further, according to the ferroelectric memory of this example, the first to third ferroelectric capacitors 39 to 41 connected in series, the two memory cell transistors 25,
26, and the memory cell 2 for storing 2-bit data, the memory cell occupied area required to store 1-bit data is equivalent to 1.5 ferroelectric capacitors. To decrease.

Next, a ferroelectric memory cell structure used in the ferroelectric memory of this example will be described with reference to FIG. As shown in FIG. 4, this ferroelectric memory cell structure has, for example, an N-type source region 31 and a drain region 32 which selectively become element regions in a part of a P-type silicon substrate 30.
Are formed, and the source region 31 and the drain region 3 are formed.
A gate electrode 35 made of polycrystalline silicon or the like is formed on a channel region between the gate electrode 2 and the gate oxide film 27 via a gate oxide film 27. The entire surface including the gate electrode 35 is covered with a first interlayer insulating film 47 made of a silicon oxide film or the like, and the first M
An OS transistor 25 is formed. Similarly, P
An N-type source region 33 and a drain region 34 which are selectively element regions are formed in the other part of the silicon substrate 30, and a gate oxide film is formed on a channel region between the source region 33 and the drain region 34. A gate electrode 36 made of polycrystalline silicon or the like is formed via. The entire surface including the gate electrode 36 is covered with a first interlayer insulating film 47 made of a silicon oxide film or the like, and a second MOS
A type transistor 26 is formed. These first and second MOS transistors 25 and 26 are used as memory cell transistors, respectively, as described above. Gate electrodes 35 and 36 are both connected to word line WL1. The N-type source region 31 and the N-type drain region 32, and the N-type source region 33 and the N-type drain region 34
Have substantially the same function and are interchangeable.

On the first interlayer insulating film 47, a first MO
A bit wiring 37 connected to the N-type drain region 32 of the S-type transistor 25 through the plug conductor 51;
A bit wiring 38 connected to the N-type source region 33 of the MOS transistor 26 through the plug conductor 52 is formed. The bit lines 37 and 38 are connected to the bit lines BL1A and BL1B, respectively, as described above.

The entire surface of the first interlayer insulating film 47 including the bit lines 37 and 38 is covered with a second interlayer insulating film 48 made of a silicon oxide film or the like. This second interlayer insulating film 4
8, a first ferroelectric capacitor 39, a second ferroelectric capacitor 40, and a third ferroelectric capacitor 41 are formed.
Each of the first to third ferroelectric capacitors 39 to 41 has a laminated structure including lower electrodes 39A to 41A, ferroelectric films 39B to 41B, and upper electrodes 39C to 41C. The lower electrodes 39A and 41A of the first and third ferroelectric capacitors 39 and 41 are connected to plate lines PL1A and PL1B, respectively.

The entire surface of the second interlayer insulating film 48 including the first to third ferroelectric capacitors 39 to 41 is covered with a third interlayer insulating film 49 made of a silicon oxide film or the like. The plug conductor 53 connected to the upper electrode 39C of the first ferroelectric capacitor 39, and the lower electrode 40A and the upper electrode 40C of the second ferroelectric capacitor 40 are connected to the third interlayer insulating film 49, respectively. Plug conductors 54 and 55 are formed, and a plug conductor 56 connected to the upper electrode 41C of the third ferroelectric capacitor 41 is formed. In addition, the first to third interlayer insulating films 47 to 4
The first MOS transistors 9 pass through the entire film thickness.
A plug conductor 57 connected to the N-type source region 31 of the type transistor 25 and a plug conductor 58 connected to the N-type drain region 34 of the second MOS transistor 26 are formed. On the third interlayer insulating film 49, a local wiring 42 connecting the plug conductors 53, 54 and 57 is formed.
Is formed, and each of the plug conductors 55, 56 and 58 is formed.
Are formed. Therefore, the first to third ferroelectric capacitors 39 to 41 are arranged so as to be connected to each other in series. The third interlayer insulating film 49 including the local wirings 42 and 43 is covered with a final insulating film 50 made of a silicon oxide film or the like, and is protected from an external atmosphere.

Next, a method of manufacturing the same ferroelectric memory cell structure will be described in the order of steps with reference to FIGS. First, as shown in FIG. 5A, for example, a well-known photolithography method, an ion implantation method, or the like is used for a part and another part of a P-type silicon substrate 30, respectively.
N-type source region 31 and drain region 32 selectively serving as element regions, N-type source region 33 and drain region 3
4. A gate oxide film 27 and a gate electrode 35, a gate oxide film 28 and a gate electrode 36 are formed. Next, a first interlayer insulating film 47 made of a silicon oxide film or the like is formed on the entire surface by a CVD method or the like, and first and second MOS transistors 25 and 26 are formed.

Next, as shown in FIG. 5B, the first MOS transistor 25 is formed by photolithography.
The first interlayer insulating film 47 on the N-type drain region 32 and the N-type source region 33 of the second MOS transistor 26
After forming contact holes in each contact hole, C
Plug conductors 51 and 52 are formed by burying polycrystalline silicon or the like by a VD method or the like. Next, after aluminum or the like is formed on the entire surface by CVD or the like, patterning is performed by photolithography to form plug conductors 51 and 5.
Bit wirings 37 and 38 are formed so as to be connected to 2 respectively.

Next, as shown in FIG. 6C, a second interlayer insulating film 48 made of a silicon oxide film or the like is formed on the entire surface by a CVD method or the like to cover the first interlayer insulating film 47. . Next, a first conductor film made of a polysilicon film or the like, a second conductor film made of a ferroelectric film, a polysilicon film, etc. are sequentially formed and laminated on the entire surface by a CVD method or the like, and then patterned. Thus, a first ferroelectric capacitor 39, a second ferroelectric capacitor 40, and a third ferroelectric capacitor 41 are formed. First
To the third ferroelectric capacitors 39 to 41 have a laminated structure including lower electrodes 39A to 41A, ferroelectric films 39B to 41B, and upper electrodes 39C to 41C, respectively.

Next, as shown in FIG. 6D, a third interlayer insulating film 49 made of a silicon oxide film or the like is formed on the entire surface by a CVD method or the like to cover the second interlayer insulating film 48. . Next, the upper electrode 39C of the first ferroelectric capacitor 39, the lower electrode 40A and the upper electrode 40C of the second ferroelectric capacitor 40, and the upper electrode of the third ferroelectric capacitor 41 by photolithography. A contact hole is formed in each of the third interlayer insulating films 49 on 41C. At the same time, the first to third interlayer insulating films 47 to 49 on the N-type source region 31 and the drain region 34 of the first and second MOS transistors 25 and 26 are so contacted as to penetrate the entire film thickness. Form a hole. Next, polycrystalline silicon or the like is buried in each contact hole by a CVD method or the like to form a plug conductor 5.
3 to 58 are formed respectively. Next, after aluminum or the like is formed on the entire surface by a CVD method or the like, patterning is performed by a photolithography method to form each of the plug conductors 53 and 54.
And a local wiring 43 connecting the plug conductors 55, 56 and 58.
To form Then, the local wiring 4 is formed by a CVD method or the like.
A final insulating film 50 made of a silicon oxide film or the like is formed on the third interlayer insulating film 49 including 2 and 43 to complete the ferroelectric memory cell structure of FIG.

FIG. 7 is a sectional view showing another example of a ferroelectric memory cell structure used in the ferroelectric memory of this embodiment. The structure of this ferroelectric memory cell structure is significantly different from that shown in FIG.
The point is that the wiring structure for connecting the three ferroelectric capacitors formed above in series is changed. That is, in this ferroelectric memory cell structure, as shown in FIG. The electrode 39A is connected to the local wiring 42 through the plug conductor 61. The upper electrode 39C of the first ferroelectric capacitor 39 is connected to the plate line PL1 through the plug conductor 62 and the local wiring 45.
A is connected.

The lower electrode 41A of the third ferroelectric capacitor 41
Are connected to the local wiring 43 through the plug conductor 66, and the plug conductor 64, the local wiring 44 and the plug conductor 6
3 is connected to the upper electrode 40C of the second ferroelectric capacitor 40. The upper electrode 41C of the third ferroelectric capacitor 41 is connected to the plate line PL1B through the plug conductor 65 and the local wiring 46. In order to manufacture this ferroelectric memory cell structure, it can be easily manufactured only by changing the laminated structure and the wiring pattern of each ferroelectric capacitor in the manufacturing steps of FIGS. 6 (c) and 6 (d). . Except for this, the structure is substantially the same as the above-described ferroelectric memory cell structure in FIG. Therefore, in FIG. 7, portions corresponding to the components in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 8 is a sectional view showing another example of a ferroelectric memory cell structure used in the ferroelectric memory of this example. The structure of this ferroelectric memory cell structure is significantly different from that shown in FIG.
The point is that the wiring structure for connecting the three ferroelectric capacitors formed above in series is changed. That is, in this ferroelectric memory cell structure, as shown in FIG. 8, the lower electrodes of the first ferroelectric capacitor 39 and the second ferroelectric capacitor 40 are a common electrode 39A. The electrode 39A is connected to the first MOS transistor 2 through the plug conductor 67.
5 is connected to the N-type source region 31. Also, the third
The lower electrode 41A of the ferroelectric capacitor 41 of FIG.
Is connected to the N-type drain region 34 of the second MOS transistor 26. Except for this, the structure is substantially the same as the ferroelectric memory cell structure of FIG. 7 described above.

As described above, according to the structure of this example, the first to third three ferroelectric capacitors 39 to 4 connected in series are connected.
1 and first and second two memory cell transistors 2
Since the memory cell 2 is configured by the memory cells 5 and 26 to store 2-bit data, the reference potential can be fixed in principle. Further, the area occupied by the memory cells required to store 1-bit data can be reduced to 1.5 ferroelectric capacitors. Therefore,
The area occupied by the memory cells required to store 1-bit data can be reduced without causing a data identification error due to a change in the reference potential.

Second Embodiment FIG. 9 is a circuit diagram showing a configuration of a ferroelectric memory according to a second embodiment of the present invention, and FIG. 10 illustrates a first operation control method of the ferroelectric memory. FIG. 11 is a timing chart for explaining a second operation control method of the ferroelectric memory. As shown in FIG. 9, the ferroelectric memory 20 of this example has a plurality of ferroelectric capacitors C (1) connected in series.
To C (N + 1) and a plurality of MOS transistors (memory cell transistors) Tr (1) to Tr (N). The gate electrodes of the MOS transistors Tr (1) to Tr (N) are commonly connected to a word line WL. One electrodes of the MOS transistors Tr (1) to Tr (N) are connected to bit lines BLT (1) to BLT (N), respectively, while the other electrodes of the transistors Tr (1) to Tr (N) are connected to the bit lines BLT (1) to BLT (N), respectively. The electrodes are commonly connected to both adjacent ferroelectric capacitors.

The ferroelectric capacitor C at one end of the plurality of ferroelectric capacitors C (1) to C (N + 1) connected in series
(1) is connected to the second plate line PLB, and the ferroelectric capacitor C (N + 1) at the other end is connected to the first plate line PLA.
It is connected to the. Bit lines BLN (1) to BLN
(N) is supplied with a reference potential, and each bit line B
LN (1) to BLN (N) and each bit line BLT (1)
To BLT (N) are differential sense amplifiers 71 (7
1 (1) to 71 (N)). Here, when a certain value k is an integer from (1 to N), for example, a plurality of ferroelectric capacitors C (k) to C
The common contact of (k + 1) is a MOS transistor Tr
That is, it is connected to the bit line BLT (k) via (k).

Next, referring to the timing chart of FIG.
A first operation control method of the ferroelectric memory of this example will be described. The description will be made in the order of the data read method and the data rewrite method. Initially, the word line WL, plate lines PLA and PLB, bit line B
LT (1) to BLT (N) and BLN (1) to BLN
(N) are each grounded. First, at time t1, the potential of the plate line PLA is raised to Vcc, and then at time t2, the bit lines BLT (k) and BL
The potential of N (k) is precharged to kVcc / (N + 1). Here, before raising the potential of the plate line PLA, the bit lines BLT (k) and BLN (k) may be precharged. In this case, the plate line PLA and the bit line BLT (k ) And BLN (k), and the potential of the precharged bit lines BLT (k) and BLN (k) may change when the potential of the plate line PLA rises. It is desirable to raise the potential of the plate line PLA first.

Next, at time t3, the potential of word line WL is raised to a value higher than the value obtained by adding the threshold voltage of the memory cell transistor to Vcc. Thereby, the precharged bit line BLT (k) rises as shown by e or falls as shown by f according to the data written in the ferroelectric capacitors C (1) to C (N). . Thereafter, at time t4, the bit lines BLT (k) and BLN
By amplifying the potential difference between the bit lines BLT (k) and BLN (k) by the differential sense amplifier 71 coupled to the set (k), the signal generated on the bit line BLT (k) is changed to Vcc. Or restrain to either ground. Thus, the data read operation ends.

Next, a data rewriting method will be described. In order to rewrite data in the ferroelectric capacitors C (1) to C (N + 1), at time t5, the potential of the plate line PLB is raised to Vcc, and then at time t7, the plate lines PLA and PLB are grounded. I do. Next, at time t8, the bit lines BLT (k) and BLN
(K) is grounded. Thereby, from time t5 to time t7
, Or between time t7 and time t8, the voltage Vcc is applied to the ferroelectric capacitors C (1) to C (N) in accordance with the data to be rewritten,
At time t8, when no voltage is applied to the ferroelectric capacitors C (1) and C (N), data held by the remanent polarization is written. Further, a potential difference between BL (k-1) and BL (k) is added to the ferroelectric capacitor C (k) (k = 2 to (N-1)) depending on data. Finally, at time t9, the word line WL is grounded, thereby completing the data rewriting operation.

When writing data,
At time t6, the potential corresponding to the data is set to bit line BL.
(K), after time t7, the same operation as data rewriting is performed.

Next, referring to the timing chart of FIG.
A second operation control method of the ferroelectric memory of this example will be described. Note that the data read operation performed up to time t4 is substantially the same as the first operation control method in FIG. 10, and a description thereof will be omitted. Thereafter, when no voltage is applied to the ferroelectric capacitors C (1) to C (N) at the time of writing, the effective capacitance values of the ferroelectric capacitors C (1) to C (N) are set to more optimal values. At time t5, the word line WL is grounded so as to be close. Next, at time t6, the plate line PLA is grounded, and the potential of the plate line PLB is raised to Vcc, so that the ferroelectric capacitors C (1) -C
Apply voltage to (N). Next, at time t7, the potential of the plate line PLA is raised to Vcc,
After the state in which no voltage is applied to the ferroelectric capacitors C (1) to C (N), at time t8, the potential of the word line WL is set higher than the value obtained by adding the threshold voltage of the memory cell transistor to Vcc. To raise.

Thereafter, from time t9 to time t12, substantially the same operation as the operation from time t6 to time t9 in the first operation control method of FIG. 10 is performed, thereby completing the data rewriting or data writing operation. I do.

As described above, according to the structure of this embodiment, substantially the same effects as those described in the first embodiment can be obtained.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like that do not depart from the gist of the present invention. Is also included in the present invention. For example, the bit wiring of the ferroelectric memory cell structure used in the ferroelectric memory is not limited to the example arranged at the lower position of the three ferroelectric capacitors, but may be in the same layer as the local wiring or plate line, or in the interlayer insulating film. May be arranged at a position higher than that. Each interlayer insulating film is not limited to a silicon oxide film, but a BSG (Boro-Silicate Glass) film and a PSG (Phosph
o-Silicate Glass) film, BPSG (Boro-Phospho-Silica)
Other insulating films such as a (te Glass) film can be used.

The gate insulating film is made of an oxide film (Oxide Fi
Not limited to (lm), a nitride film (Nitride Film) may be used, or a double film structure of an oxide film and a nitride film may be used. That is, as long as the transistor is a MIS (Metal Insulator Semiconductor) transistor, the transistor is not limited to a MOS transistor but may be a MNS (Metal Nitride Semiconductor) transistor, or an MNOS (Metal Nitride Oxi).
de Semiconductor) type transistor. Further, the conductivity type of the semiconductor substrate or each semiconductor region may be reversed between the P type and the N type. That is, the present invention can be applied not only to the N-channel type but also to a P-channel type MIS transistor.
In addition, the materials of the insulating films, the conductor films, and the like, the film forming methods, and the like are merely examples, and can be changed according to the application, purpose, and the like.

[0081]

As described above, according to the ferroelectric memory and the control method thereof and the ferroelectric memory cell structure and the control method of the present invention, three ferroelectric capacitors connected in series and two Since a unit memory cell is formed by the memory cell transistors to store 2-bit data, the reference potential can be fixed in principle. Further, the area occupied by the unit memory cells required to store one-bit data can be reduced to 1.5 ferroelectric capacitors. Therefore, without causing a data identification error due to a change in the reference potential,
The area occupied by unit memory cells required to store one-bit data can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a first operation control method of the ferroelectric memory.

FIG. 3 is a timing chart for explaining a second operation control method of the ferroelectric memory.

FIG. 4 is a sectional view showing a ferroelectric memory cell structure used in the ferroelectric memory.

FIG. 5 is a process chart showing a method of manufacturing the ferroelectric memory cell structure in the order of steps.

FIG. 6 is a process chart showing a method of manufacturing the ferroelectric memory cell structure in the order of steps.

FIG. 7 is a sectional view showing another example of a ferroelectric memory cell structure used in the ferroelectric memory.

FIG. 8 is a sectional view showing another example of a ferroelectric memory cell structure used in the ferroelectric memory.

FIG. 9 is a circuit diagram showing a configuration of a ferroelectric memory according to a second embodiment of the present invention.

FIG. 10 is a timing chart illustrating a first operation control method of the ferroelectric memory.

FIG. 11 is a timing chart for explaining a second operation control method of the ferroelectric memory.

FIG. 12 is a circuit diagram showing a conventional ferroelectric memory.

FIG. 13 is a circuit diagram showing a conventional ferroelectric memory.

[Explanation of symbols]

1,20 ferroelectric memory 2,3 memory cell 21,22,23,71,71 (1) -71 (N)
Differential sense amplifiers 25, 26, Tr (1) to Tr (N) MOS transistors (memory cell transistors) 27, 28 Gate oxide films 31, 33 Source regions 32, 34 Drain regions 35, 36 Gate electrodes 37, 38 Bit wiring 39 First ferroelectric capacitor 40 Second ferroelectric capacitor 41 Third ferroelectric capacitor 42 to 46 Local wiring 47 First interlayer insulating film 48 Second interlayer insulating film 49 Third interlayer Insulating film 50 Final insulating film 51 to 58, 61 to 68 Plug conductor C (1) to C (N + 1) Ferroelectric capacitor WL1, WL2, WL Word line BL0B, BL1A, BL1B, BL2A, BL2B,
BLT (1) to BLT (N), BLN (1) to BLN
(N) Bit line PL1A, PL1B, PL2A, PL2B, PLA, P
LB plate wire

Claims (28)

[Claims] 1. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, wherein two bits of data are stored using three ferroelectric capacitors. A ferroelectric memory characterized by the above-mentioned. 2. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, wherein a memory cell including three ferroelectric capacitors and two memory cell transistors is provided. A ferroelectric memory, comprising: 3. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, comprising three first, second and third ferroelectric capacitors connected in series. , A first and second two memory cell transistors constitute a memory cell, and of the three ferroelectric capacitors, the side of the first and second ferroelectric capacitors which is connected to each other Are connected to a first bit line via the first memory cell transistor, and the second
The electrodes connected to each other of the third and third ferroelectric capacitors are both connected to a second bit line via the second memory cell transistor, and the first and second memory cell transistors are commonly used. A ferroelectric memory, wherein the ferroelectric memory is connected to a word line. 4. An electrode to which the bit line of the first ferroelectric capacitor is not connected is connected to a first plate line, and a bit line of the third ferroelectric capacitor is connected. 4. The ferroelectric memory according to claim 3, wherein a second plate line is connected to the electrode on the non-existing side. 5. A first reference potential applying bit line corresponding to the first bit line and a second reference potential applying bit line corresponding to the second bit line are provided.
Are connected to a first differential sense amplifier, and the second bit line and the second reference potential applying bit line are connected to a second differential sense amplifier. 5. The ferroelectric memory according to claim 3, wherein the ferroelectric memory is connected to an amplifier. 6. A memory cell is constituted by first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors.
Of the ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors that are connected to each other are both connected to the first bit line via the first memory cell transistor; The electrodes of the second and third ferroelectric capacitors that are connected to each other are connected to a second bit line via the second memory cell transistor, and the first and second memory cells are connected to each other. A transistor is connected to a common word line, a first plate line is connected to an electrode to which the bit line of the first ferroelectric capacitor is not connected, and a bit of the third ferroelectric capacitor is connected. An operation control method for a ferroelectric memory in which a second plate line is connected to an electrode to which a line is not connected, wherein the polarization direction of the first ferroelectric capacitor is set. Data read to the first bit line And writing data read out to the second bit line by setting a polarization direction of the third ferroelectric capacitor. Control method for a ferroelectric memory. 7. The method according to claim 1, wherein the first and second lines are connected to the word line.
Applying a voltage between the first plate line and the first bit line and between the second plate line and the second bit line in a state where a voltage for turning on the memory cell transistor is applied. 7. The method according to claim 6, wherein the polarization directions of the first and third ferroelectric capacitors are set by the following. 8. After performing the data reading, the first and second memory cell transistors are turned off in a state in which a voltage to turn off the first and second memory cell transistors is applied to the word line. After applying a voltage between the plate line and the second plate line to change the direction and magnitude of the polarization of the first ferroelectric capacitor to the third ferroelectric capacitor, Item 7. The first method according to Item 7,
7. The operation control method for a ferroelectric memory according to claim 6, wherein the polarization direction of the third ferroelectric capacitor is set. 9. A memory cell is constituted by first, second and third three ferroelectric capacitors connected in series and first and second two memory cell transistors.
Of the ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors that are connected to each other are both connected to the first bit line via the first memory cell transistor; The electrodes of the second and third ferroelectric capacitors that are connected to each other are connected to a second bit line via the second memory cell transistor, and the first and second memory cells are connected to each other. A transistor is connected to a common word line, a first plate line is connected to an electrode to which the bit line of the first ferroelectric capacitor is not connected, and a bit of the third ferroelectric capacitor is connected. An operation control method for a ferroelectric memory in which a second plate line is connected to an electrode to which a line is not connected, wherein one of the first and second plate lines is grounded. The first plate line and the second plate By applying a voltage to the word line and a voltage to turn on the first and second memory cell transistors to the word line, a voltage change according to the written data is made to occur in the first and second memory cells. 2. A method for controlling operation of a ferroelectric memory, comprising: reading data including a step of causing the two bit lines to generate data. 10. A voltage change occurring in the first and second bit lines is performed by a differential sense amplifier including a step of detecting a potential difference from another bit line precharged to a constant voltage. The operation control method for a ferroelectric memory according to claim 9, wherein: 11. A voltage value for precharging a bit line used to detect a potential difference between the first plate line and the second bit line, the first plate line and the second bit line.
Approximately 1/3 of the voltage applied between the first plate line and the second plate line is used as a voltage value for precharging the bit line used for detecting the potential difference with the other bit line. 11. The operation control method for a ferroelectric memory according to claim 10, wherein approximately two thirds of a voltage applied between the ferroelectric memory and the plate line is used. 12. A first, second and third series-connected components.
And a first and second two memory cell transistors, a memory cell is formed. Of the three ferroelectric capacitors, the first and second ferroelectric capacitors are provided. The electrodes of the body capacitors connected to each other are also the first electrodes.
And the electrodes of the second and third ferroelectric capacitors connected to each other are connected to the second bit line via the second memory cell transistor. , The first and second memory cell transistors are connected to a common word line, and the electrode of the first ferroelectric capacitor to which the bit line is not connected is connected to the first electrode. An operation control method for a ferroelectric memory, wherein a plate line is connected, and a second plate line is connected to an electrode on a side of the third ferroelectric capacitor to which a bit line is not connected, After performing data reading, setting the grounded plate line of the first or second plate line to the same potential as the non-grounded plate line;
And rewriting data including grounding the first and second plate lines and then grounding the first and second bit lines. Operation control method. 13. The first, second and third series-connected components.
And a first and second two memory cell transistors, a memory cell is formed. Of the three ferroelectric capacitors, the first and second ferroelectric capacitors are provided. The electrodes of the body capacitors connected to each other are also the first electrodes.
Of the second and third ferroelectric capacitors are connected to the second bit through the second memory cell transistor. , The first and second memory cell transistors are connected to a common word line, and the electrode of the first ferroelectric capacitor to which the bit line is not connected is connected to the first electrode. An operation control method for a ferroelectric memory, wherein a plate line is connected, and an electrode on a side of the third ferroelectric capacitor to which a bit line is not connected is connected to a second plate line, After performing the data read, the first plate line and the second plate line are connected in the opposite direction to the data read in a state where a voltage for turning off the first and second memory cell transistors is applied to the word line. plate By applying a voltage between the first ferroelectric capacitor and the third
After the step of changing the polarization direction and the magnitude of the ferroelectric capacitor, the grounded plate line of the first or second plate line is made the same as the non-grounded plate line. Applying a potential, and then grounding the first and second plate lines, and then applying the first and second plate lines.
Rewriting the data including the step of grounding the bit line. 14. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, wherein two or more bits are used by using a ferroelectric capacitor one more than the number of bits of data to be stored. A ferroelectric memory, characterized in that the ferroelectric memory is configured to store data. 15. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric substance, comprising a plurality of memory cell transistors and one more series connected than the memory cell transistors. A memory cell is constituted by the ferroelectric capacitors, and the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors which are connected to each other are both k-th. The memory cell transistor is connected to the k-th bit line via the memory cell transistor, the gate electrode of the memory cell transistor is connected to a common word line, and the bit line of the first ferroelectric capacitor is connected. The first plate line is connected to the non-electrode, and the second plate line is connected to the electrode to which the bit line of the last ferroelectric capacitor is not connected. Ferroelectric memory that. 16. A plurality of memory cell transistors,
A memory cell is constituted by one more ferroelectric capacitor connected in series than the memory cell transistor, and among the ferroelectric capacitors, the k-th (k is an integer) and k + 1-th
The mutually connected electrodes of the ferroelectric capacitor are connected to the k-th bit line via the k-th memory cell transistor, and the gate electrode of the memory cell transistor has a common word line. Are connected, the first plate line is connected to the electrode to which the bit line of the first ferroelectric capacitor is not connected, and the electrode to which the bit line of the last ferroelectric capacitor is not connected. A method of controlling operation of a ferroelectric memory in which a second plate line is connected to the electrodes of (a), (b) in which all the plate lines are connected to the word line while applying a voltage to turn on the memory cell transistor. A method of controlling the operation of a ferroelectric memory, comprising setting a polarization direction of the ferroelectric capacitor and writing data by applying a voltage between the ferroelectric memory and a bit line. 17. A semiconductor device comprising: a plurality of memory cell transistors;
A memory cell is constituted by one more ferroelectric capacitor connected in series than the memory cell transistor, and among the ferroelectric capacitors, the k-th (k is an integer) and k + 1-th
The mutually connected electrodes of the first ferroelectric capacitor are both connected to the k-th bit line via the k-th memory cell transistor, and the gate electrode of the memory cell transistor has a common word line. Are connected, the first plate line is connected to the electrode to which the bit line of the first ferroelectric capacitor is not connected, and the electrode to which the bit line of the last ferroelectric capacitor is not connected. A method of controlling the operation of a ferroelectric memory in which a second plate line is connected to an electrode of (a), after applying the data read, applying a voltage for turning off the memory cell transistor to the word line. In this state, by applying a voltage between the first plate line and the second plate line in the direction opposite to the data reading, the polarization directions and magnitudes of all the ferroelectric capacitors are changed. 17. A method for controlling the operation of a ferroelectric memory, comprising the steps of: setting a polarization direction of the ferroelectric capacitor and writing data by the method according to claim 16 after the step of causing the data to be written. 18. A plurality of memory cell transistors,
A memory cell is constituted by one more ferroelectric capacitor connected in series than the memory cell transistor, and among the ferroelectric capacitors, the k-th (k is an integer) and k + 1-th
The mutually connected electrodes of the ferroelectric capacitor are connected to the k-th bit line via the k-th memory cell transistor, and the gate electrode of the memory cell transistor has a common word line. Are connected, the first plate line is connected to the electrode to which the bit line of the first ferroelectric capacitor is not connected, and the electrode to which the bit line of the last ferroelectric capacitor is not connected. A method of controlling operation of a ferroelectric memory in which a second plate line is connected to an electrode of the first plate line, wherein one of the first and second plate lines is grounded. By applying a voltage between the first and second memory cell transistors to the word line and applying a voltage between the first and second memory cell transistors to the word line, all voltage changes corresponding to the written data can be performed. A method of controlling the operation of a ferroelectric memory, wherein data is read including a step of causing the bit line to generate data. 19. A voltage change occurring in the first and second bit lines is performed by a differential sense amplifier including a step of detecting a potential difference from another bit line precharged to a constant voltage. 19. The operation control method for a ferroelectric memory according to claim 18, wherein: 20. A voltage applied between the first plate line and the second plate line as a voltage value for precharging a bit line used for detecting a potential difference between the k-th second bit line and the k-th second bit line. 20. The operation control method for a ferroelectric memory according to claim 19, wherein approximately k / (N + 1) is used. 21. A plurality of memory cell transistors,
A memory cell is constituted by one more ferroelectric capacitor connected in series than the memory cell transistor, and among the ferroelectric capacitors, the k-th (k is an integer) and k + 1-th
The mutually connected electrodes of the ferroelectric capacitor are connected to the k-th bit line via the k-th memory cell transistor, and the gate electrode of the memory cell transistor has a common word line. Are connected, the first plate line is connected to the electrode to which the bit line of the first ferroelectric capacitor is not connected, and the electrode to which the bit line of the last ferroelectric capacitor is not connected. A method of controlling operation of a ferroelectric memory in which a second plate line is connected to an electrode of the first or second plate line after the data reading is performed. Making the plate line of the same potential as the plate line that is not grounded;
A method of controlling operation of a ferroelectric memory, further comprising the steps of: grounding the first and second plate lines; and grounding all bit lines thereafter, and rewriting data. 22. A plurality of memory cell transistors,
A memory cell is constituted by one more ferroelectric capacitor connected in series than the memory cell transistor, and among the ferroelectric capacitors, the k-th (k is an integer) and k + 1-th
The mutually connected electrodes of the ferroelectric capacitor are connected to the k-th bit line via the k-th memory cell transistor, and the gate electrode of the memory cell transistor has a common word line. Are connected, the first plate line is connected to the electrode to which the bit line of the first ferroelectric capacitor is not connected, and the electrode to which the bit line of the last ferroelectric capacitor is not connected. A method for controlling the operation of a ferroelectric memory in which a second plate line is connected to an electrode of (a), wherein after the data is read, a voltage for turning off the memory cell transistor is applied to the word line. In this state, by applying a voltage between the first plate line and the second plate line in the direction opposite to the data reading, the polarization directions and the magnitudes of all the ferroelectric capacitors are changed. After the step of setting the grounding plate line of the first or second plate line to the same potential as the non-grounded plate line, and thereafter setting the first and second plate lines to the same potential. A method of controlling the operation of a ferroelectric memory, comprising the steps of: (i) grounding the plate line and (ii) grounding all the bit lines, and then rewrite data. 23. A ferroelectric memory cell in which a memory cell including first, second, and third ferroelectric capacitors and first and second memory cell transistors is formed on a semiconductor substrate. A first M cell that operates as the first memory cell transistor formed in a desired region on the semiconductor substrate, respectively.
An IS transistor and a second MIS transistor that operates as the second memory cell transistor are first transistors.
And first and second bit wirings respectively connected to the element regions of the first and second MIS transistors are formed on the first interlayer insulating film. The first and second bit lines are covered by the first
Forming a second interlayer insulating film on the interlayer insulating film,
The first, second, and third ferroelectric capacitors were formed on the interlayer insulating film, and a wiring structure for connecting the first, second, and third ferroelectric capacitors in series was formed. A ferroelectric memory cell structure, characterized in that: 24. The ferroelectric memory cell structure according to claim 23, wherein a buried wiring is formed to connect a part of the wiring structure to an element region of the first and second MIS transistors. . 25. A third interlayer insulating film is formed on the second interlayer insulating film so as to cover the first, second, and third ferroelectric capacitors. 25. The ferroelectric memory cell structure according to claim 23, wherein the wiring structure is formed. 26. The ferroelectric capacitor according to claim 23, wherein each of the first, second, and third ferroelectric capacitors has a laminated structure in which an upper electrode and a lower electrode are formed on both surfaces of a ferroelectric film. 24. The ferroelectric memory cell structure according to claim 24, wherein 27. A first MIS is formed on a desired region of a semiconductor substrate.
Forming a first transistor and a second MIS transistor, and forming a first interlayer insulating film so as to cover the semiconductor substrate; and forming the first and second transistors on the first interlayer insulating film. The first is connected to the element region of the MIS transistor.
Forming a second bit line, forming a second bit line, and forming a second bit line on the first interlayer insulating film so as to cover the first and second bit lines. 2
Forming a first, second, and third ferroelectric capacitors on the interlayer insulating film; and forming the first, second, and third ferroelectric capacitors on the first and second ferroelectric capacitors to cover the first, second, and third ferroelectric capacitors. After forming a third interlayer insulating film on the second interlayer insulating film, a wiring structure for connecting the first, second and third ferroelectric capacitors in series is formed on the third interlayer insulating film. A method for manufacturing a ferroelectric memory cell structure, comprising: a wiring structure forming step. 28. The ferroelectric capacitor forming step includes, after sequentially forming a first conductive film, a ferroelectric film, and a second conductive film to form a laminated film, forming the laminated film into a desired shape. 28. The method according to claim 27, wherein the ferroelectric memory cell structure is patterned into a shape.