JP2000312311A - Signal processing device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To realize high-speed processing of ultra-high-definition imaging and to reduce the size of an apparatus with a simple circuit configuration. SOLUTION: The writing of a digital video signal obtained from a television camera to a memory 20 provided on the input side of a parallel signal processing unit 3 is controlled to divide the digital video signal into an arbitrary area in a two-dimensional space. The video signal is processed in parallel for each divided area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus, and more particularly to a video signal processing apparatus for digitizing an ultra-high definition video signal obtained from an ultra-high definition television camera and performing parallel signal processing.

[0002]

2. Description of the Related Art Conventionally, for example, in order to digitally process an output video signal of a television camera, a real-time processing is required, so that a high-speed signal processing circuit is required.

[0003] Furthermore, as the resolution of a television camera becomes higher, the number of signals to be processed becomes larger. Therefore, in order to perform real-time processing, it is necessary to parallelize signal processing circuits.

Conventionally, a parallel signal processing circuit divides an input digital signal in time sequence and performs parallel processing (see Japanese Patent Application Laid-Open No. Hei 7-231417).

[0005]

Since a video signal obtained from a television camera is two-dimensional information, when a video signal output as a one-dimensional signal is divided in time series,
A signal input to one processing circuit is not spatially continuous, but is complicated in that two-dimensional signal processing such as a spatial filter is performed in parallel to exchange signals between a plurality of parallelized channels. Processing is required.

On the other hand, there is also known a technique for performing parallel signal processing of the image sensor output for each image area (see Japanese Patent Application Laid-Open No. 5-153488). This technique is used for parallelizing video signals output as one-dimensional signals. It cannot be applied directly to signal processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing device which realizes high-speed processing of an ultra-high-definition image and which can be reduced in size with a simple circuit configuration.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to an apparatus for processing video signals in parallel after digital conversion, wherein the video signals after digital conversion are processed in a horizontal direction which is a pixel array direction and in the horizontal direction. Area dividing means for dividing a plurality of two-dimensional spatially divided areas by dividing in an orthogonal vertical direction;
As an overlapped image of a part of the image of the adjacent divided area adjacent to each of the divided areas, an adding unit for adding to the video signal of each divided area, and a number corresponding to the number of divisions of the divided area, and A plurality of memories each having a storage area corresponding to the signal amount of the video signal to which the extra video is added, and dividing the video signal to which the extra video stored in each of the memories is added by the division corresponding to each of the memories. By providing parallel signal processing means for performing signal processing in parallel for each region, and video synthesizing means for synthesizing the video signal to which each of the marginal images subjected to the parallel signal processing is added, for video output, Construct a signal processing device.

Here, by adding the video signal of a part of the divided area as a marginal image by the adding means, the horizontal direction, the vertical direction,
Alternatively, signal processing can be performed using video signals in a wide area in both directions.

The plurality of memories are constituted by a plurality of field memories or a combination of a FIFO memory and a field memory, and when the timing of recording the video signal in the memory is shifted for each divided area, the recording timing of each memory is changed. Is captured at a wider timing before and after the divided region, so that a video signal of a region wider than the divided region can be captured in each memory.

The video signal may be an ultra-high definition video signal obtained from an imaging device.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[Summary] The present invention is directed to an apparatus for performing parallel digital signal processing on a signal output output from an image pickup apparatus in an ultra-high resolution video signal format, for example, by dividing a video signal into two-dimensional areas. In addition, by adding a marginal image to each of the divided areas, two-dimensional signal processing is performed on the image signals in parallel.

That is, in an apparatus for processing an ultra-high-definition video signal obtained from an imaging apparatus such as an ultra-high-definition television camera in parallel with a digital signal after AD conversion, an area dividing section, a parallel signal processing section, and an area synthesizing section. A video signal is divided into two-dimensional spatial areas by controlling writing to a memory provided on the input side of each parallel signal processing system, and signal processing is performed in parallel on each of the divided areas. Do.

In this case, a video signal of a part of an adjacent divided region is added to each divided region as a marginal image, and a video signal (region) wider in a horizontal direction, a vertical direction, or both directions than the divided region is added. Signal processing is performed by using the pasted image.

Hereinafter, a specific example will be described.

[First Example] A first embodiment of the present invention will be described with reference to FIGS.

(System Configuration) First, the configuration of the present system will be schematically described. FIG. 1 shows a configuration of a signal processing device according to the present invention. Here, an ultra-high definition television camera will be described as an example.

This device is roughly divided into an A / D converter 1, an area divider 2, a parallel signal processor 3, an area synthesizer 4, and a D / A converter 5.

The A / D converter 1 converts, for example, an analog video signal output from a CCD image pickup device of a television camera into a digital signal.

The area dividing section 2 has a plurality (here, n = 6)
) Field memories 20. Using these field memories 20, a video signal digitized by the A / D converter 1 is divided into a plurality of areas. In this example, it is assumed that the video signal is divided into six divided areas (see FIG. 2 described later).

In this case, pixel data (for example, 30 to 40 pixels) of an adjacent divided area is added to each divided area as a marginal image. Therefore, the storage area of the field memory 20 has a size (the size in the horizontal direction and the vertical direction) including the extra image.

The number of pixels in each divided area can be, for example, 640 pixels in the horizontal direction and 518 pixels in the vertical direction. As a result, a general-purpose digital LSI or the like can be easily used, and low-speed serial transmission can be used for signal transmission.

The parallel signal processing unit 3 includes a plurality of signal processing circuits 30 corresponding to each field memory 20.
To each signal processing circuit 30, a video signal for each divided area output from each field memory 20 of the area dividing unit 2 is transmitted as a low-speed serial signal or the like, and is converted into a parallel signal or the like and then processed by a filter or the like. Are executed in parallel.

As specific processing, processing such as gain control, contour compensation, coring, and gamma correction are executed in parallel.

The processed signal is converted into a serial signal or the like, and transmitted to the area combining section 4 at the next stage.

The area synthesizing section 4 includes FIFOs (First-In, First-Ou) corresponding to each signal processing circuit 30.
t) A memory 40 and a changeover switch 41 (such as a multiplexer) are provided. The signal for each divided area transmitted to each FIFO memory 40 is synthesized as an ultra-high definition video signal through the changeover switch 41.

The D / A converter 5 converts the synthesized digital video signal into an analog signal and outputs it as an output signal.

(System Operation) Next, the operation of the present apparatus will be described.
A description will be given based on FIG.

The video signal input from the CCD image pickup device of the television camera is A / D converted by the A / D converter 1 and converted into a digital signal. Then, the digitized video signal is recorded in the field memory 20 prepared for each divided area divided two-dimensionally.

The video signals of each divided area recorded in the field memory 20 are processed in parallel by respective signal processing circuits 30.

Each of the video signals that have been processed in parallel is
Via the O-memory 40 and the changeover switch 41, it is synthesized again into one video signal (entire screen). The synthesized video signal is D / A converted and output as an output signal.
It is displayed on a monitor such as an ultra-high definition CRT.

(Addition of extra image in horizontal direction)
Next, a case where a margin image is added in the horizontal direction of a video signal will be described with reference to FIGS.

An example of the operation timing of the horizontal line 1 shown in FIG. 2 and the operation timing of the memory shown in FIG. 3 will be described.

FIG. 2 shows an example in which a video signal is divided into two-dimensional areas.

Here, the input video signal is divided into a total of six divided areas 100 (hereinafter referred to as divided areas 1 to 6) of two stages vertically (Y in the vertical direction) and three stages horizontally (X in the horizontal direction). And stored in each field memory 20 (hereinafter referred to as field memories 1 to 6).

The field memories 1 to 6 store the divided areas 1 to
6 and a storage capacity corresponding to a marginal image portion P (hatched area in FIG. 3) in the divided areas adjacent to the divided areas 1 to 6, and enables asynchronous read / write operation.

In this case, the extra video portion P is divided into a horizontal component and a vertical component. The extra video portion P in the horizontal component corresponds to the positions X _{1 to} X ₃ , and the extra video portion P in the vertical component is the position Y ₁ (= horizontal line e) to
This corresponds to Y ₃ (= horizontal line g).

FIG. 3 shows an example of the operation timing of the field memory 20.

The various symbols shown in FIG. 3 indicate the following contents.

A: Horizontal scanning period corresponding to the divided region 1 b: Horizontal scanning period corresponding to the divided region 2 c: Horizontal scanning period corresponding to the divided region 3 d: Recording / reading grace period of the field memory D: Adjacent Overlap period with divided area H: Horizontal scanning period of input video signal dd: Arbitrary delay time In FIGS. 2 and 3, first, in field memory 1, it corresponds to ３ of horizontal scanning period H of input video signal. Period a, and a period D in which the divided region 1 and the divided region 2 overlap.
(Margin image) (in FIG. 2, the length to the position X ₃ of the hatched area) the image data of the sequentially recorded.

After the recording, after a recording / reading grace period d, reading is performed at a low speed within the period H. The read image data is sequentially sent to the signal processing circuit 1 (the signal processing circuit 30) and is subjected to arithmetic processing.

Then, for clock speed conversion,
It is recorded in the O memory 1 (FIFO memory 40) and is read again at an arbitrary timing at the same clock speed as the first input video signal.

The same operation as above is performed in the field memories 2 to
6 is sequentially executed in the same manner.

Further, in the field memory 2, since there are two adjacent divided regions, the divided region 1 and the divided region 3, two overlapping periods D are added before and after the horizontal scanning period b.

In the field memory 3, the adjacent divided area is in the previous divided area 2, so that the overlap period D is added before the horizontal scanning period.

Hereinafter, the same operations as those of the field memories 1, 2, and 3 are performed in the field memories 4, 5, and 6.

The image data output from the FIFO memories 1 to 6 is switched at a high speed by the changeover switch 41 according to the image format to be output and is synthesized into one image, and D / A conversion processing is performed as necessary. After that, it is output.

(Addition of extra picture in vertical direction)
Next, a case where a margin image is added in the vertical direction of the video signal will be described with reference to FIGS.

The horizontal lines (e-1), e,
Examples of f, g, (g + 1) and the operation timing of the memory shown in FIG. 4 will be described.

The various symbols shown in FIG. 4 indicate the following contents.

A: Horizontal scanning period corresponding to divided regions 1 and 4 d: Recording / reading grace period of field memory D: Overlap period with adjacent divided regions H: Horizontal scanning period of input video signal dd: Arbitrary delay Time MEM1 (e-1) to MEM4 (g + 1): data for one line in the field memory MEM1 '(e-1) to MEM4' (g + 1): FIF
One line of data in the O memory. Then, as shown in FIG.
When 1) is output, the field memory 1 contains
Video data MEM1 (e-1) for the period (a + D) is recorded.

This video data is read out at a low speed, subjected to arithmetic processing, and after clock speed conversion, as described above.
It is output as video data MEM1 '(e-1).

While the horizontal line (e-1) is being output, the field memory 4 for recording the video data of the divided area 4 located vertically below the divided area 1 is not operating.

When the horizontal line e is being output, the field memories 1 and 4 simultaneously store the video data MEM1 (e) and the video data MEM4 (e) at the same timing.
And record At this time, MEM1 (e) and MEM4
(E) is the same video data.

Similarly, when the horizontal line f is being output, the same video data is stored in the field memories 1 and 1, respectively.
4 are recorded as MEM1 (f) and MEM4 (f).

When the horizontal line (g + 1) is being output, the field memory 1 does not operate, and is recorded only in the field memory 4 as video data MEM4 (g + 1).

By performing the memory control at the above operation timing, the field memory 1 stores in the field memory 1 a horizontal line g (position Y _{3 in} FIG. 2) which is one line larger than the horizontal line f as the divided area. ) Will be recorded.

On the other hand, in the field memory 4, a horizontal line e one line before the horizontal line f, which is a divided area, is stored.
The video data from (the position Y _{1 in} FIG. 2) to the horizontal line h is recorded.

The operation timing of the above-described memory control is similarly executed in the field memories 2 and 5, and further in the field memories 3 and 6, respectively.

Although the number of adjacent divided areas recorded in each memory in a redundant manner has been described as one horizontal line e or one horizontal line g with respect to the horizontal line f, the number of lines may be larger than the horizontal line f. Good.

As described above, the image data redundantly recorded in each memory becomes the video signal to which the extra video is added.

(Calculation Processing) Next, calculation processing will be described.

FIG. 5 shows that when a two-dimensional image calculation process such as a spatial filter process is performed, a calculated video signal in an area that is one-dimensionally or two-dimensionally wider than the area output as a result of the calculation has a marginal image. This is for explaining the reason why the added video signal is necessary.

As an example, when a spatial enhancement filter is realized, one example of the calculation formula is as follows.

O (x, y) = 2 * M (x, y) − {M (x, y−1) + M (x−1, y) + M (x + 1, y) + M (x, y + 1)} / 4 (1) where O (x, y): calculation result M (x, y): pixel data to be calculated (x, y): spatial coordinates x increases to the right, and y increases downward. And 2 for the spatial position (x, y) of the video signal.
When performing dimensional image processing, positions (x, y-1), (x-1, y), (x + 1, y) around the spatial position (x, y)
y), video signals such as (x, y + 1) are required. That is, the two-dimensional image processing requires an input video signal in an area wider than the area obtained as a result of the processing. For this reason, an extra image is added.

[Second Example] A second embodiment of the present invention will be described with reference to FIGS. The description of the same parts as those in the first example is omitted,
The same reference numerals are given.

In the present embodiment, as shown in FIG. 6, a FIFO memory 21 is further provided at a stage preceding the field memory 20 in the area dividing section 2. FIG. 7 shows an example of operation timing in the present system. In the drawing, the symbol d is a recording / reading grace period of the FIFO memory 21. Other symbols are the same as those in the operation timing of FIG. 3 described above.

By providing the FIFO memory 21, the operating speed of the field memory 20 can be reduced.

[0070]

As described above, according to the present invention,
For the memory provided on the input side of the parallel signal processing unit,
The writing of a digital video signal obtained from a television camera is controlled to divide it into an arbitrary area two-dimensionally,
Since video signals are processed in parallel for each divided area, signal processing can be performed at high speed even with a higher resolution television camera, and each signal processing can be performed with a lower resolution television camera. The operation speed of the circuit can be suppressed low, whereby high-speed processing of the video signal can be realized, and the size of the device can be reduced by using a general-purpose LSI.

Further, according to the present invention, since a part of the video signal of the divided area adjacent to each divided area is added as a marginal image, the marginal image is provided around the original divisional area. Even if the above two-dimensional signal processing is performed, the end of the divided area image is not affected by the signal processing, whereby an ultra-high-definition imaging system can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example in which a video signal is divided into two-dimensional regions.

FIG. 3 is an explanatory diagram showing operation timings of field memories adjacent in the horizontal direction of an image.

FIG. 4 is an explanatory diagram showing operation timings of field memories adjacent in the vertical direction of an image.

FIG. 5 is an explanatory diagram illustrating an example of two-dimensional image processing.

FIG. 6 is a block diagram showing a system configuration according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing operation timing of a field memory in the system shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 Area division part 3 Parallel signal processing part 4 Area synthesis part 5 D / A conversion part 20 Field memory 21 FIFO 30 Signal processing circuit 40 FIFO 41 Changeover switch 100 Division area

Claims (4)

[Claims] 1. An apparatus for processing a video signal in parallel after digital conversion, wherein the video signal after digital conversion is divided into a horizontal direction which is a pixel arrangement direction and a vertical direction which is orthogonal to the horizontal direction. Region dividing means for forming a plurality of two-dimensional spatial divided regions; and adding means for adding a part of an image of an adjacent divided region adjacent to each of the divided regions as a marginal image to a video signal of each of the divided regions. A plurality of memories having a number corresponding to the number of divisions of the divided area, and having a storage area corresponding to a signal amount of a video signal to which the marginal image is added; and the margins stored in each of the memories. Parallel signal processing means for performing signal processing on the video signal to which the video is added in parallel for each of the divided areas corresponding to each of the memories; And the video signal, the signal processing apparatus being characterized in that comprises the video synthesizing means for synthesizing as an image output. 2. An image of an area wider than the divided area in the horizontal direction, the vertical direction, or both directions by adding a video signal of a part of the divided area as a marginal image by the adding means. The signal processing device according to claim 1, wherein the signal processing is performed using the signal. 3. The method according to claim 1, wherein the plurality of memories are constituted by a plurality of field memories or a combination of a FIFO memory and a field memory, and when the timing of recording the video signal in the memory is shifted for each divided area, 3. The signal processing device according to claim 1, wherein the recording timing is fetched before and after the divided area at a timing wider than the divided area, so that a video signal of an area wider than the divided area is fetched into each memory. 4. The signal processing apparatus according to claim 1, wherein the video signal is an ultra-high definition video signal obtained from an imaging device.