JP2000322392A - Data processor and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor with which improvement of system, performance is realized by efficiently transferring data to other clusters by effectively using a buffer when data transfer length is short. SOLUTION: A data transferring device 6 of this data processor is provided with an instruction decoding means 7 which receives a transfer instruction to transfer data from a memory 4 in it own cluster 1 to the memories of other clusters 1' and 1" from an arithmetic processor 3, and decodes the contents of the transfer instruction, and an instruction storing means 8 which stores an instruction decoded by the instruction decoding means 7, and a data transferring means 9 which transmits the instruction read from the instruction storing means 8 to a local network 5. Thus, data can be efficiently transferred to the other clusters 1' and 1", and the performance of this system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a data processing method, and more particularly, to a system in which, when a data transfer length is short, data is efficiently transferred to another cluster by effectively utilizing a buffer. The present invention relates to a data processing device and a data processing method for improving the performance.

[0002]

2. Description of the Related Art Conventionally, in a transfer apparatus for transferring data between clusters, buffer management for transferring data to another cluster is determined so that transfer performance between clusters can be exhibited for an instruction having a long transfer length. Buffer capacity has been secured. This buffer capacity is made uniform regardless of the type of instruction.

FIG. 6 is a diagram showing a conventional management buffer storage image. As shown in FIG. 6, even if the decomposed instructions 1 to 4 are obtained by decomposing instructions having a short data transfer length and a small number of elements, an element buffer having a larger capacity than each of the decomposed instructions 1 to 4 is provided for each of the decomposed instructions. Since data is allocated and stored, there is a gap in the management buffer.

[0004] In the above, the data transfer length is the length of one entire instruction, and the number of elements is each element constituting this instruction. Instruction disassembly means disassembly of the instruction into elements constituting the instruction irrespective of the transfer length of the instruction.

[0005]

However, as described above, when there is data of an instruction having a short data transfer length, one buffer length to be transmitted corresponds to one decomposed instruction in which the buffer length is decomposed. There is a problem in that the buffer is not sufficiently used, so that the buffer is exhausted and a considerable data transfer loss occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and when the data transfer length is short, a buffer is effectively used to efficiently transfer data to another cluster. An object of the present invention is to provide a data processing device and a data processing method for improving performance.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a memory, an arithmetic processing unit, and a data transfer device for executing data transfer between them are connected to a local network. A plurality of connected clusters are provided in parallel, and the data transfer device is a data processing device that also performs data transfer between the clusters via an inter-cluster network connecting the clusters. When a transfer instruction to transfer data to a memory of another cluster is received from the arithmetic processing unit, instruction decoding means for decoding the contents of the transfer instruction, instruction storage means for storing the instruction decoded by the instruction decoding means, Data transfer means for sending the command read from the command storage means to the local network, wherein the command storage means For instructions that have been decoded by reader in stages,
The instruction decomposing means for decomposing each element constituting an instruction, and the number of elements indicating the data amount of each element of each instruction decomposed by the instruction decomposing means, the buffer provided for each cluster and used during data transfer is used. Transfer length determining means for determining how many data of instructions can be stored in one management area, wherein the data of the instructions determined to be storable by the transfer length determining means are stored in the same buffer. It is characterized in that data is transferred to another cluster by storing it in the management area.

The transfer length discriminating means includes first and second disassembled instruction holding means for holding the instruction decomposed into each element by the instruction decomposing means together with the number of elements, and an instruction for each predetermined transfer unit. Transfer unit buffer capacity holding means for holding the buffer capacity of the first unit, element number check for comparing the number of elements held in the first disassembly instruction holding means with the buffer capacity held in the transfer unit buffer capacity holding means Based on the comparison result between the means and the element number checking means, a buffer generation start flag for setting the validity or invalidity of the storage of the buffer in the same management area and setting information of the buffer generation start flag are received, and based on this information, A buffer number generation circuit for deciding whether to acquire a new buffer number. And further comprising a buffer numbers.

The plurality of disassembly instruction holding units constitute an instruction type in which the type of instruction is stored, instruction accompanying information in which additional information related to the instruction is stored, and an instruction disassembled by the instruction disassembly unit. The number of elements indicating the data amount of each element,
And a distance indicating a distance between elements of each instruction.

The element number checking means compares the number of elements stored in the plurality of instruction holding means with the buffer amount stored in the transfer unit buffer capacity holding means.
A determination is made whether subsequent decomposed instructions can still be stored in the same buffer, and if a subsequent decomposed instruction can be stored in the same buffer, the buffer generation start flag is invalidated, Sends invalidation information indicating that the buffer generation start flag is invalid to the buffer number generation circuit, and if the subsequent disassembled instruction cannot be stored in the same buffer, the buffer generation start flag is enabled, It is characterized in that validity information indicating that the buffer generation start flag is valid is sent to the buffer number generation circuit.

The buffer number generation circuit refers to the buffer generation start flag and, when the buffer generation start flag is invalid, does not acquire a new buffer number and refers to the buffer generation start flag to start buffer generation. When the flag is valid, a new buffer number is obtained.

Further, in a data processing method for performing data processing for executing data transfer between clusters via an inter-cluster network connecting the clusters,
Upon receiving a transfer instruction for transferring data from the memory in the own cluster to the memory in the other cluster, the first step of decoding the contents of the transfer instruction and the instruction decoded in the first step are executed. The number of instruction data is divided into one management area of a buffer used at the time of data transfer provided for each cluster, according to the number of elements indicating the data amount of each element of each divided instruction. A second step of determining whether the is storable;
And storing the instruction data determined to be capable of storing the instruction data in the second step in the same management area of the buffer and transferring the data to another cluster. And

With the above configuration, when the data transfer length is short, the performance of the data processing device is prevented from deteriorating due to the depletion of the buffer, and the buffer is effectively used. Transfers can be made to improve system performance.

Further, since the size of the management buffer can be dynamically and flexibly changed according to the data length,
The management buffer can be used efficiently.

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

First, a first embodiment of the present invention will be described.

In a cluster-connected parallel computer having a network device for connecting clusters, data is loaded from a memory in its own cluster, data is transferred to another cluster, and stored in a memory in another cluster.
In the data transfer method when data is loaded from the memory in another cluster, transferred to the own cluster, and stored in the memory in the own cluster, the data is loaded from the memory and the loaded data is transferred to the other cluster And a buffer for receiving transfer data from another cluster and writing the data to the memory.

At this time, buffer management is performed to efficiently transfer an instruction having a long data transfer length to another cluster,
Data is transferred in buffer management units. When the data transfer length is long, the buffer can effectively store data and transfer data to other clusters. However, when the data transfer length is short, there is a gap in the buffer and the buffer cannot be stored effectively.

Therefore, this embodiment is an example in which data can be efficiently transferred to another cluster even when the data length is short.

FIG. 1 is a block diagram showing the overall configuration of the information processing system according to the first embodiment of the present invention. The system shown in FIG. 1 includes a plurality of clusters 1, 1 ′, 1 ″ and an inter-cluster network 2 connecting the clusters 1, 1 ′, 1 ″.

Since the configurations of the clusters 1, 1 ′ and 1 ″ are the same, the cluster 1 will be described here as an example.
The cluster 1 includes a shared memory 4 shared by a plurality of processing units 3, a local network 5 having an interface with the plurality of processing units 3 and the shared memory 4, and a local network 5 and an inter-cluster network 2. Then, the shared memory 4 of the own cluster 1 and the other cluster 1 ′,
1 '' which controls data transfer between the shared memories.

The data transfer device 6 receives a transfer command from the arithmetic processing device 3 via the local network 5 to transfer the data from the shared memory 4 of the source cluster to the shared memory of the destination cluster, and decodes it. Decoding means 7; instruction storage means 8 for storing the instructions decoded by the instruction decoding means 7; reading and writing to the shared memory 4 in the cluster; And data transfer means 9 for transmitting / receiving data to / from ', 1''.

FIG. 2 is a block diagram showing the internal configuration of the instruction storage means 8 according to the first embodiment of the present invention.

As shown in FIG. 2, the instruction storage means 8 includes an instruction storage buffer 21 for storing the instructions decoded by the instruction decoding means 7 and an instruction read register 22 for sequentially reading the instructions stored in the instruction storage buffer 21. Instruction decomposing means 23 which receives the instruction held in the instruction read register 22 and decomposes the instruction for each element constituting the instruction.
And each element of the instruction decomposed by the instruction decomposing means 23, and the decomposed instruction is stored in one management area of a buffer (not shown) provided in each of the clusters 1 ′ and 1 ″. The transfer length determining means 23 which determines whether the instruction can be stored by the number of elements indicating the data amount of each element of each instruction, and the instruction decomposed by the transfer length determining means 24 is transferred to the other clusters 1 'and 1''. And a buffer number generation circuit 25 that generates a buffer number when the operation is performed.

In FIG. 2, the instruction storage buffer 21
The command decoded by the command decoding means 7 is received. Next, the instruction stored in the instruction storage buffer 21 is read by the instruction read register 21, and the instruction
Break down instructions. The transfer length determining unit 24 receives the instruction decomposed by the instruction decomposing unit 23, checks the number of elements of the decomposed instruction, and determines whether the data of the instruction can be stored in the instruction storage buffer 21. Circuit. The buffer number generation circuit 25 is a circuit for generating a buffer number when transferring the decomposed instruction to the clusters 1 ′ and 1 ″.

FIG. 3 is a block diagram showing the internal configuration of the transfer length determining means 24 shown in FIG.

As shown in FIG. 3, the transfer length determining means 24
Includes three disassembly instruction holding units 31, 35, and 36 for holding the instructions disassembled by the instruction disassembly unit 23, a buffer capacity holding unit 33 for holding the buffer capacity of each instruction for each transfer unit, Element number checking means 32 for comparing the number of elements held in the means 31 with the buffer capacity held in the transfer unit buffer capacity holding means 33
And a buffer generation start flag 34 for which validity and invalidity are set according to the comparison result of the element number check means 32,
A buffer number generation circuit 25 that receives setting information of the buffer generation start flag 34 and determines whether to acquire a new buffer number based on the information.

In FIG. 3, disassembly instruction holding means 31, 3
5 is an instruction type 31A, 35A in which the instruction type is stored.
Instruction accompanying information 31B and 35B storing additional information related to the instruction, element numbers 31C and 35C storing the number of elements of the instruction decomposed by the instruction decomposing means 23, and a distance indicating the distance between the elements. 31D and 35D. The disassembly instruction holding unit 36 stores an instruction type 36A in which the type of instruction is stored, instruction accompanying information 36B in which additional information related to the instruction is stored, and the number of elements of the instruction disassembled by the instruction disassembly unit 23. 36C of stored elements,
The buffer 36 includes a distance 36D indicating the distance between elements and a buffer number 36E in which the buffer number generated by the buffer number generation circuit 25 is stored.

FIG. 4 is a diagram showing a storage image of the management buffer in the instruction storage buffer 21.

As shown in FIG. 4, each of the plurality of management buffers 1 to 3 according to this embodiment is provided with two
It can be seen that they are stored one by one and used efficiently.

As described above, according to the present invention, by providing the transfer length determining means 24 for determining the transfer length of an instruction and the instruction decomposing means 23 for decomposing an instruction, the instruction decomposing means 23 is provided.
When the transfer length of the instruction decomposed by the above is short, the transfer length is determined by the transfer length determining means 24, and the maximum number of decomposed requests that can be stored in the management buffer is determined.
The data of the number is packed in the management buffer and transferred to the other clusters 1 ′ and 1 ″.

Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.

The inter-cluster transfer command issued from the processing unit 3 shown in FIG. 1 is received by the data transfer unit 6 via the local network 5 and is decoded by the command decoding unit 7. The decoded instruction is sent to the instruction storage means 8.

The decryption command input to the command storage means 8 is:
First, it is buffered in the instruction storage buffer 21.
The instruction stored in the instruction storage buffer 21 is read out to the instruction reading register 22. The read instruction is held in the instruction reading register 22 while the instruction decomposing means 23 is performing the decomposition processing of the preceding instruction. When the disassembling process of the preceding instruction is completed by the instruction disassembling unit 23, the instruction held in the instruction read register 22 is disassembled by the instruction disassembling unit 23. In the decomposition processing means 23,
Instruction decomposition is performed in units of the maximum number of elements of the management buffer capacity.
The instruction decomposed here is sent to the transfer length determining means 24.

The instruction sent from the instruction disassembly means 23 is held by the disassembly instruction holding means 1. The held contents are an instruction type 31A, instruction accompanying information 31B, the number of elements 31C decomposed by the instruction decomposing means 23, and a distance 31D indicating the distance between elements.

The transfer unit buffer capacity held in the transfer unit buffer capacity holding means 33 in advance is compared with the number of elements held in the disassembly instruction holding means 1 by the element number checking means 32. For example, the number of elements held in the disassembly instruction holding means 1 is 256 elements, and the buffer capacity held in the transfer unit buffer capacity holding means 33 is 51
In the case of 2, this buffer can store the data of two instructions that have been decomposed in the same buffer. Since a buffer generation start flag 34 is provided for buffer number generation, when this flag 34 becomes valid, the buffer number generation circuit 25 acquires a new buffer number.

Here, the number of elements indicates how many elements the instruction consists of. The buffer capacity held in the transfer unit buffer capacity holding means 33 means how many elements the buffer stores. It indicates whether it can be done.
That is, when the number of elements is 1 and the capacity is 1, only one element can be stored. Further, if the buffer capacity does not change and the number of elements increases to 2, the increased number of elements cannot be stored. Thus, the number of elements 1 may be considered to correspond to the buffer capacity 1.

The element number checking means 32 compares the number of elements held by the transfer unit buffer capacity holding means 33 with the number of elements held by the disassembly instruction holding means 1, and the subsequent decomposed instructions are still stored in the same buffer. It is determined whether the data can be stored and transferred. If the subsequent decomposed instruction can still be stored in the same buffer, the buffer generation start flag 34 is invalidated and invalid information is sent to the buffer number generation circuit 25. The buffer number generation circuit 25 receives the invalidation information, and sends out the buffer number acquired at the time of the preceding disassembled instruction to the transfer length determination means 24 without acquiring a new buffer number. If the subsequent disassembled instruction cannot be stored in the same buffer, the buffer generation start flag 34 is made valid and transmitted to the buffer number generation circuit 25. At this time, the buffer number generation circuit 25 acquires a new buffer number and sends it to the transfer length determining means 24.

The disassembly instruction input from the instruction disassembly means 23 is first stored in the disassembly instruction holding means 31, then in the disassembly instruction holding means 35, and finally in the disassembly instruction holding means 36. That is, as described above, when the disassembly command is stored in the disassembly command holding unit 31, the buffer capacity of the transfer unit previously held in the transfer unit buffer capacity holding unit 33 and the buffer capacity of the disassembly command holding unit 1 The number of elements is compared by the element number check means 32. Then, when stored in the disassembly instruction holding means 3 from the disassembly instruction holding means 2, the buffer number 36E generated by the buffer number generation circuit 25 is added.

As described above, the disassembly instruction holding means 35 is a portable holding means for writing the buffer number 36E for the instruction held by the disassembly instruction holding means 31. The time until the data is transferred to the holding unit 36 is determined by the number-of-elements checking unit 32.
This is provided in order to match the comparison time performed in.

The disassembly instruction holding means 36 receives the instruction held in the disassembly instruction holding means 35, and simultaneously holds the buffer number generated by the buffer number generation circuit 25. The instruction held by the disassembly instruction holding means 36 is
The data is sent to the data transfer means 9.

As described above, according to the present embodiment, when the data transfer length is short, the performance is prevented from deteriorating due to buffer exhaustion, and the data is efficiently transferred to another cluster by using the buffer effectively. System performance can be improved.

Next, a second embodiment of the present invention will be described.

FIG. 5A is a diagram showing a storage image of the management buffer according to the second embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing a management method of a start address and an end address of each management buffer.

This embodiment is an example in which the size of the management buffer is not a predetermined fixed length but can be dynamically changed according to the instruction data length.

In order to dynamically change the buffer size according to the data length as in this embodiment, means for managing the start address and the end address of the buffer storing the data is required. May be realized as long as a predetermined effect can be obtained.

Since the means for managing the buffer start address and the end address are well known, detailed description of the operation of this embodiment will be omitted.

As described above, according to the present embodiment, the size of the management buffer can be dynamically and flexibly changed according to the data length, so that the management buffer can be used efficiently.

[0049]

As described above, according to the present invention,
The following remarkable effects are obtained.

(1) When the data transfer length is short, the performance of the data processing device is prevented from deteriorating due to the depletion of the buffer, and the data is efficiently transferred to another cluster to improve the system performance in order to use the buffer effectively. Can be done.

(2) Since the size of the management buffer can be changed dynamically and flexibly according to the data length,
The management buffer can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an information processing system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of an instruction storage unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating an internal configuration of a transfer length determining unit illustrated in FIG. 2;

FIG. 4 is a diagram illustrating a storage image of a management buffer.

FIG. 5A is a diagram illustrating a storage image of a management buffer according to a second embodiment of the present invention, and FIG. 5B is a diagram illustrating a management method of a start address and an end address of each management buffer. is there.

FIG. 6 is a diagram showing a conventional buffer storage image.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 cluster 2 inter-cluster network 3 arithmetic processing unit 4 shared memory 5 local network 6 data transfer unit 7 instruction storage unit 8 instruction decoding unit 9 data transfer unit 21 instruction storage buffer 22 instruction read register 23 instruction decomposition unit 24 transfer length determination unit 25 Buffer number generating circuit 31, 35, 36 Decomposition instruction holding means 31A, 35A, 36A Instruction type 31B, 35B, 36B Instruction accompanying information 31C, 35C, 36C Number of elements 31D, 35D, 36D Distance 32 Element number checking means 33 Transfer unit buffer Capacity holding means 34 Buffer generation start flag 36E Buffer number

Continued on the front page F-term (reference) 5B013 DD01 DD05 5B033 AA10 AA14 BA01 DC04 5B045 AA00 BB17 BB36 BB47 DD02 5B060 AA12 AA20 AC11 AC18 CA17 CD02 CD07 KA01 KA08 5B089 GA01 GA04 HA06 KA05 KA14 KB06 KD10

Claims (6)

[Claims] 1. A plurality of clusters in which a memory, an arithmetic processing unit, and a data transfer device for executing data transfer between them are connected by a local network are provided in parallel, and the data transfer device connects each cluster. A data processing device that also performs data transfer between clusters via a connecting inter-cluster network, wherein the data transfer device executes a transfer command to transfer data from a memory in its own cluster to a memory of another cluster. When received from the processing device, an instruction decoding unit that decodes the contents of the transfer instruction, an instruction storage unit that stores the instruction decoded by the instruction decoding unit, and an instruction read out from the instruction storage unit is sent to the local network. And a data transfer unit, wherein the instruction storage unit stores the instruction decrypted by the instruction decryption unit. An instruction decomposing unit that decomposes each element constituting an instruction, and the number of elements indicating the data amount of each element of each instruction decomposed by the instruction decomposing unit are used at the time of data transfer provided for each cluster. Transfer length determining means for determining how many data of instructions can be stored in one management area of the buffer, and storing the data of the instruction determined to be storable by the transfer length determining means. A data processing apparatus for storing data in the same management area of a buffer and transferring data to another cluster. 2. The data processing apparatus according to claim 1, wherein the transfer length determining unit holds the instruction decomposed into each element by the instruction decomposing unit together with the number of elements. Holding means; transfer unit buffer capacity holding means for holding a predetermined buffer capacity of an instruction for each transfer unit; number of elements held in the first disassembly instruction holding means; A number-of-elements check means for comparing the buffer capacity held in the means, and a buffer generation start flag in which validity or invalidity of storage in the same management area of the buffer is set according to a comparison result of the number-of-elements check means, A buffer number generation circuit that receives setting information of the buffer generation start flag and determines whether to acquire a new buffer number based on the information; A data processing apparatus, wherein the second disassembly instruction holding means further includes a buffer number generated by the buffer number generation circuit. 3. The data processing device according to claim 2, wherein the plurality of disassembly instruction holding units include: an instruction type in which the type of the instruction is stored; and instruction accompanying information in which additional information related to the instruction is stored. A data processing apparatus, comprising: a number of elements indicating a data amount of each element constituting an instruction decomposed by the instruction decomposing means; and a distance indicating a distance between elements of each instruction. 4. The data processing device according to claim 2, wherein the element number check unit is stored in the transfer unit buffer capacity holding unit and the number of elements stored in the plurality of instruction holding units. Comparing the buffer amount with the buffer amount, determining whether or not the subsequent decomposed instruction can still be stored in the same buffer, and if the subsequent decomposed instruction can be stored in the same buffer, When the generation start flag is invalidated, invalid information indicating that the buffer generation start flag is invalid is sent to the buffer number generation circuit, and the subsequent disassembled instruction cannot be stored in the same buffer. Validating the buffer generation start flag and sending valid information indicating that the buffer generation start flag is valid to the buffer number generation circuit. Data processing apparatus, characterized in that. 5. The data processing device according to claim 2, wherein the buffer number generation circuit refers to the buffer generation start flag and, when the buffer generation start flag is invalid, sets a new buffer number. A data processing device, wherein a new buffer number is acquired without referring to the buffer generation start flag and when the buffer generation start flag is valid. 6. A data processing method for performing data processing that also performs data transfer between clusters via an intercluster network connecting the clusters, wherein data is transferred from a memory in the own cluster to a memory in another cluster. Receiving the transfer instruction to the effect that the first instruction decodes the contents of the transfer instruction; and decomposes the instruction decoded in the first step for each element constituting the instruction. A second step of determining how many instruction data can be stored in one management area of a buffer used at the time of data transfer provided for each cluster based on the number of elements indicating the data amount of each element And storing the instruction data determined to be capable of storing the instruction data in the second step in the same management area of the buffer, and A third step of transferring data to the data processing apparatus.