JP2000324019A - Cdma transmission system and radio device using same transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude intense variation of a spread code sequence waveform at a chip section end, to prevent the frequency bandwidth from increasing, and to improve the communication quality by excluding intense variation in spread code value which is continuous in a transition section when the spread code value is different between adjacent chip sections. SOLUTION: A CDMA transmitter is constituted by inserting spread code sequence waveform continuing circuits(CODE-CS) 150 to 15n between spread code generating circuits(CG) 130 to 13n and spreading circuits(SS) 120 to 12n. Those CODE-CSs 150 to 15n are provided and then only when the spread code value is different between adjacent chip sections, the spread code value can gently be varied in the transition section. In the CODE-CSs 150 to 15n, spread code sequences from the corresponding CGs 130 to 13n are inputted to adders and outputs at output terminals are inputted to and held in latch registers with leading edges of clock signals applied to clock terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDMA (Code
Division Multiple Access) transmission system and a wireless device using the transmission system.

[0002]

2. Description of the Related Art In recent years, in the field of mobile communication such as automobile telephones and mobile telephones, those using a CDMA transmission system have been put to practical use. FIG. 10 shows a schematic configuration of a general CDMA transmitter. In the figure, a known value used for a pilot signal from an input terminal 100 and information values from n information input terminals 101 to 10n are input to corresponding phase modulation circuits (MOD) 110 and 111 to 11n, respectively. The number n of input information means the number of communications for simultaneous multiple access.

Each phase modulation circuit modulates the phase of a carrier signal in accordance with input information,
Generate n + 1 primary modulated waves corresponding to signals from 0 to 10n. Spreading circuits (SS) 120 to 12n respectively correspond to a corresponding primary modulated wave and a spreading code generation circuit (C
G) The product with the spreading code sequence applied from 130 to 13n is obtained in synchronization with the time period (chip period) of the spreading code sequence, and the obtained product is output as a spreading code. In addition,
The spreading code sequences generated by the spreading code generation circuits (CG) 130 to 13n are orthogonal to each other. Further, the spread code generation circuits (CG) 130 to 13n generate a spread code sequence corresponding to each row of the Walsh function having a code length N of n + 1 or more by one.
In the symbol period, the repetition occurs for the number of segments.

[0004] The n + 1 spread signals and various control signals are then summed in a summing circuit (SUM) 140. The output of the summing circuit (SUM) 140 is band-limited by a band-limiting circuit (BPF) 141, and the transmission circuit (TX) 142 performs frequency conversion and power amplification as necessary and transmits the result. Here, the operation of the phase modulation circuits (MOD) 110 to 11n in FIG. 10 will be described in detail below. Each of the phase modulation circuits (MODs) 110 to 11n divides a carrier signal at a fixed time T like the primary modulation wave and the symbol structure shown in FIG. 11, and sets the phase of each period to the QPSK bit shown in FIG. Placement or Figure 1
In accordance with the bit arrangement of the offset QPSK shown in FIG. 3, the phase of the carrier signal is modulated so as to correspond one-to-one to the symbol values 00, 01, 10, and 11 transmitted in one period to generate a primary modulated wave.

[0005] Here, the primary modulation wave is a general term for signals that are phase-modulated such as QPSK and offset QPSK. Further, when QPSK is used as the primary modulation wave as described above, the phase of the QPSK wave is 0, 90, 180,
It takes four values of 270 degrees (or 0, ± 90, 180 degrees), and when offset QPSK is used, the phase information of the QPSK wave is 45, 135, 225,
It is assumed that four values of 315 degrees (or ± 45 and ± 135 degrees) are taken. The phase difference is a residual value of 360 degrees, and the phases of the QPSK and offset QPSK waves are set so as to divide the entire phase space to the maximum. For example, the reference phase is 4 degrees for QPSK and 4 degrees for offset QPSK.
Assuming 5 degrees, all phases are 90 degrees apart from each other. The four phases of the primary modulated wave are set to states 00, 01, 1
By associating them with 0 and 11, the transmission bit sequence can be made to correspond to dibits in which two bits are combined, and two bits can be transmitted with one symbol.

On the other hand, the symbol period T is an amount defined by the reciprocal of the symbol rate.
In the case of symbols / second (hereinafter, symbol / second is referred to as sps), T = 31.25 μs. Therefore,
When the symbol rate is 32 ksps, the transmission rate of QPSK is 64 kbit / sec (hereinafter, bit / sec is bps).
Described).

Next, the spreading circuits (SS) 120 to
The operation of 120n will be described. As described above, in order to express each of the four types of phases of QPSK or offset QPSK, the waveforms of the carriers in the symbol period T are mutually different.
Four types of waveforms, each different by 0 degrees, are required.
At least four or more samples per symbol period are required to describe the kind of waveform. Here, the number of samples per symbol period is assumed to be four.

Now, as shown in FIG. 14, each symbol period of the primary modulated wave is divided into segments 0 of the same time section.
Is divided into four segment sections from to. Here, the segment means a period from the first code to the last code in a single spreading code sequence in each symbol period. Furthermore, each segment section is
As shown in FIG. 15, the signal is divided into chip sections of a number equal to the number of codes of the spread code string. The chip value is given by the product of the primary modulation wave and the spread code value in each chip section. Since the primary modulation wave is a time function, the time resolution of the chip value is the chip period τ. But CD
In MA transmission, a spreading operation and a spreading operation on the receiving side, which will be described later, are performed, so that the time resolution of information to be transmitted is the segment period τN. Here, N is the code length.

The waveform of the spread signal shown in FIG. 15 shows a case where the first code string of the Walsh function having a code length of 32 is used as the spread code string. It is not always necessary to use a Walsh function as the spreading code string, but it is necessary that the spreading code strings are orthogonal to each other. Here, when the inner product of the code sequence becomes zero, the code sequence is said to be orthogonal. Hereinafter, a Walsh code string having a code length of 32 will be described.

First, the orthogonality of the 0th to 2nd Walsh code strings will be described. The 0th to the 2nd Walsh code strings are respectively given as follows. 0th code sequence: (-1, -1, -1, -1, ...,-1,
-1, -1, -1) First code string: (-1, 1, -1, 1, ..., -1, -1)
1, −1, 1) second code string: (−1, −1, 1, 1,..., −1,
-1, 1, 1) Inner product (0, 1) of 0th and 1st Walsh code strings, 1st
And the inner product (1, 2) of the second Walsh code string and the inner product (0, 2) of the 0th and the second Walsh code string can be calculated as follows. That is, the inner product (0, 1) = 1-1 + 1−1 +.
= 0 Inner product (1, 2) = 1-1-1 + 1 + ... + 1-1-1 + 1
= 0 Inner product (0,2) = 1 + 1-1-1 + ... + 1 + 1-1-1
= 0. Since these inner products are all 0, Wals
It becomes clear that the code strings of the h function are orthogonal to each other.

On the other hand, the inner product of the Walsh code string itself can be calculated as follows. That is, the inner product (0, 0) = 1 + 1 + 1 + 1 +... + 1 + 1 + 1 + 1
= 32 Dot product (1,1) = 1 + 1 + 1 + 1 + ... + 1 + 1 + 1 + 1
= 32 Dot product (2,2) = 1 + 1 + 1 + 1 + ... + 1 + 1 + 1 + 1
= 32, and the inner product of all the code strings themselves normalized by the code length 32 is always unit 1. This is because Wa is a code string.
When the lsh code string is used, it means that the same Walsh code string can be used as the spreading code string and the despreading code string.

Now, it is assumed that three pieces of information are multiplexed and transmitted using the 0th to 2nd Walsh code strings shown in a certain segment period. If the value a is transmitted using the 0th Walsh code sequence, the value b is transmitted using the first Walsh code sequence, and the value c is transmitted using the third Walsh code sequence, the summation circuit ( The information (sum signal (0, 1, 2)) input to the SUM 140 is described as follows for each chip. Sum signal (0,1,2) = a (-1, -1, -1, -1, ...,-1, -1, -1, -1, -1) + b (-1,1, -1,1,1, ..., -1, 1, -1, 1) + c (-1, -1, 1, 1, ..., -1, -1, 1, 1) If it is assumed that the sum signal can be correctly received on the receiving side ,
The received sum signal is multiplied by the spreading code sequence, and the value of the primary modulation signal of the corresponding segment is obtained as shown below.

That is, the value corresponding to the 0th Walsh code string is the sum signal (0, 1, 2) and the 0th Walsh code string.
The inner product of the code sequence is given as follows. Sum signal (0, 1, 2) 0th Walsh code string =-(-abc)-(-a + bc)-(-ab-c) ...-(-ab-c) -(-A + bc)-(-ab + c)-(-a + b + c) = 32a. Therefore, the sum signal (0, 1, 2) 0th Wa
If the inner product with the lsh code sequence is normalized by the code length 32, it becomes clear that the value a is correctly received, and the values b and c are completely suppressed and can be received correctly without interference.

Similarly, the value corresponding to the first Walsh code string is given by the inner product of the sum signal (0, 1, 2) and the first Walsh code string, the value of which is 32b, and the value of the second Walsh code string is 32b. The value corresponding to the code string is the sum signal (0, 1,.
2) and the inner product of the second Walsh code string, and the value is 32c. Therefore, if the inner product of the sum signal (0, 1, 2) and the first Walsh code sequence is normalized by the code length 32, the value b is correctly received, and the sum signal (0, 1, 2)
Is normalized by the code length 32, the value c is correctly received.

As described above, as long as the spreading code strings are orthogonal to each other, multiple access can be performed by the number of spreading code strings, and communication can be performed only when the spreading code strings match. Note that 1 in segment 0 of symbol section 1 in FIG.
The primary modulation wave has a positive value of 0 to 1, and the primary modulation wave in segment 1 has a negative value of 0 to -1.
The sign of the chip value of segment 0 in the corresponding symbol section 1 in the figure changes to a negative and positive alternation, and the sign of the chip value of segment 1 changes to a positive and negative alternation.

The chip rate of the spread signal is 32.
In the case of, 32 ksps / 4 segments32 chips / segment = 4.096 M chips / sec.
Chip / sec is described as cps). All spread signals are
Since the signal changes synchronously in each chip section, a sum signal that takes the sum of the chip values as the signal value in the chip section is:
The waveform shows a constant value in the chip section. Therefore, 3
Regardless of the transmission information rate, the chip rate is always 4.096 Mcps, regardless of the transmission information rate, regardless of whether the transmission is performed at the maximum information rate of 2 Mbps for simultaneous communication of two channels or at the minimum information rate of 64 kbps for one channel. .

In this way, as shown in FIG. 10, a plurality of spread signals corresponding to the information signal and the required control signal are spread orthogonally to each other by the spread code generation circuits (CG) 130 to 130n. Spreading circuits (SS) 120 to 12n are used to generate a sum of a plurality of spreading codes by a summing circuit (SUM) 140 using a code sequence, and the sum signal thus obtained is transmitted by a transmitting circuit (TX) as necessary. , And performs frequency conversion and power amplification, and transmits it as a CDMA signal.

In order to accurately transmit a rectangular wave of a CDMA signal, a frequency band several times the chip rate is required. As shown in FIG. 10, a band limiting circuit (BPF)
As a function of 141, a band-pass filter operation is performed, and the frequency bandwidth is limited to about the chip rate. Here, the radio wave transmitted from the transmission circuit (TX) as described above is generally rarely transmitted via an ideal radio wave propagation path. In mobile communication such as a mobile phone or a mobile phone, the transmitter itself moves, so that a Doppler shift occurs and the carrier frequency shifts. Alternatively, when the signal is received through a plurality of radio wave propagation paths, a fading phenomenon occurs in which the phase and amplitude of the received wave change with time.

Therefore, on the receiving side, the CDMA receiver is composed of main circuits for reception, synchronous detection, reception control, demodulation, despreading, phase correction, judgment and the like. In FIG.
A reception control circuit (CNT) 204 detects various control signals required for controlling the receiver from the received signal, and outputs a plurality of despread code strings required for reception. A synchronization detection circuit (SYNC) 203 outputs a carrier reproduction wave, a chip synchronization signal, a segment synchronization signal, a symbol synchronization signal, and the like from the received signal.

The demodulation circuit (deMOD) 201 is shown in FIG.
Has the configuration shown in FIG. In the figure, the receiving circuit (R
X) A received wave applied to an input terminal 2010 connected to 200 is input to multipliers 2011 and 2012. Here, the demodulation circuit (deMOD) 201 generally uses a synchronous detection method, finds the product of the carrier reproduced wave 202 and the received wave by the multiplier 2011, and subsequently calculates the product of the carrier cycle accumulated by the accumulator 2014 for each carrier cycle. The inner product for each is obtained, and the obtained inner product is stored in a latch register (REG) 20.
16 and held for the carrier cycle period, and outputs the value held by the latch register (REG) 2016 as the in-phase component i (t) of the demodulated signal of the primary modulation wave for each carrier cycle. At the same time, the demodulation circuit (deMOD) 201
The multiplier 2012 calculates the product of the orthogonal carrier signal obtained by shifting the carrier reproduced wave 202 by 90 degrees by the phase shifter 2013 and the received wave, and then accumulator 2015 for each carrier cycle.
To obtain the inner product for each carrier cycle, fetch the obtained inner product in the latch register (REG) 2017, hold it for the carrier cycle period, and store it in the latch register (REG) 20.
The value held at 17 is the quadrature component q of the demodulated signal of the primary modulation wave.
(T) is output every carrier cycle. The signals R input to the accumulators 2014 and 2015 are cumulative reset signals input from the control terminal 2018 every carrier cycle. At the leading edge of the cumulative reset signal R, the accumulators 2016 and 2017 hold the input values.

The in-phase component i (t) and the quadrature component q (t) of the demodulated signal from the demodulation circuit (deMOD) 201 are shown in FIG.
, N + 1 despreading circuits (deSS) 21
Input to 0-21n. FIG. 18 shows this diffusion circuit (d
One configuration example of eSS) 210 to 21n is shown. In-phase components i (t) of the demodulated signal are input to input terminals 2100 and 2101,
The quadrature component q (t) of the demodulated signal is input. According to the chip synchronization signal, multipliers 2102 and 2103 respectively calculate in-phase component i (t) of the demodulated signal, quadrature component q (t) of the demodulated signal, and the i-th despread code sequence input from terminal 22i. The product is obtained, and the accumulation of the product is obtained for each segment according to the segment synchronization signal.

Here, i indicates the i-th channel. The i-th despread code sequence is a de-spread code sequence corresponding to the i-th spread code sequence used on the transmitting side. When the Walsh function is used, the despread code sequence and the spread code sequence are equal to each other. As shown in FIG. 16, the corresponding despreading code sequence is input to terminals 220 to 22n of despreading circuits 201 to 20n.

Subsequently, referring to FIG.
The outputs of 2, 2103 are accumulators 2014, 20
Accumulated at 15. Accumulator 2104, 2105
, The cumulative reset signal R is input from the terminal 2110 for each segment. Accumulator 2104, 2105
Are normalized by the code length, respectively, and the in-phase component I _i ′ (t) of the despread signal and the quadrature component Q _i ′ (t) of the despread signal held in the segment section by the latch registers (REG) 2106 and 2107. ) As output terminal 210
8 and 2109.

Since the spreading code sequences are orthogonal to each other, when the despreading code sequence matches the transmission spreading code sequence, the outputs of the despreading circuits 210 to 21n output finite values, Can be received correctly. If the despreading code sequence does not match the transmission spreading code sequence, the despreading circuits 210 to 21n
Is always zero, and does not output a received signal as a result.

The in-phase component I _i ′ (t) of the despread signal and the quadrature component Q _i ′ (t) of the despread signal for the n information channels of simultaneous multiple access are output from the despread circuits 211 to 21n, respectively. You. Also, the in-phase component I ₀ ′ of the despread signal related to the pilot signal common to these n channels
(T) and the quadrature component Q ₀ ′ (t) of the despread signal are
Output from the despreading circuit 210.

These despread signals are disturbed during propagation, such as phase differences, amplitude distortions, and delays. A known value, for example, a pilot spread signal obtained by spreading the primary modulation of the phase information of "0" is transmitted, and an error between the phase difference detected on the receiving side and the known value is measured to generate a signal during propagation. The phase error of the disturbance can be roughly known. Therefore, FIG.
As shown in FIG. 6, a pilot method is generally used in which a pilot signal for transmitting a known value is added to one channel to n-channel information to roughly correct the disturbance during propagation.

For this reason, a case where one pilot channel is added to n information channels will be described.
The same applies to the case where one pilot channel is added to the information channel, or the case where the in-phase component of the primary modulation wave in each spread signal is assigned to information and the orthogonal component is assigned to a pilot signal. In FIG. 16, a despreading circuit (deS
S) Each output of 211 to 21n and a despreading circuit (de
SS) output the phase correction circuits (CMP) 231 to 23
n. FIG. 19 shows this phase correction circuit (CMP).
3 shows one configuration of 231 to 23n.

The in-phase component I of the information channel i is supplied to the input terminals 2300 and 2301 from the despreading circuit (deSS) 21i.
_i ′ (t) and the orthogonal component Q _i ′ (t) of the despread signal are input, respectively. Also, input terminals 2302 and 2303
, The in-phase component I ₀ ′ (t) and the quadrature component Q ₀ ′ (t) of the pilot channel are input from the despreading circuit 210. Subsequently, the in-phase component I _i ′ of the information channel i
(T) indicates to the multipliers 2310 and 2311 that the information channel i
Quadrature component Q _i of '(t) is input to a multiplier 2312 and 2313, in-phase component I ₀ of a pilot channel' (t)
Is input to multipliers 2310 and 2312, and the orthogonal component Q ₀ ′ (t) of the pilot channel is input to multipliers 2313 and 2311. The adder 2320 includes multipliers 2310 and 231
3 is output to the terminal 2340 as the in-phase component I _i (t) of the phase correction signal. Further, the adder 2321
Represents the difference between the output of the multiplier 2312 and the output of the multiplier 2311 as the quadrature component Q _i (t) of the phase correction signal at the terminal 234.
Output to 1.

The outputs of the phase correction circuits (CMP) 231 to 23n are, as shown in FIG.
1 to 24n. Judgment circuit (DEC) 241-2
4n performs mapping for obtaining a phase angle from the in-phase component I _i (t) and the quadrature component Q _i (t) of the phase correction signal, performs quadrant determination based on the phase angle obtained by this mapping, and receives information symbols. Symbol S _i (t) is connected to terminal 25
1 to 25n.

[0030]

In a conventional CDMA transmission system, a spread signal in which a spectrum is spread is generated by multiplying a PSK wave of a primary modulation wave by a spread code sequence such as a Walsh code sequence. In FIG. 2 showing a time response waveform of a spread code string in chips 1 to 3, a broken line shows an example of a conventional spread code string waveform. A code value of 1 is shown in the chip section 1 and the chip section 2, a code value of -1 is shown in the chip section 3, and a code value of 1 is shown in the chip section 4, but the same applies to other cases. When the spreading code values are equal in adjacent chip sections such as chip section 1 and chip section 2, there is no discontinuity in the waveform of the spread signal in adjacent chip sections.

On the other hand, between chip section 2 and chip section 3,
Alternatively, when the spread code values are different from each other, such as between the chip section 3 and the chip section 4, a sharp waveform change appears at the end of the chip section in the spread signal. When the code value is held up to the end of the chip section in all the chip sections, a sharp waveform change occurs at the end of the chip section as shown by the broken line in FIG. 2, and the frequency bandwidth of the spread signal increases extremely. As a result, there is a problem that communication quality deteriorates.

Accordingly, an object of the present invention is to eliminate a drastic fluctuation of a spread code string waveform at the end of a chip section, prevent an increase in frequency bandwidth, and improve communication quality.

[0033]

In order to achieve the above object, according to the present invention, for example, as shown by a solid line waveform in FIG. This is changed so as to eliminate a sudden change in the spread code value in the transition section. Here, the transition section refers to a section that is installed near the end of each chip section and over an adjacent chip section. For example, in the case of FIG. 2, transition section 2 is between chip section 1 and chip section 2, transition section 3 is between chip section 2 and chip section 3, and transition section 4 is between chip section 3 and chip section 4. Become. Note that all transition sections have the same time length R.

As described above, when the spread code value is different in the adjacent chip section, the rapid change of the spread code value in the transition section is eliminated, so that the sharp change of the spread code string waveform at the end of the chip section is eliminated. In addition, it is possible to prevent an increase in the frequency bandwidth. However, if the spreading code sequence waveform is changed and distorted at the end of the chip section, the information phase to be propagated changes, and the communication quality deteriorates if the configuration of the conventional CDMA receiver is used. Occurs.

Therefore, in the present invention, upon demodulation, instead of using the received signal up to the end of the chip section in every chip section, the received signal in the section with little distortion near the center of the chip is used as an effective area, and demodulation is performed. By setting the demodulation section to be used, an unstable value around the transition section is removed, and a stable demodulation operation can be performed. That is, the features of the present invention are as described in the claims. According to the invention of claim 1, the carrier signal is phase-modulated on the transmitting side in accordance with the information and the primary Means for generating a modulated wave; means for generating a spread code string from which a rapid change in the value of a spread code in an end region of a chip section has been eliminated;
Multiplying the next modulated wave to generate a spread spectrum signal, and means for transmitting the generated spread signal,
Means for selecting, from the received signal, a received signal in a demodulation section excluding at least a transition section in which a rapid change in the value of the spreading code has been eliminated, and performing a reverse operation on the received signal selected by the means. A CDMA transmission system comprising means for performing despreading using a spreading code sequence and restoring information.

As described above, a received signal in a demodulation section excluding at least a transition section in which a sudden change in the value of the spreading code is excluded is selected from the received signals, and an inverse is performed using the selected received signal. Since the spreading is performed, a stable demodulation operation can be performed even if the spreading code string at the end of the chip section is changed on the transmission side so as to eliminate a sudden change.

According to a second aspect of the present invention, there is provided a wireless device using the CDMA transmission method according to the first aspect. As means for selecting a received signal, there is a means between the demodulating means for demodulating the received signal and the means for performing despreading, as in the invention according to claim 3, wherein the demodulated signal is demodulated by the demodulating means. It is possible to select a received signal in the demodulation section from among them.

The means for selecting a received signal may be a means for selecting a received signal in a demodulation section from a received signal for each chip section as in the invention according to claim 4. Only when the value of the despreading code differs between adjacent chip sections as in the described invention, it is possible to select a received signal in a demodulation section from received signals.

[0039]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, the transmitter according to this embodiment includes spreading code generation circuits (CGs) 130-1.
A spreading code sequence waveform continuity circuit (CODE-CS) 150 to 15n is inserted between 3n and spreading circuits (SS) 120 to 12n. In this transmitter, the spreading code sequence waveform continuation circuit (CODE-CS) 15
Configurations other than 0 to 15n are the same as those shown in FIG. This spread code string waveform continuation circuit (CODE-CS)
By providing 150 to 15n, as shown in FIG. 2, only when the spread code value differs between adjacent chip sections,
The spreading code value can be gradually changed in the transition section.

FIG. 3 shows a spread code string waveform continuation circuit (CO
DE-CS) 150 to 15n. In the figure, a spread code sequence from a corresponding spread code generation circuit (CG) 13i is input to an input terminal 300, and is input to an adder 301 as it is. The output of the output terminal 306 is taken in and held by the latch register (REG) 305 at the leading edge of the clock signal applied to the clock terminal (CLK) 307. The adder 301 has an input terminal 300
Code and latch register (REG) 3
The difference from the value held in 05 is output. The output value of the adder 301 is multiplied in a multiplier 302 by a value output from a smoother (SMO) 303. The output of the multiplier 302 is added to the output value of the latch register 305 in the adder 304, and the added value is output from the output terminal 306.

Here, as shown in FIG. 4, the smoother (SMO) 303 outputs a value whose output (t) continuously changes from 0 to 1 in each transition section, for example, a value represented by Formula 1. . The smoother output (t) is the chip section τ
Since the values are periodically output, the output values for one chip section are stored in the ROM, and the values shown in FIG. 4 can be output periodically by sequentially reading out the output values.

[0042]

(Equation 1)

Next, the operation of the spread code sequence waveform continuity circuit (CODE-CS) will be described. Since the operation is periodic with respect to the chip section, the operation from time t = R / 2 to time t = 2τ + R / 2 will be described, but the same applies to other chip sections. Trailing edge of transition section t = R / 2
It is assumed that a clock is applied to the clock terminal (CLK) 307 and the spread code value of the next chip section is determined. As shown in FIG. 2, at time t = R / 2, the output of the output terminal 306 is “1”, and thus “1” is captured and held in the latch register (REG) 305.
The input terminal 300 has a spread code value 1 of chip section 2
Is applied. Since the output of the latch register (REG) 305 is equal to the input of the input terminal 300, the output of the adder 301 becomes 0. Therefore, regardless of the output value of the smoother (SMO) 303, the output of the multiplier 302 changes in the transition section 2
, The output of the adder 304 remains unchanged at 1, and the value 1 is continuously output to the output terminal 305. Further, at the trailing edge t = τ + R / 2 of the transition section 2, the latch register (REG) 305 captures and holds the output value 1, and the input terminal 300 supplies the next chip section 3
Is applied.

Therefore, the output of the adder 301 is -2, but the output of the smoother (SMO) 303 is 0 until the leading edge of the transition section 3, so that the multiplier 302 outputs the value 0 continuously. . However, the output terminal 306 has the multiplier 304
And the sum of the latch register (REG) 305 is output, so that the value 1 held in the latch register 305 is continuously output up to the leading edge of the transition section 3. In transition section 3, the output of the smoother 303 rises from the value 0 at the leading edge and continuously increases to the value 1 at the trailing edge. Therefore, the output of the multiplier 302 changes from 0 to -2. Thus, the sum of the output of the multiplier 304 and the value held in the latch register 305 appears at the output terminal 306 while changing from 1 to −1. For this reason, the spread code value of the transition section 3 is shaped into a waveform that changes smoothly as shown in FIG. Further, at the end of the transition section 3, the value -1 of the output terminal is taken into the latch register 305, and the operation shifts to the next operation, and the same operation as described above is performed.

As described above, the spread code string waveform continuation circuit (C
By providing ODE-CS) 150 to 15n, when the spread code value is different in the adjacent chip section, the spread code value is gradually changed in the transition section, and a sharp change in the spread code sequence waveform at the end of the chip section is eliminated. In addition, it is possible to prevent an increase in the frequency bandwidth. However, when the waveform of the spread code string at the end of the chip section is distorted, the information phase to be propagated changes, and the communication quality deteriorates if the configuration of the conventional CDMA receiver is used.

In order to perform communication with a predetermined bandwidth,
The frequency band of the transmission wave is band-limited by the band-limiting circuit (BPF) 141. In this case, if the phase is made continuous as described above, the distorted waveform in the transition section affects the preceding and subsequent sections as interference. And the communication quality is degraded. That is, as shown in FIG. 6, k band delay units 1401 to 14 are used as a band limiting circuit (BPF) 141.
And 0k, multiplied by the tap coefficients W ₁ to _W-k to signal delayed by these delaying units 1401~140k multiplier 1
When a transversal filter composed of 411 to 141k and a summation circuit (SUM) 1420 for summing up the signals from the multipliers 1411 to 141k is used, a signal corresponding to a distorted waveform in a transition section is input to this filter. The output of the filter is affected by the sections before and after the transition section, and different frequency components are mixed in the output desired frequency band, which deteriorates the communication quality.

Therefore, in the receiver according to this embodiment, as shown in FIG. 6, a demodulation section is set within a section excluding a transition section in each chip section, and an inverse is set using a received signal value in this demodulation section. I try to spread. Therefore, in the receiver, as shown in FIG.
A demodulation circuit (deMOD) 201 and a despreading circuit (deS
S) Select circuit (switch circuit) between 210 and 21n
251 and 252, and despreads the in-phase component i (t) of the demodulated signal from the demodulation circuit 201 and the quadrature component q (t) of the demodulated signal only when the timing signal is output from the timing control circuit 253. Circuit (deSS) 210
21n. Note that this receiver is the same as that shown in FIG. 16 except that the selection circuits 251 and 252 and the timing control circuit 253 are provided.

Here, the timing control circuit 253 outputs the above-described timing signal in a demodulation section within each chip section based on a signal output for each chip, for example, a chip synchronization signal. This demodulation section is set to a section near the chip center where distortion is small, and its start timing is after R / 2 and its end timing is before τ-R / 2. In this case, for example, when the demodulation period is set by sampling using the system clock of the receiver, as shown in FIG. 8, when the number of samples in the chip section is n and the number of samples in the demodulation section is m, the number of samples is m / 2
When the timing signal is output, the output of the timing signal is stopped when the output reaches nm / 2-1, so that the timing signal can be output only in the demodulation section described above. Note that the number of samples becomes n / 2 until the number of samples becomes m / 2, and the number of samples exceeds n-m / 2-1.
Until becomes, the discarded section does not use the received signal value.

If the output of the demodulation circuit 201 is A / D converted by an A / D converter and despreading is performed based on the converted value, the timing of the A / D conversion is obtained. The above-mentioned sampling may be performed.
Further, when the despread code value is the same as the adjacent chip section,
Since there is no discontinuous point, the above-described timing signal may be output in all of the chip sections. In this case, as shown in FIG.
51, 252, selection circuits 2112, 2113, and timing control circuit 211 having the same configuration as the timing control circuit 253.
1 is provided in each of the despreading circuits (deSS) 210 to 21n, and based on the despreading code sequence in the despreading circuit (deSS), the timing control circuit 2111 determines whether the despreading code value is the same as that of the adjacent chip section. It is only necessary to determine whether or not the above-described timing signal is output only when the despread code value is different from the adjacent chip section. By doing so, when the despread code value is the same as the adjacent chip section, the in-phase component i of the demodulated signal in the transition section
(T), the quadrature component q (t) can also be used in the despreading process, so that the accuracy of demodulation can be improved.

Therefore, according to this embodiment, when the spread code value differs in the adjacent chip section, the spread code value is gradually changed in the transition section on the transmitter side, and the spread code sequence waveform at the end of the chip section is changed. Eliminating severe fluctuations to prevent an increase in the frequency bandwidth, and the receiver performs despreading using the received signal value in the demodulation period in each chip section. Demodulation can be performed accurately without being affected by the distortion of the waveform, and the communication quality can be improved.

Each of the circuits shown in the above embodiments can be understood as a means for realizing each function. Since the above-described communication is performed between the mobile station and the base station, both the mobile station and the base station include the above-described transmitter and receiver. Therefore, when the mobile station is a wireless device such as a mobile phone, the wireless device is provided with the above-described transmitter and receiver.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a CDMA transmitter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a spread code string waveform in chip sections 1 to 4;

FIG. 3 is a spread code sequence waveform continuation circuit (CODE-CS).
FIG. 3 is a diagram showing the configuration of FIG.

FIG. 4 is a diagram showing output characteristics of a smoother (SMO).

FIG. 5 is a diagram showing a configuration of a band limiting circuit (BPF).

FIG. 6 is a diagram for explaining a transition section and a demodulation section in each chip section.

FIG. 7 is a diagram illustrating a configuration in which a selection circuit and a timing control circuit are provided between a demodulation circuit (deMOD) and a despreading circuit in a CDMA receiver according to an embodiment of the present invention.

FIG. 8 is an explanatory diagram when a demodulation period is set based on the number of samples.

FIG. 9 is a diagram illustrating a configuration in which a selection circuit and a timing control circuit are provided in a despreading circuit (deSS).

FIG. 10 is a diagram showing a configuration of a conventional CDMA transmitter.

11 is a diagram showing a waveform of a primary modulated wave of the CDMA transmitter shown in FIG. 10 in a symbol 0 and a symbol 1 section.

FIG. 12 is a diagram illustrating an example of a bit arrangement (bit constellation) of QPSK.

FIG. 13 is a diagram illustrating an example of a bit arrangement (bit constellation) of an offset QPSK.

FIG. 14 is a diagram illustrating an example of a segment configuration in a symbol section of a primary modulation wave.

FIG. 15 is a diagram illustrating an example of a chip configuration in a segment section.

FIG. 16 is a diagram illustrating a configuration example of a conventional CDMA receiver.

17 is a diagram illustrating a configuration example of a demodulation circuit (deMOD) in the CDMA receiver illustrated in FIG.

18 is a diagram illustrating a configuration example of a despreading circuit (deSS) in the CDMA receiver illustrated in FIG.

19 is a diagram illustrating a configuration example of a phase correction circuit (CMP) in the CDMA receiver illustrated in FIG.

[Explanation of symbols]

100 to 10n: Information input terminal, 110 to 11n: Phase modulation circuit (MOD), 120 to 12n: Spreading circuit (SS), 130 to 13n: Spreading code generation circuit (CG), 140: Summation circuit (SUM), 141 ... Band limiting circuit (BPF), 142 ... Transmission circuit (TX), 151-15n ... Spreading code sequence waveform continuation circuit (CODE)
-CS), 201: demodulation circuit (deMOD), 202: carrier reproduced wave, 203: synchronization detection circuit (SYNC), 204: reception control circuit (CNT), 210 to 21n: despreading circuit (deSS), 231 to 23n ... Phase correction circuit (CMP), 241 to 24n. Judgment circuit (DEC), 251 to 25n. Output terminal, 253, 2111. Timing control circuit, 251, 252, 2112, 2113.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K004 AA05 FA05 FF00 FF05 5K022 EE02 EE25 5K067 AA11 AA23 BB03 BB04 CC00 CC10 GG01 GG11 HH21

Claims (5)

[Claims] 1. A means for generating a primary modulation wave by phase-modulating a carrier signal in accordance with information on a transmitting side, and a sharp change in a value of a spreading code in an end region of a chip section is eliminated. Means for generating a spread code string generated by the means, multiplying the spread code string generated by the means by the primary modulation wave to generate a spread signal, and transmitting the generated spread signal. Means on the receiving side for selecting, from among the received signals, a received signal in a demodulation section excluding at least a transition section in which a rapid change in the value of the spreading code has been eliminated, and a receiving signal selected by this means. Means for performing despreading using a despreading code sequence and restoring information.
MA transmission method. 2. A means for phase-modulating a carrier signal in accordance with information to generate a primary modulation wave, and a spread code sequence from which a rapid change in a spread code value in an end region of a chip section has been eliminated. Means for generating a spread signal obtained by multiplying the spread code sequence generated by the means by the primary modulation wave to generate a spread signal, and transmitting the generated spread signal; and Means for selecting a received signal in a demodulation section excluding at least a transition section in which a sudden change in the value of the spreading code is excluded; and despreading the received signal selected by the means using a despreading code sequence. And a means for restoring information by using the CDMA transmission method. 3. A receiving means for receiving and demodulating the transmitted spread signal, wherein the means for selecting a received signal selects a received signal in the demodulation section from the demodulated received signal. A wireless device using the CDMA transmission method according to claim 2, wherein 4. The apparatus according to claim 2, wherein said means for selecting a reception signal selects a reception signal in said demodulation section from said reception signals for each chip section. Wireless device using the CDMA transmission method. 5. A means for selecting a received signal, comprising: selecting a received signal of the demodulation section from the received signals only when a value of a despread code is different in an adjacent chip section based on the despread code string. The radio equipment using the CDMA transmission method according to claim 2, wherein the radio equipment is selected.