JP2001068950A - Gate bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To much more enhance the reliability and the characteristic of a gate bias circuit. SOLUTION: The gate bias circuit is provided with a 1st FET 1 whose gate is connected to a signal line 6 and whose source is connected to ground, and a 2nd FET 2 whose drain is connected to ground, whose gate receives a prescribed bias voltage Vcont, and whose source is connected to a drive power supply VB via a resistor R1. Then the signal line 6 and the source of the 2nd FET 2 are interconnected. The drain-source resistance of the 2nd FET 2 is part of a breeder resistor that is a resistor connected in parallel with an output terminal to reduce a voltage regulation of a gate bias circuit of the 1st FET 1. Thus, while a gate voltage Vgs of the 1st FET 1 is set to a desired value, the drain-source resistance of the 2nd FET 2 is set nearly to a characteristic impedance of the signal line 6 at the same time so as to obtain a desired gain and to reduce an input return loss altogether.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate bias circuit, and more particularly to a gate bias circuit having improved flexibility in setting a bias and durability against static electricity.

[0002]

2. Description of the Related Art Conventionally, a gate bias circuit has, for example,
Applied to FET circuits. FIG. 4 shows a gate bias circuit of Conventional Example 1. In FIG. 4, for example, a resistor R5
By using a resistance value of 50Ω for 0, the input return loss and the stability can be improved at a relatively low frequency of the microwave simultaneously with the setting of the gate bias of the first FET.

FIG. 5 shows a gate bias circuit of a second conventional example. Referring to FIG. In this case, the second
Since the FET functions as an electrostatic protection circuit, the configuration is strong against static electricity.

[0004] As a third conventional example similar in technical field to the present invention, there is "Differential amplifier and operational amplifier" disclosed in Japanese Patent Application Laid-Open No. H11-027062. In the third conventional example, the bias stage 3 in the figure attached to the publication includes a sixth transistor 9 and a seventh transistor 11, and the gate voltage of the sixth transistor 9 fluctuates. Is changing. The third conventional example aims at simultaneously improving the input return loss, improving the stability as an amplifier, optimally setting the gate voltage, and preventing electrostatic breakdown.

[0005] Japanese Unexamined Patent Application Publication No. 11-0668038 discloses "Electrostatic destruction protection circuit in semiconductor integrated circuit device".
Is designed so that the protection transistor is not destroyed by abnormal static electricity. In Conventional Example 4, a first P-channel MOS transistor having a source / drain connected between a signal line connected to an external connection terminal and ground, a drain connected to the gate of the first MOS transistor, and a source connected A second P-channel MOS transistor having a gate connected to the power supply line via the first resistor and a gate connected to the ground via the second resistor.

The “Electrostatic discharge protection circuit and semiconductor integrated circuit” of Japanese Patent Application Laid-Open No. 05-136360 of Conventional Example 5 is described in J.
The purpose of the present invention is to properly protect the FET from electrostatic damage, and two JFETs are provided as variable impedance elements between the signal input terminal and GND and between the negative power supply Vss.

[0007] An opto-electronic integrated circuit disclosed in Japanese Unexamined Patent Publication No. Sho 63-169821, which is a conventional example 6, is intended for application to high-speed optical communication. And a series connection circuit of a first field-effect transistor, and these two circuits are connected in an H-shape.

[0008]

However, in the above-mentioned prior art example 1, the first resistance value is larger than the resistance value of the resistor R50.
Have lower gate forward impedance. For this reason, when static electricity gets on the signal line, there is a problem that a large current flows to the gate and the gate insulating film is likely to be destroyed.

Further, in the conventional example 2, the gate voltage of the second FET cannot be set variably or freely. Therefore, the drain-source resistance of the second FET cannot be set to an intended value, for example, 50Ω. Therefore,
At the same time as setting the gate bias of the first FET,
There is a problem that input return loss and stability cannot be improved.

In the prior art 3, the voltage at the intermediate point N3 of the two transistors is changed by the fluctuation of the gate voltage of the sixth transistor 9 in the attached drawing of FIG.
N / OFF.

Further, the conventional examples 4 and 5 have similar purposes, but have different circuit configurations. Conventional example 6
Have similarities in the external circuit configuration, but dissimilar purposes and applications.

An object of the present invention is to provide a gate bias circuit having higher reliability and characteristics.

[0013]

In order to achieve the above object, a gate bias circuit according to the first aspect of the present invention comprises a first FE having a gate connected to a signal line and a source grounded.
T, a second FE having a drain grounded, a gate connected to a terminal of a predetermined bias voltage (Vcont), and a source connected to a terminal of a drive power supply (VB) via a resistor (R1).
T, and the signal line and the source of the second FET are further connected to each other.

According to a second aspect of the present invention, in the gate bias circuit of the first aspect, the bias voltage (Vcont)
A resistor (R2) is further connected between the terminal and the source terminal.

According to a third aspect of the present invention, in the gate bias circuit of the second aspect, the bias voltage (Vcont)
A resistor (R10) is further connected between the terminal of (1) and ground.

According to a fourth aspect of the present invention, in the gate bias circuit of the third aspect, the bias voltage (Vcont)
(R11) between the terminal of the power supply and the terminal of the drive power supply (VB)
Are further connected.

According to a fifth aspect of the present invention, in the gate bias circuit of the second aspect, a capacitor (C21) and a resistor (R21) are further connected in parallel between the source of the first FET and ground.

According to a sixth aspect of the present invention, in the gate bias circuit of the second or third aspect, the second FET is provided.
A resistor (R3) is further connected between the source and the ground.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a gate bias circuit according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 3, there is shown one embodiment of the gate bias circuit of the present invention.

FIG. 1 shows a gate bias circuit according to the first embodiment. In FIG. 1, the gate bias circuit according to the first embodiment includes two FETs 1 and 2 and two resistors R1 and R2.

In the connection relationship between the two FETs 1 and 2,
The signal line 6 is connected to the gate of the first FET 1,
FET1 is grounded. The gate bias Vcont is connected to the gate of the second FET 2 via the resistor R2, the drain is grounded, and the source is connected to the drive power supply VB via the resistor R1.

In the gate bias circuit of the first embodiment having the above-described configuration, the connection between the first FET 1 and the second FET 2 is based on the relationship between the gate of the first FET 1 and the second FET.
The two sources are connected to each other and further connected to the signal line 6. The source of the first FET 1 is grounded.

In the above connection relationship, the second FET 2
Are grounded. On the other hand, a resistor R1 is also connected to the signal line 6 on the gate side of the first FET1, and the voltage of the drive power supply VB is applied to the other end of the resistor R1.

A resistor R2 is connected to the gate of the second FET2.
Is applied via the gate bias Vcont. At this time, the resistance between the drain and source of the second FET 2 is set to R0
Then, the gate voltage of the first FET 1 becomes equal to a value obtained by dividing the drive power supply voltage VB by the resistors R0 and R1. Therefore, the resistor R0 is a part of the bleeder resistor which is a resistor connected in parallel to the output terminal of the gate bias circuit of the first FET 1 in order to improve the voltage fluctuation rate.

(Explanation of Operation of Embodiment) FIG. 1 will be described. The gate voltage Vgs of the first FET and the source voltage Vgg of the second FET have a relationship of Vgg = Vgs, and the second F
When the gate bias Vcont of ET2 is appropriately selected,
Assuming that the resistance value between the drain and the source of the second FET 2 is R0, Vgg = Vgs = VB × R0 / (R0 + R1).

If the resistor R1 has a high resistance value, the gate-side shunt resistance value of the first FET 1 becomes R0,
At relatively low frequencies in the microwave band, the first FET 1
Since the input impedance of the element is high, the input impedance Zin
Becomes substantially equal to the resistance value R0 between the drain and the source of the second FET2.

For example, VB = −10 V, R1 = 1 KΩ, and the gate bias Vcont is adjusted so that the gate voltage Vgs of the first FET = −0.5 V, and the second FET is adjusted.
2, a resistance value R0 between the drain and the source can be set. At this time, the resistance value R0 = Vgs × R1 / (VB−V
gs) = 0.5 × 1000 / 9.5 = 53Ω, the input impedance Zin = R0 = 53Ω, which can be set to almost 50Ω which is the characteristic impedance of the signal line 6.

(Explanation of Effects) FIG. 1 will be described. As described above, while setting the gate voltage Vgs of the first FET to a desired value, the resistance value R0 between the drain and the source of the second FET 2 is set to about 50Ω which is the characteristic impedance value of the signal line 6 at the same time. it can. Therefore, the input impedance Zin can be made approximately 50Ω by setting the resistor R1 to a high resistance value. Therefore, for example, it is possible to obtain a desired gain and at the same time to improve the input return loss.

In general, an FET operates in an unstable manner at a relatively low frequency in a microwave band. However, since the shunt of the signal line 6 has a relatively low resistance value R0, the loss can improve the stability of the first FET.

Further, the static electricity on the signal line 6 is rapidly alleviated by punch-through between the drain and the source of the second FET, where the drain and the source are connected and a current flows. Therefore, when the integrated circuit of the present invention is mounted or the like, there is an effect that the insulating film of the first FET can be prevented from being damaged by static electricity.

(Other Embodiment) Another embodiment of the present invention will be described with reference to FIGS. First, FIG. 2 will be described.
Since the value of the gate bias Vcont that determines the resistance value R0 between the drain and the source of the second FET is controlled so that the Vt value of the FET is almost constant, for example, the gain of the first FET is optimized. Alternatively, it can be fixed.

In this example, the voltage of the drive power supply VB is
The voltage is divided by 10 and the resistor 11 to determine the gate bias Vcont. Therefore, there is an advantage that the gate voltage of the first FET is automatically set only by applying the driving power supply VB.

Next, FIG. 3 will be described. This example shows a case where the present invention is used with a single power supply by using a self-bias circuit for the first FET. A self-bias circuit is formed by adding a resistor R21 and a capacitor C21 to the source of the first FET.

As an example, the gate voltage Vgs of the first FET
Is -0.5 V, and the source voltage Vgg of the second FET is 0.5
The case of designing to be V is shown below. First, the current value of the first FET is examined so that the negative power supply Vss becomes 1 V, and the resistance value of the resistor R21 is determined. VB = 10V,
Assuming that R1 = 1KΩ and R3 = 10Ω, in order to set the source voltage Vgg of the second FET to 0.5V, the drain-source resistance of the second FET is R0 = 0.5 × 1000.
The voltage of the gate bias Vcont may be determined so that /(10−0.5)−10=43Ω. At this time, R
0 + R3 = 53Ω, and at a relatively low frequency in the microwave band, the input impedance Zin
Becomes approximately equal to the characteristic impedance of the signal line of 50Ω. Further, since the resistance value of the resistor R3 can be reduced, an effect as an electrostatic protection circuit of the second FET can be obtained.
As described above, the same effects as in FIG. 1 can be obtained in FIGS.

A second FET having a drain or a source connected thereto is added to a signal line on the gate side of the first FET, and the drain-source resistance is set to a part of the bleeder resistance of the gate bias circuit of the first FET. It is characterized by being used as

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0037]

As apparent from the above description, in the gate bias circuit of the present invention, the signal line is connected to the gate of the first FET, the source is grounded, and the drain of the second FET is grounded and connected to the gate. The bias voltage (Vcont) is applied, the source is connected to the drive power supply (VB) via the resistor (R1), and the signal line and the source of the second FET are connected.

The voltage of the gate bias Vcont is applied to the gate of the second FET via the resistor R2. If the resistance value between the drain and the source of the second FET at this time is R0, this resistance R0 becomes a part of the bleeder resistance of the gate bias circuit of the first FET. Therefore, the first FE
While the gate voltage Vgs of T is set to a desired value, the resistance value R0 between the drain and the source of the second FET can be set substantially to the characteristic impedance value of the signal line. Can be improved.

[Brief description of the drawings]

FIG. 1 shows a circuit configuration example of a first embodiment of a gate bias circuit of the present invention.

FIG. 2 shows a gate bias circuit according to a second embodiment.

FIG. 3 shows a gate bias circuit according to a third embodiment.

FIG. 4 shows a gate bias circuit of Conventional Example 1.

FIG. 5 shows a gate bias circuit of Conventional Example 2.

[Explanation of symbols]

 1, 2, 11, 21, 22, 31, 31 FET 6 Signal line 12 FET 16, 26, 36, 46 Signal line C21 Capacitor R0 Resistance value between drain and source of second FET2 R1, R2, R3, R21 , R50 Resistor VB Drive power supply Vcont Gate bias of second FET Vgg Source or drain voltage of second FET Vgs Gate voltage of first FET Zin Input impedance

Claims (6)

[Claims] A first FET having a gate connected to a signal line and a source grounded, a drain connected to a ground and a gate connected to a predetermined bias voltage (Vco).
nt) and a second FET whose source is connected to the terminal of the driving power supply (VB) via a resistor (R1). The second FET is connected between the signal line and the source of the second FET. A gate bias circuit, wherein the gate bias circuit is further connected. 2. The gate bias circuit according to claim 1, wherein a resistor (R2) is further connected between a terminal of the bias voltage (Vcont) and a source terminal. 3. The gate bias circuit according to claim 2, wherein a resistor (R10) is further connected between a terminal of the bias voltage (Vcont) and ground. 4. The gate bias circuit according to claim 3, wherein a resistor (R11) is further connected between a terminal of the bias voltage (Vcont) and a terminal of the driving power supply (VB). . 5. The gate bias circuit according to claim 2, wherein a capacitor (C21) and a resistor (R21) are further connected in parallel between the source of said first FET and ground. . 6. The gate bias circuit according to claim 2, wherein a resistor (R3) is further connected between a source of the second FET and ground.