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JP2001085706A - Optical semiconductor device module - Google Patents

Optical semiconductor device module

Info

Publication number
JP2001085706A
JP2001085706A JP25741099A JP25741099A JP2001085706A JP 2001085706 A JP2001085706 A JP 2001085706A JP 25741099 A JP25741099 A JP 25741099A JP 25741099 A JP25741099 A JP 25741099A JP 2001085706 A JP2001085706 A JP 2001085706A
Authority
JP
Japan
Prior art keywords
optical semiconductor
semiconductor element
optical
electrode
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25741099A
Other languages
Japanese (ja)
Inventor
Mitsuo Yanagisawa
美津夫 柳沢
Shinichi Koriyama
慎一 郡山
Kenji Kitazawa
謙治 北澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP25741099A priority Critical patent/JP2001085706A/en
Publication of JP2001085706A publication Critical patent/JP2001085706A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Optical Couplings Of Light Guides (AREA)
  • Light Receiving Elements (AREA)

Abstract

(57)【要約】 【課題】光半導体素子内に暗電流よりも大きい逆電流を
生じるのを解消し、光半導体素子の出力電気信号の応答
速度の劣化を抑制して、高速通信用として好適なものと
すること。 【解決手段】光信号を受光して電気信号に変換する光半
導体素子4が搭載されるとともに、光半導体素子4の入
力を行う第一の導体パターンと光半導体素子4の出力を
行う第二の導体パターンを形成した略直方体状の絶縁基
体20を具備して成り、第二の導体パターンに容量結合
部15を設けた。
(57) [Problem] To eliminate reverse current larger than dark current in an optical semiconductor element and suppress deterioration of response speed of an output electric signal of the optical semiconductor element, suitable for high-speed communication. Things to do. An optical semiconductor element for receiving an optical signal and converting the optical signal into an electrical signal is mounted, and a first conductor pattern for inputting the optical semiconductor element and a second conductor pattern for outputting the optical semiconductor element. An insulating substrate 20 having a substantially rectangular parallelepiped shape having a conductor pattern was provided, and a capacitive coupling portion 15 was provided on the second conductor pattern.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、光ファイバ通信シ
ステム等に使用され、光ファイバ等からの光を受光し電
気信号に変換する光半導体素子モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device module used in an optical fiber communication system or the like, which receives light from an optical fiber or the like and converts the light into an electric signal.

【0002】[0002]

【従来の技術】従来の光半導体素子モジュール(以下、
光モジュールという)を図2に示す。同図(a)は蓋体
を除いた光半導体素子モジュールの平面図、(b)は
(a)のA−A線における断面図である。同図におい
て、1は略直方体状の光半導体素子収納用パッケージ
(以下、光パッケージという)、2は光出射端が光パッ
ケージ1内に引き込まれた光ファイバ、3はセラミック
ス等から成り、光半導体素子4を搭載するキャリアとし
ての略直方体状の光半導体素子搭載用の絶縁基体、4は
フォトダイオード等の受光素子(光電変換素子)から成
り、光ファイバ2の光出射端と受光部が対向するように
配置される光半導体素子、5は光半導体素子4にバイア
ス電圧等の駆動信号の入力および出力信号の取り出し等
を行うためのボンディングワイヤ、6は絶縁基体3の表
面に形成されたボンディングワイヤ接続用のメタライズ
層、7は外部へ出力信号を取り出すための電極パッド9
等が形成された配線基板、8は光パッケージ1内におい
て光ファイバを載置固定するための光ファイバ載置台で
ある。
2. Description of the Related Art A conventional optical semiconductor device module (hereinafter, referred to as "optical semiconductor device module")
An optical module is shown in FIG. FIG. 2A is a plan view of the optical semiconductor element module without a cover, and FIG. 2B is a cross-sectional view taken along line AA in FIG. In FIG. 1, reference numeral 1 denotes a substantially rectangular parallelepiped optical semiconductor element storage package (hereinafter referred to as an optical package), 2 denotes an optical fiber having a light emitting end drawn into the optical package 1, 3 denotes a ceramic or the like, and A substantially rectangular parallelepiped insulating substrate for mounting an optical semiconductor element as a carrier for mounting the element 4 includes a light receiving element (photoelectric conversion element) such as a photodiode, and the light emitting end of the optical fiber 2 faces the light receiving section. 5 is a bonding wire for inputting a drive signal such as a bias voltage to the optical semiconductor element 4 and extracting an output signal, and 6 is a bonding wire formed on the surface of the insulating base 3. A metallizing layer 7 for connection is an electrode pad 9 for extracting an output signal to the outside.
Reference numeral 8 denotes an optical fiber mounting table on which an optical fiber is mounted and fixed in the optical package 1.

【0003】また、図3は他の従来例を示し、同図
(a)は蓋体を除いた光半導体素子モジュールの平面
図、(b)は(a)のB−B線における断面図である。
同図に示すように、光半導体素子搭載用の絶縁基体3の
内部にビアホール10が形成され、そのビアホール10
を通じて駆動信号の入力および出力信号の取り出し等を
行う構成としたものである。そして、電極パッド9は光
パッケージ1の内部側面に形成され、電極パッド9に接
続されたピン,メタライズ層(図示せず)等により外部
に出力信号を取り出すようにしている。また、ボンディ
ングワイヤ5は光半導体素子4の受光面近傍の信号出力
部に一端が接続される信号出力用のものであり、他端が
ビアホール10に接続される。なお、他の構成は図2と
同じであり、また図3と同様の構成のものが公知である
(特許第2638542号公報参照)。
FIG. 3 shows another conventional example. FIG. 3A is a plan view of an optical semiconductor device module without a cover, and FIG. 3B is a cross-sectional view taken along line BB of FIG. is there.
As shown in the figure, a via hole 10 is formed inside an insulating substrate 3 for mounting an optical semiconductor element, and the via hole 10 is formed.
Through which the input of the drive signal and the extraction of the output signal are performed. The electrode pad 9 is formed on the inner side surface of the optical package 1, and an output signal is taken out to the outside by a pin connected to the electrode pad 9, a metallization layer (not shown), or the like. One end of the bonding wire 5 is connected to a signal output portion near the light receiving surface of the optical semiconductor element 4, and the other end is connected to the via hole 10. The other configuration is the same as that of FIG. 2, and a configuration similar to that of FIG. 3 is publicly known (see Japanese Patent No. 2638542).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来の光モジュールには以下のような問題点があった。光
ファイバ2から出射した光は光半導体素子4により電気
信号に変換され、その電気信号は光半導体素子搭載用の
絶縁基体3を通じて光パッケージ1の外部の信号処理回
路等に伝送される。しかしながら、光半導体素子4に
は、光信号の入力がない時にも逆バイアス電圧を印加し
ているため、微小な暗電流による逆電流が流れており、
この暗電流は光半導体素子4中の熱により自由電子,正
孔等の自由電荷が発生することにより生じる。この暗電
流が光半導体素子4外に流れている電流に影響を与え、
例えば外部の信号処理回路等のバイアス電流,電源電流
の一部を光半導体素子4に引き込み、暗電流よりも大き
な逆電流が発生することになる。
However, the above-mentioned conventional optical module has the following problems. The light emitted from the optical fiber 2 is converted into an electric signal by the optical semiconductor element 4, and the electric signal is transmitted to a signal processing circuit or the like outside the optical package 1 through the insulating base 3 for mounting the optical semiconductor element. However, since a reverse bias voltage is applied to the optical semiconductor element 4 even when no optical signal is input, a reverse current due to a minute dark current flows,
This dark current is generated by generating free charges such as free electrons and holes due to heat in the optical semiconductor element 4. This dark current affects the current flowing outside the optical semiconductor element 4,
For example, a part of a bias current and a power supply current of an external signal processing circuit or the like is drawn into the optical semiconductor element 4, and a reverse current larger than a dark current is generated.

【0005】そして、光信号から変換された電気信号
は、先ず光パッケージ1の外部の信号処理回路内の増幅
器(アンプ)により増幅されるが、前記逆電流は増幅器
まで電気信号が到達する速度(応答速度)の劣化に繋が
り、高速伝送になるほど微小な逆電流の影響が大きくな
るため、高速通信用の光モジュールにとって問題となっ
ていた。
[0005] The electric signal converted from the optical signal is first amplified by an amplifier (amplifier) in a signal processing circuit outside the optical package 1. Response speed), and the higher the transmission speed, the greater the effect of minute reverse current. This has been a problem for optical modules for high-speed communication.

【0006】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、光半導体素子内に発生す
る逆電流を解消して暗電流のみとし、光半導体素子より
出力された電気信号の応答速度の劣化を抑制して、高速
通信用として好適な光モジュールとすることにある。
Therefore, the present invention has been completed in view of the above circumstances, and an object of the present invention is to eliminate only a dark current by eliminating a reverse current generated in an optical semiconductor device, and to reduce the electric current output from the optical semiconductor device. An object of the present invention is to provide an optical module suitable for high-speed communication by suppressing deterioration of signal response speed.

【0007】[0007]

【課題を解決するための手段】本発明の光半導体素子モ
ジュールは、光半導体素子が搭載されるとともに、該光
半導体素子の入力を行う第一の導体パターンと前記光半
導体素子の出力を行う第二の導体パターンを形成した略
直方体状の絶縁基体を具備して成る光半導体素子モジュ
ールであって、前記第二の導体パターンに容量結合部を
設けたことを特徴とする光半導体素子モジュール。
An optical semiconductor element module according to the present invention has an optical semiconductor element mounted thereon and a first conductor pattern for inputting the optical semiconductor element and a second conductor pattern for outputting the optical semiconductor element. An optical semiconductor element module comprising a substantially rectangular parallelepiped insulating base on which a second conductor pattern is formed, wherein a capacitive coupling portion is provided on the second conductor pattern.

【0008】本発明は、上記構成により、電気信号出力
用の第二の導体パターンの信号伝送経路に容量結合部を
設けることで、外部のバイアス電流,電源電流等の一部
が光半導体素子内に引き込まれて暗電流よりも大きい逆
電流を生じるのを解消し、非受光時に光半導体素子内に
は暗電流成分のみがあり、その結果光半導体素子の出力
電気信号の応答速度の劣化を抑制して、高速通信用とし
て最適な光モジュールとし得る。
According to the present invention, by providing a capacitive coupling portion in the signal transmission path of the second conductor pattern for outputting an electric signal, a part of an external bias current, a power supply current and the like can be partly provided in the optical semiconductor element. To prevent reverse current greater than dark current from being drawn into the optical semiconductor device, and there is only a dark current component in the optical semiconductor device when no light is received. As a result, deterioration of the response speed of the output electric signal of the optical semiconductor device is suppressed. Thus, an optical module optimal for high-speed communication can be obtained.

【0009】本発明において、好ましくは、前記絶縁基
体の光半導体素子の搭載面に入力電極および出力電極が
形成され、前記第一の導体パターンは、前記入力電極と
そこから前記搭載面の反対面に貫通して入力用電極パッ
ドに接続されるビア導体および前記入力用電極パッドと
から成るとともに、前記第二の導体パターンは、前記出
力電極と前記反対面に形成され出力電極と対向して容量
結合部を構成する出力用電極パッドとから成り、かつ前
記入力電極および出力電極を取り囲むように形成された
接地電極と、前記絶縁基体内部に前記接地電極と対向し
て形成された内装接地電極とを接続する第二のビア導体
とを設けてあることを特徴とする。
In the present invention, preferably, an input electrode and an output electrode are formed on a mounting surface of the insulating substrate on which the optical semiconductor element is mounted, and the first conductor pattern is formed on the input electrode and the opposite surface of the mounting surface from the input electrode. And a via conductor connected to the input electrode pad and the input electrode pad, and the second conductor pattern is formed on the output electrode and the opposite surface, and is opposed to the output electrode and has a capacitance. A ground electrode formed of an output electrode pad constituting a coupling portion, and formed so as to surround the input electrode and the output electrode; and an internal ground electrode formed inside the insulating base so as to face the ground electrode. And a second via conductor that connects the second via conductor and the second via conductor.

【0010】本発明は、このような構成により、容量結
合部および入力電極用のビア導体の周囲に接地電位部を
形成することで電磁遮蔽(電磁シールド)し、外部のバ
イアス電流,電源電流等の一部による電磁結合を抑制し
て、逆電流の発生をさらに防止し暗電流成分のみとし得
る。
According to the present invention, electromagnetic shielding (electromagnetic shielding) is achieved by forming a ground potential portion around a capacitive coupling portion and a via conductor for an input electrode, and an external bias current, power supply current, etc. , The occurrence of a reverse current can be further prevented, and only the dark current component can be obtained.

【0011】[0011]

【発明の実施の形態】本発明の光モジュールについて以
下に説明する。図1(a)は本発明の光モジュールの光
半導体素子および絶縁基体部の部分断面図、(b)は絶
縁基体の光半導体素子の搭載面側の正面図である。同図
において、1は略直方体状の光パッケージ、2は光出射
端が光パッケージ1内に引き込まれた光ファイバ、4は
フォトダイオード等の受光素子(光電変換素子)から成
り、光ファイバ2の光出射端と受光部が対向するように
配置される光半導体素子、5は光半導体素子4から出力
された電気信号の取り出しを行うためのボンディングワ
イヤ、8は光パッケージ1内において光ファイバを載置
固定するための光ファイバ載置台である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An optical module according to the present invention will be described below. FIG. 1A is a partial cross-sectional view of an optical semiconductor element and an insulating base part of an optical module according to the present invention, and FIG. 1B is a front view of the insulating base on the side where the optical semiconductor element is mounted. In FIG. 1, reference numeral 1 denotes a substantially rectangular parallelepiped optical package, 2 denotes an optical fiber whose light emitting end is drawn into the optical package 1, 4 denotes a light receiving element (photoelectric conversion element) such as a photodiode, and the like. An optical semiconductor element 5 in which a light emitting end and a light receiving section are opposed to each other, 5 is a bonding wire for extracting an electric signal output from the optical semiconductor element 4, and 8 is an optical fiber mounted in the optical package 1. It is an optical fiber mounting table for mounting and fixing.

【0012】また、9aは絶縁基体20の光半導体素子
4の搭載面の反対面に設けられ、入力電極13と対向す
る入力用電極パッド、9bは前記反対面に形成され出力
電極9bと対向して容量結合部を構成する出力用電極パ
ッド、10は入力電極13と入力用電極パッド9aとを
接続するビア導体、11は絶縁基体20の内部に接地電
極12と対向して形成された内装接地電極、13はバイ
アス電圧等の駆動信号入力用であって光半導体素子4の
搭載面に形成された入力電極、14は光半導体素子4か
らの電気信号を出力するための出力電極、15は出力電
極14とそれに対向する出力用電極パッド9bとから形
成される容量結合部、20は多層に積層されたセラミッ
クス基板等から成り、略直方体状の絶縁基体である。
An input electrode pad 9a is provided on the surface of the insulating substrate 20 opposite to the surface on which the optical semiconductor element 4 is mounted, and an input electrode pad 9b is formed on the opposite surface to face the output electrode 9b. The output electrode pad 10 which forms a capacitive coupling portion is a via conductor connecting the input electrode 13 and the input electrode pad 9a, and 11 is an internal ground formed inside the insulating base 20 so as to face the ground electrode 12. Electrodes 13 are input electrodes for inputting drive signals such as bias voltage and formed on the mounting surface of the optical semiconductor element 4, 14 are output electrodes for outputting an electric signal from the optical semiconductor element 4, and 15 are outputs The capacitive coupling portion 20 formed by the electrode 14 and the output electrode pad 9b opposed thereto is made of a ceramic substrate or the like laminated in multiple layers, and is a substantially rectangular parallelepiped insulating base.

【0013】本発明の絶縁基体20は、光信号の伝送情
報量がギガビット(109 ビット)オーダーの高速伝送
速度領域において、誘電損失が小さい材料とするのが好
ましく、セラミックス,ガラスセラミックス,ガラス有
機樹脂系複合材料等が良い。具体的には、アルミナ(A
2 3 )セラミックス,窒化アルミニウム(AlN)
セラミックス,窒化珪素(Si3 4 )セラミックス等
である。また、高周波伝送損失を小さくするには、ボン
ディングワイヤ5,入力用電極パッド9a,出力用電極
パッド9b,内装接地電極11,接地電極12,入力電
極13,出力電極14,ビア導体10,第二のビア導体
10a等の信号伝送線路用の導体として、Ag,Cu,
Au,Al,これらを主成分として含む合金等の低電気
抵抗のものが好ましい。
[0013] insulating substrate of the present invention 20, the transmission information amount of the optical signal is in a high-speed transmission speed range gigabit (10 9 bit) order, it is preferable to be small dielectric loss materials, ceramics, glass ceramics, glasses organic Resin-based composite materials are preferred. Specifically, alumina (A
l 2 O 3 ) ceramics, aluminum nitride (AlN)
Ceramics, silicon nitride (Si 3 N 4 ) ceramics and the like. To reduce the high-frequency transmission loss, the bonding wire 5, the input electrode pad 9a, the output electrode pad 9b, the internal ground electrode 11, the ground electrode 12, the input electrode 13, the output electrode 14, the via conductor 10, the second As conductors for signal transmission lines, such as via conductors 10a, Ag, Cu,
Those having a low electric resistance such as Au, Al and alloys containing these as a main component are preferable.

【0014】本実施形態において、駆動信号入力経路を
構成する第一の導体パターンは、入力電極13とそこか
ら搭載面の反対面に貫通して入力用電極パッド9aに接
続されるビア導体10および入力用電極パッド9aとか
ら成り、電気信号出力経路を構成する第二の導体パター
ンは、出力電極14と前記反対面に形成され出力電極1
4と対向して容量結合部15を構成する出力用電極パッ
ド9bとから成る。
In the present embodiment, the first conductor pattern forming the drive signal input path includes the input electrode 13 and the via conductors 10 penetrating therethrough and connected to the input electrode pad 9a through the surface opposite to the mounting surface. The second conductor pattern, which is composed of the input electrode pad 9a and forms an electric signal output path, is formed on the opposite surface to the output electrode 14 and the output electrode 1
4 and an output electrode pad 9b that constitutes the capacitive coupling portion 15 in opposition.

【0015】また、絶縁基体20の搭載面の入力電極1
3および出力電極14の周囲を取り囲むようにして接地
電極12が形成され、接地電極12と絶縁基体20内部
の内装接地電極11とを接続する複数の第二のビア導体
10aがビア導体10に平行に形成される。この場合図
1(a)に示すように、第二のビア導体10aは、ビア
導体10と容量結合部15の周囲に、ビア導体10,容
量結合部15を中心軸とする円筒面に沿って対称的に設
けるのが好ましい。また、第二のビア導体10aの長さ
は、絶縁基体20の厚さ(光半導体素子4の搭載面とそ
の反対面との距離)の1/2±0.1mmとするのが良
く、この範囲から外れると電磁界の乱れが生じ容量結合
部15の結合損失が発生する。
The input electrode 1 on the mounting surface of the insulating substrate 20
A ground electrode 12 is formed so as to surround the periphery of the third electrode 3 and the output electrode 14, and a plurality of second via conductors 10 a connecting the ground electrode 12 and the internal ground electrode 11 inside the insulating base 20 are parallel to the via conductor 10. Formed. In this case, as shown in FIG. 1A, the second via conductor 10a is formed around the via conductor 10 and the capacitive coupling portion 15 along a cylindrical surface around the via conductor 10 and the capacitive coupling portion 15 as a central axis. Preferably, they are provided symmetrically. In addition, the length of the second via conductor 10a is preferably 1 / ± 0.1 mm of the thickness of the insulating base 20 (the distance between the mounting surface of the optical semiconductor element 4 and the opposite surface). If the distance is out of the range, the electromagnetic field is disturbed and coupling loss of the capacitive coupling portion 15 occurs.

【0016】絶縁基体20内部の内装接地電極11は、
ビア導体10および容量結合部15を妨げないように間
隙11aが形成されてあり、間隙11aの大きさは、容
量結合部15の容量結合(電磁結合)を妨げないととも
に高速伝送に適したものが良く、高速伝送速度のビット
レートによって異なるが、縦横の一辺が1.0〜3.0
mmの正方形状の孔とするのが好ましい。1.0mm未
満では、電磁界の乱れが生じ容量結合部15の結合損失
が発生し、3.0mmを超えると、同様に結合損失が発
生する。
The interior ground electrode 11 inside the insulating base 20 is
A gap 11a is formed so as not to obstruct the via conductor 10 and the capacitive coupling portion 15. The size of the gap 11a is suitable for high-speed transmission while not obstructing capacitive coupling (electromagnetic coupling) of the capacitive coupling portion 15. It depends on the bit rate of the high transmission rate, but one side in the vertical and horizontal directions is 1.0 to 3.0.
It is preferable that the hole be a square hole of mm. If it is less than 1.0 mm, disturbance of the electromagnetic field occurs and coupling loss of the capacitive coupling portion 15 occurs. If it exceeds 3.0 mm, the coupling loss similarly occurs.

【0017】また、間隙11aの光パッケージの底面か
らの高さは0.3mm以上が良く、0.3mm未満で
は、電磁界の乱れが生じ容量結合部15の結合損失が発
生する。
The height of the gap 11a from the bottom surface of the optical package is preferably 0.3 mm or more. If it is less than 0.3 mm, disturbance of the electromagnetic field occurs and coupling loss of the capacitive coupling portion 15 occurs.

【0018】本発明の絶縁基体20は、絶縁基体20に
設けられた入力用電極パッド9a,出力用電極パッド9
bを、光パッケージの内側面に設けた入力用電極パッド
9a,出力用電極パッド9bに対応する電極パッド(図
示せず)に各々半田付け等により接続することで光パッ
ケージ内に設置される。
The insulating substrate 20 according to the present invention comprises an input electrode pad 9a and an output electrode pad 9 provided on the insulating substrate 20.
b is connected to an electrode pad (not shown) corresponding to the input electrode pad 9a and the output electrode pad 9b provided on the inner side surface of the optical package by soldering or the like, thereby being installed in the optical package.

【0019】上記実施形態では、光パッケージ内に光フ
ァイバ2の光出射端を引き込んだ構成としているが、こ
のような構成に限らず、絶縁基体20の搭載面の周縁部
に封止用メタライズ層を設け、この封止用メタライズ層
上に球レンズ等の集光レンズを設けたキャップをロウ付
けし、搭載面と反対面の入力用電極パッド9a,出力用
電極パッド9bの各々に金属端子をロウ付けした構成と
し、キャンタイプのパッケージとすることもできる。こ
の場合、光ファイバ2をパッケージ内に取り付ける必要
はない。
In the above embodiment, the light emitting end of the optical fiber 2 is drawn into the optical package. However, the present invention is not limited to such a structure. And a cap provided with a condenser lens such as a spherical lens is brazed on the metallizing layer for sealing, and a metal terminal is provided on each of the input electrode pad 9a and the output electrode pad 9b opposite to the mounting surface. It can be brazed and can be a can type package. In this case, there is no need to mount the optical fiber 2 in the package.

【0020】かくして、本発明は、外部のバイアス電
流,電源電流等の一部が光半導体素子内に流れ込んで暗
電流よりも大きい逆電流を生じるのを解消し、その結果
非受光時には光半導体素子内に暗電流成分のみが存在す
ることになり、よって光半導体素子の出力電気信号の応
答速度の劣化を抑制して、高速通信用として最適な光モ
ジュールとし得る。
Thus, the present invention eliminates a part of an external bias current, a power supply current, or the like flowing into the optical semiconductor element to generate a reverse current larger than the dark current. Since only the dark current component exists in the optical module, deterioration of the response speed of the output electric signal of the optical semiconductor element can be suppressed, and an optical module optimal for high-speed communication can be obtained.

【0021】尚、本発明は上記の実施形態に限定される
ものではなく、本発明の要旨を逸脱しない範囲内で種々
の変更は何等差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes may be made without departing from the scope of the present invention.

【0022】[0022]

【発明の効果】本発明は、電気信号出力経路用の第二の
導体パターンに容量結合部を設けたことにより、外部の
バイアス電流,電源電流等の一部が光半導体素子内に流
れ込んで暗電流よりも大きい逆電流を生じるのを解消
し、その結果非受光時には光半導体素子内に暗電流成分
のみが存在することになり、よって光半導体素子の出力
電気信号の応答速度の劣化を抑制して、高速通信用とし
て好適な光モジュールを構成し得るという作用効果を有
する。
According to the present invention, the provision of the capacitive coupling portion in the second conductor pattern for the electric signal output path allows a part of the external bias current, power supply current, etc. to flow into the optical semiconductor device and cause darkness. This eliminates the occurrence of a reverse current larger than the current, and as a result, when no light is received, only a dark current component exists in the optical semiconductor element, thereby suppressing the deterioration of the response speed of the output electric signal of the optical semiconductor element. Thus, the optical module suitable for high-speed communication can be configured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の光モジュールを示し、(a)は光半導
体素子および絶縁基体部の部分断面図、(b)は絶縁基
体の搭載面側の正面図である。
1A and 1B show an optical module of the present invention, wherein FIG. 1A is a partial cross-sectional view of an optical semiconductor element and an insulating base, and FIG. 1B is a front view of a mounting surface side of the insulating base.

【図2】従来の光モジュールを示し、(a)は光モジュ
ールの蓋体を除いた平面図、(b)は(a)のA−A線
における断面図である。
2A and 2B show a conventional optical module, wherein FIG. 2A is a plan view of the optical module without a cover, and FIG. 2B is a cross-sectional view taken along line AA of FIG.

【図3】従来の他の光モジュールを示し、(a)は光モ
ジュールの蓋体を除いた平面図、(b)は(a)のB−
B線における断面図である。
3A and 3B show another conventional optical module, in which FIG. 3A is a plan view of the optical module without a cover, and FIG.
It is sectional drawing in the B line.

【符号の説明】[Explanation of symbols]

1:光パッケージ 2:光ファイバ 4:光半導体素子 5:ボンディングワイヤ 9a:入力用電極パッド 9b:出力用電極パッド 10:ビア導体 10a:第二のビア導体 11,12:接地電極 13:入力電極 14:出力電極 15:容量結合部 20:絶縁基体 1: optical package 2: optical fiber 4: optical semiconductor element 5: bonding wire 9a: input electrode pad 9b: output electrode pad 10: via conductor 10a: second via conductor 11, 12: ground electrode 13: input electrode 14: output electrode 15: capacitive coupling part 20: insulating base

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】光半導体素子が搭載されるとともに、該光
半導体素子の入力を行う第一の導体パターンと前記光半
導体素子の出力を行う第二の導体パターンを形成した略
直方体状の絶縁基体を具備して成る光半導体素子モジュ
ールであって、前記第二の導体パターンに容量結合部を
設けたことを特徴とする光半導体素子モジュール。
1. A substantially rectangular parallelepiped insulating base on which an optical semiconductor element is mounted and on which a first conductor pattern for inputting the optical semiconductor element and a second conductor pattern for outputting the optical semiconductor element are formed. An optical semiconductor element module comprising: the second conductor pattern provided with a capacitive coupling portion.
【請求項2】前記絶縁基体の光半導体素子の搭載面に入
力電極および出力電極が形成され、前記第一の導体パタ
ーンは、前記入力電極とそこから前記搭載面の反対面に
貫通して入力用電極パッドに接続されるビア導体および
前記入力用電極パッドとから成るとともに、前記第二の
導体パターンは、前記出力電極と前記反対面に形成され
出力電極と対向して容量結合部を構成する出力用電極パ
ッドとから成り、かつ前記入力電極および出力電極を取
り囲むように形成された接地電極と、前記絶縁基体内部
に前記接地電極と対向して形成された内装接地電極とを
接続する第二のビア導体とを設けてあることを特徴とす
る請求項1記載の光半導体素子モジュール。
2. An input electrode and an output electrode are formed on a surface of the insulating substrate on which the optical semiconductor element is mounted, and the first conductor pattern penetrates the input electrode and an opposite side of the mounting surface from the input electrode so that an input is formed. The second conductor pattern is formed on the opposite surface to the output electrode and faces the output electrode to form a capacitive coupling portion. A second electrode connecting the ground electrode formed of the output electrode pad and surrounding the input electrode and the output electrode, and an internal ground electrode formed inside the insulating base so as to face the ground electrode. 2. The optical semiconductor element module according to claim 1, wherein said via conductor is provided.
JP25741099A 1999-09-10 1999-09-10 Optical semiconductor device module Pending JP2001085706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25741099A JP2001085706A (en) 1999-09-10 1999-09-10 Optical semiconductor device module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25741099A JP2001085706A (en) 1999-09-10 1999-09-10 Optical semiconductor device module

Publications (1)

Publication Number Publication Date
JP2001085706A true JP2001085706A (en) 2001-03-30

Family

ID=17306000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25741099A Pending JP2001085706A (en) 1999-09-10 1999-09-10 Optical semiconductor device module

Country Status (1)

Country Link
JP (1) JP2001085706A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197929A (en) * 2001-12-27 2003-07-11 Mitsubishi Electric Corp Photodetector carrier and optical receiver
EP1388916A1 (en) * 2002-08-09 2004-02-11 Agilent Technologies, Inc. - a Delaware corporation - Optoelectronic package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197929A (en) * 2001-12-27 2003-07-11 Mitsubishi Electric Corp Photodetector carrier and optical receiver
EP1388916A1 (en) * 2002-08-09 2004-02-11 Agilent Technologies, Inc. - a Delaware corporation - Optoelectronic package
US6841799B2 (en) 2002-08-09 2005-01-11 Agilent Technologies, Inc. Optoelectronic package

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