JP2001014214A - Memory sharing method and multiprocessor facility using this method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] In a memory sharing method, when there is a difference in memory access speed between a plurality of processors, it is possible to reduce the overhead of a processor having a high memory access speed and prevent the performance of the entire equipment from deteriorating. The purpose is to: SOLUTION: A memory access request is generated from a second processor 120 having a lower memory access speed to a first processor 110 having a higher memory access speed, and the first processor 110 comprises:
A step of executing the memory access of the second processor 120 on behalf of the second processor 120 by the interrupt function during the operation of the processor based on the memory access request. According to this method, the memory access of the second processor 120 to the memory 140 of the first processor 110 is limited to one cycle, and the memory sharing is realized with a constant waiting time regardless of the difference in the memory access speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory sharing method using two or more microprocessors, and a microprocessor facility using the method.

[0002]

2. Description of the Related Art In a facility using two or more microprocessors, one memory is used by two or more microprocessors as a means for transferring data between the microprocessors or reducing the amount of memory used. Sharing. When memory sharing is performed by equipment using two or more microprocessors, a bus release type memory sharing method that uses a memory in a time-sharing manner with a bus arbitration circuit is a method of constructing an inexpensive system using a normal memory. is there.

A conventional bus-release type memory sharing method is shown in FIG.
1 will be described based on a configuration example of the multiprocessor facility shown in FIG. The first processor 10 and the second processor 30 are both connected to the address bus 50 and the data bus 60 of the memory 70.
Are connected to the bus arbitration circuit 20, and the access to the memory 70 of each of the processors 10 and 30 is managed by the bus arbitration circuit 20.

FIG. 12 shows an example of a bus arbitration management rule by the bus arbitration circuit 20. In this bus arbitration, the one that has issued the request first has priority, and if a request occurs at the same time, the request is accepted according to the priority order. The memory sharing operation when the memory access speeds of the first processor 10 and the second processor 30 are equal will be described with reference to FIG.

First, the first processor 10 sends a request signal 1
Is generated, the bus arbitration circuit 20 generates a response signal 1 in accordance with the request signal 1, and the first processor 10 confirms the generation of the response signal 1 and performs memory access. Next, when the request signal 2 is generated from the second processor 30, the bus arbitration circuit 20 generates a response signal 2 according to the request signal 2, and the second processor 30 confirms the generation of the response signal 2 and Perform access.

When the first processor 10 generates a request signal 1 during the memory access of the second processor 30,
The bus arbitration circuit 20 does not generate the response signal 1 because the memory access of the second processor 30 has not been completed,
The processor 10 stops the operation assuming that the request signal 1 is suspended because the response signal 1 has not been generated.
In the operation of the first processor 10 of FIG. 13, the instruction (n +
The fact that 7) is repeated twice indicates that the operation is stopped for one cycle. However, when the memory access speeds of the first and second processors 10 and 30 are equal, the number of operation stop cycles is small, so that the performance of the entire system is not significantly reduced.

[0007] Therefore, when designing a processor facility based on the bus release type memory sharing method, the first and second processors 10 and 30 are designed to have the same memory access speed.

[0008]

However, there are processor facilities in which the first and second processors 10 and 30 have different memory access speeds. As an example, there is a facility composed of a digital signal processor and a microcomputer. Digital signal processors require high-speed memory access to perform digital signal processing, while microcomputers require low-speed memory access to perform system control. A high-speed and inexpensive method for performing data communication between the digital signal processor and the microcomputer is the above-described bus release type memory sharing method.

In such a memory sharing method, when there is a difference between the memory access speeds of the first and second processors 10 and 30, there is a problem that the performance of the entire equipment is significantly reduced. The memory sharing operation when there is a difference in the memory access speed will be described with reference to FIG.

First, the first processor 10 sends a request signal 1
Is generated, the bus arbitration circuit 20 generates a response signal 1 in accordance with the request signal 1, and the first processor 10 confirms the generation of the response signal 1 and performs memory access. Since the memory access speed of the processor 1 is high, the access ends in a short time. Next, when the request signal 2 is generated from the second processor 30, the bus arbitration circuit 20 generates the response signal 2 according to the request signal 2, and the second processor 3
No. 0 confirms the generation of the response signal 2 and performs memory access. Since the memory access speed of the second processor 30 is low, the access takes a long time.

When the first processor 10 generates a request signal 1 during the memory access of the second processor 30,
The bus arbitration circuit 20 does not generate the response signal 1 because the memory access of the second processor 30 has not been completed,
The processor 10 stops the operation assuming that the request signal 1 is suspended because the response signal 1 has not been generated.
In the operation of the first processor 10 in FIG. 14, the instruction (n +
The continuous operation of 7) six times indicates an operation stop of 5 cycles. The overhead of the first processor 10 due to this operation stoppage (excess time not used) is the first,
The number increases as the difference between the access speeds of the second processors 10 and 30 increases.

According to the present invention, in such a memory sharing method, when there is a difference between the memory access speeds of a plurality of processors, the overhead of a processor having a high memory access speed can be reduced, and the performance of the entire multiprocessor facility is reduced. The purpose is to be able to prevent.

[0013]

SUMMARY OF THE INVENTION A memory sharing method according to the present invention is a method for sharing a memory in a facility having a plurality of processors having different memory access speeds. Generating a memory access request from another processor having a lower memory access speed than the high-speed processor, and the high-speed processor uses the interrupt function during the operation of the processor based on the memory access request to generate a request for the other processor. A step of executing a memory access as a proxy.

According to the present invention, when there is a difference in the memory access speed between the processors, it is possible to obtain a memory sharing method capable of reducing the overhead of a processor having a high memory access speed and preventing a decrease in the performance of the entire equipment. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a method for sharing a memory in a facility having a plurality of processors having different memory access speeds, wherein the processor has a high memory access speed. Generating a memory access request from another processor having a lower memory access speed than the high speed processor; andthe high speed processor, based on the memory access request,
A step of executing a memory access of the other processor by proxy by an interrupt function during operation of the processor, wherein a memory transfer between processors having different memory access speeds is executed by a proxy transfer instruction of the high speed processor. By using this method, there is an effect that memory sharing can be realized with a constant waiting time regardless of a difference in memory access speed.

According to a second aspect of the present invention, there is provided a multiprocessor facility comprising a plurality of processors having different memory access speeds and sharing a memory, wherein the processor has a high memory access speed. An interrupt arbitration circuit for connecting to the high speed processor and outputting a proxy transfer instruction corresponding to the memory access of the other processor during operation of the processor in response to a memory access request from another processor having a lower memory access speed than the high speed processor A proxy transfer instruction generating circuit for executing a memory access of the other processor as a proxy in response to a proxy transfer instruction of the interrupt arbitration circuit; a proxy transfer register for transferring data to and from the memory; Address bus and external data connected to registers for A bus for writing / reading from / to the memory from the other processor via the external address bus, the external data bus, and the register for proxy transfer by a proxy transfer instruction corresponding to the memory access request. In response to a proxy transfer instruction of an interrupt arbitration circuit of a high-speed processor, read / write to / from a memory is performed in one cycle between the proxy transfer register and another processor. And read / write via the external address bus and the external data bus. Therefore, the memory access of another processor acting as a substitute for the memory of the high-speed processor is limited to one cycle, and the memory is shared with a certain waiting time regardless of the difference in the memory access speed. .

A third aspect of the present invention is the invention according to the second aspect, wherein a high-speed processor is provided with a pipeline operation function, and a proxy transfer instruction output from the interrupt arbitration circuit is provided in the instruction pipeline. Inserting a proxy transfer instruction output from the interrupt arbitration circuit into the instruction pipeline enables writing / reading to / from the memory at a high speed. This has the effect that reading is performed.

A fourth aspect of the present invention is the invention according to the second or third aspect, characterized in that the semiconductor device is formed on a semiconductor substrate. According to a fifth aspect of the present invention, there is provided a multiprocessor facility including a plurality of processors each having a memory, wherein each processor is provided with another processor during operation of the processor in response to a memory access request from the other processor. An interrupt arbitration circuit that outputs a proxy transfer instruction corresponding to a memory access; a proxy transfer instruction generation circuit that executes a memory access of the other processor as a proxy in response to the proxy transfer instruction of the interrupt arbitration circuit; A proxy transfer register for transferring data; an external address bus and an external data bus connected to the proxy transfer register and another processor; and a ring for connecting an interrupt arbitration circuit of each processor. By a proxy transfer instruction corresponding to the memory access request input through
A write / read to / from the memory from the other processor is performed via the external address bus, the external data bus, and the proxy transfer register, and an interrupt arbitration circuit of each processor is provided. According to the proxy transfer instruction, the read / write with respect to the memory is performed in one cycle between the proxy transfer register and the other processor, and the other processor performs the read / write via the proxy transfer register and the external address bus and the external data bus. Execute. Therefore, the memory access of the other processor to this memory is limited to one cycle, the memory sharing is realized with a constant waiting time regardless of the difference in the memory access speed, and the multiprocessor equipment by the processors having different memory access speeds is provided. It has the effect that it can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a configuration diagram of a multiprocessor facility using a memory sharing method according to a first embodiment of the present invention. The first processor 110 having a high memory access speed is connected to the memory 140, and the memory 1
40 is shared with a second processor 120 having a lower memory access speed than the first processor 110.

The high-speed first processor 110 substitutes a memory access requested by the second processor 120 in response to an interrupt arbitration circuit 111 (to be described in detail later) and a proxy transfer instruction (to be described later) of the interrupt arbitration circuit 111. , A proxy transfer register 113 for transferring data to and from the memory 140, and an external address bus 150 and an external data bus 160 connected to the proxy transfer register 113. The low-speed second processor 120 is connected to the interrupt arbitration circuit 111 of the first processor 110 and the external address bus 150 and the external data bus 160.

The interrupt arbitration circuit 111 is a circuit which is conventionally held by the processor 110, and executes an interrupt process for a factor (external terminal, timer, etc.) generated asynchronously with the program operation. The operation of this interrupt processing is shown in FIG. The first processor 110 (n), (n +
1), (n + 2)... Are sequentially executed. Among these instructions, there are an instruction for permitting an interrupt and an instruction for disabling an interrupt, and the interrupt enable signal is changed according to the instruction in order to control the permission and inhibition of the interrupt. The interrupt request signal is high (H
When i) is reached, while the interrupt enable signal is low (Lo),
The acceptance of the interrupt is postponed, and the interrupt enable signal goes high again.
When it becomes i, the interrupt is accepted, the process branches to an interrupt routine, and the instructions (p), (p + 1), (p + 2)... are sequentially executed.

In the present invention, a proxy transfer interrupt function is added to the interrupt arbitration circuit 111. The proxy transfer interrupt indicates “executing a proxy transfer instruction for performing a transfer corresponding to a memory access of the second processor 120 during the operation of the first processor 110”, and a memory access request from the second processor 120. , A proxy transfer instruction corresponding to the memory access of the second processor 120 is output to the proxy transfer instruction generation circuit 112. By this proxy transfer interrupt, the interrupt arbitration circuit 111 replaces the bus arbitration circuit 20 in the conventional configuration of FIG.
Arbitration of memory access between the first and second processors 110 and 120 is realized.

The memory sharing operation in the above configuration will be described with reference to FIG. First, the second processor 120 sends the first
A request signal 130 is generated for the processor 110. Then, the interrupt arbitration circuit 111 of the first processor 110 performs an arbitration operation for executing the proxy transfer instruction based on the request signal 130. That is, the interrupt arbitration circuit 111 generates the proxy transfer execution signal 132 together with the response signal 131, and the proxy transfer instruction generation circuit 112 generates the transfer instruction INST according to the proxy transfer execution signal 132. The transfer instruction INST is transmitted to the second processor 12
0 is for performing the requested memory access as a proxy. In the case of a read request, the contents of the memory 140 are transferred to the proxy transfer register 113. In the case of a write request, the contents of the proxy transfer register 113 are transferred to the memory 140. Will be transferred. This transfer instruction uses only one cycle in the first processor 110. The second processor 120 communicates with the proxy transfer register 113 via the external address bus 150.
And read / write via the external data bus 160. The access of the second processor 120 takes a long time.

As described above, the number of cycles required for the proxy transfer instruction is only one cycle irrespective of the memory access speed, so that the overhead of the first processor 110 does not increase even if the difference in the memory access speed increases.
Therefore, it is possible to prevent the overhead of the first processor 110 from increasing as in the related art. Further, in this configuration, since the interrupt function and the transfer instruction inherent in the first processor 110 are used, the first processor 1
10, a proxy transfer interrupt function, a proxy transfer instruction generation circuit,
This can be realized by adding a proxy transfer register. FIG. 4 illustrates the increase in the circuit scale according to the present invention. Since the circuit scale (or a part of the circuit scale) corresponding to the arbitration circuit 20 in the conventional configuration moves to the first processor 110 as the proxy transfer interrupt function, the increase in the circuit size in the entire configuration is caused by the generation of the proxy transfer instruction. Only the circuit 112 and the substitute transfer register 113 are added.

FIG. 5 shows an example in which the first embodiment is embodied in a digital signal processor (corresponding to a first processor). FIG. 5 is a diagram for explaining the configuration focusing on the memory control. As the request / response signal 230, a chip select signal / CS for memory access, enable signals / WE and / RE for write / read access, and a response signal / ACK for notifying the outside of the data transfer operation are provided. These signals are transmitted to the second processor 120 in FIG.
Corresponding to the request signal 130 and the response signal 131.

As the address / data signal 231,
AD [15: 0] and DT [15: 0] are provided. These signals correspond to the external address bus 150 and the external data bus 160 in FIG. These signals are connected to the interrupt arbitration circuit 210, the address register 220, and the data register 221. The address register 221 and the data register 220 are connected to an address bus 240 and a data bus 250, respectively. That is, it corresponds to the proxy transfer register 113 in FIG.

The interrupt arbitration circuit 210 is connected to the proxy transfer instruction generation circuit 211 and the selector 280.
The selector 280 normally supplies the instruction supplied from the instruction memory 270 to the first instruction register 290. However, when the proxy transfer execution signal 232 is generated, the selector 280 transfers the instruction supplied from the proxy transfer instruction generation circuit 211 to the first instruction register 290. 290
To supply. The first instruction register 290 supplies instructions to the first instruction decoder 291 and the second instruction register 292.
The second instruction register 292 supplies an instruction to the second instruction decoder 293. First and second instruction decoders 291,
92 decodes the instruction and supplies a control signal to each functional block. The address bus 240 and the data bus 250 include a data memory 260 corresponding to the memory 140, a proxy transfer register 223, a data memory pointer register 261 used in normal operation, and an arithmetic register 26.
2. The arithmetic unit 263 is connected.

FIG. 6 illustrates the pipeline timing of this digital signal processor. There are five pipeline stages, an IF stage for inputting instruction data from the instruction memory 270, a D1 stage in which a control signal is supplied from the first instruction decoder 291 to each functional block, and a control for each functional block from the second instruction decoder 293. D2 stage to which a signal is supplied, MA stage to which an address is supplied to data memory 260 from address bus 240, data to be supplied to data memory 260 from data bus 250, or data bus 250 from data memory 260
Is provided as an EX stage, to which data is supplied. Write to data memory 260 by transfer command,
Alternatively, the value written to the data register 220 is EX
It takes place at the end of the stage.

First, the write operation will be described with reference to the timing chart shown in FIG. When a request signal by writing is generated by activating / CS and / WE, the address and data of AD [15: 0] and DT [15: 0] are stored in the address register 221 and the data register 220. At the same time, the interrupt arbitration circuit 210
Generates a proxy transfer execution signal 232. In accordance with the proxy transfer execution signal 232, the proxy transfer command generation circuit 211 generates a proxy transfer command, and the selector 280 supplies the proxy transfer command (r → m) to the first command register 290. This proxy transfer instruction instructs each function block to “transfer data from data register 220 to data memory 260”. By this proxy transfer instruction, writing from the terminal to the data memory 260 is performed.

Next, the read operation will be described with reference to the timing chart shown in FIG. When a request signal for reading is generated by activating / CS and / RE, the address of AD [15: 0] is stored in the address register 221. At the same time, the interrupt arbitration circuit 21
0 generates a proxy transfer execution signal 232. In accordance with the proxy transfer execution signal 232, the proxy transfer command generation circuit 211 generates a proxy transfer command (m → r), and the selector 280 supplies the proxy transfer command to the first instruction register 290. This proxy transfer instruction instructs each function block to “transfer data from data memory 260 to data register 220”. By this proxy transfer command, reading from the data memory 260 to the terminal is performed. [Second Embodiment] FIG. 9 is a configuration diagram of a processor facility using a memory sharing method according to a second embodiment of the present invention.

First processor 310, second processor 3
20 and the third processor 330 respectively include an interrupt arbitration circuit 311, 321, 331 and a proxy transfer instruction generation circuit 3.
12, 322, 332, proxy transfer registers 313, 3
23,333. Each processor 310,
320 and 330 are connected to a first memory 314, a second memory 324, and a third memory 334, respectively. Proxy transfer instruction generation circuits 312 and 322 in each processor
332 is a request signal ring 360, a response signal ring 37
0, they are connected in a loop, and the proxy transfer registers 313,
323 and 333 are connected by a shared address bus 340 and a shared data bus 350.

The memory sharing operation of this processor facility will be described with reference to FIG. Each processor 31
When 0, 320, and 330 want to access the memories 314, 324, and 334 connected to other processors, they issue request signals. This request signal is a request signal ring 3
It goes around each processor via 60. Each processor executes the proxy transfer instruction according to the request signal and simultaneously issues a response signal. The response signal circulates through each processor via the response signal ring 370. When the processor that has issued the request signal detects the response signal, the request is accepted, and a series of operations ends. In FIG. 10, a request signal (n) is issued by the first processor 310 and indicates access of the second processor 320 to the memory 324. This signal (n) circulates through the first processor 310, the second processor 320, the third processor 330, and the first processor 310. The second processor 320 determines that the signal (n) is a request for itself, executes the proxy transfer command, and issues a response signal (n) at the same time. This response signal (n) circulates through the second processor 320, the third processor 330, and the first processor 310. The request is accepted by the first processor 310 detecting the response signal (n). Next, the second processor 320 issues a request signal (n + 1). The request signal (n + 1) indicates an access to the memory 334 of the third processor 330. The request signal (n + 1) goes around the third processor 330 and the first processor 310. The third processor 330 determines that the request signal (n + 1) is a request for itself, executes the proxy transfer command, and issues a response signal (n + 1) at the same time. This response signal (n + 1) goes around with the first processor 310 and the second processor 320. The request has been accepted by the second processor 320 detecting the response signal (n + 1).

Also in the second embodiment, since the number of cycles required for the proxy transfer instruction is only one cycle irrespective of the memory access speed, it is possible to suppress a decrease in the performance of the entire processor equipment due to the above series of operations. Therefore, the configuration of this processor facility is extremely effective when a plurality of processors having different memory access speeds are used.

In the first and second embodiments,
A plurality of processors and memories can be formed on a single or a plurality of semiconductor substrates.

[0035]

As described above, according to the present invention, memory sharing between processors having different memory access speeds is performed by using a proxy transfer instruction, so that a memory can be stored with a constant waiting time regardless of a difference in memory access speed. Sharing can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multiprocessor facility using a memory sharing method according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of an interrupt arbitration circuit of the multiprocessor facility.

FIG. 3 is an explanatory diagram of a memory sharing operation of the multiprocessor facility.

FIG. 4 is an explanatory diagram of an increase in circuit scale in the multiprocessor facility.

FIG. 5 is a configuration diagram of a digital signal processor of the multiprocessor facility.

FIG. 6 is an explanatory diagram of pipeline timing of a digital signal processor of the multiprocessor facility.

FIG. 7 is an explanatory diagram of a write operation timing of the digital signal processor of the multiprocessor facility.

FIG. 8 is an explanatory diagram of a read operation timing of the digital signal processor of the multiprocessor facility.

FIG. 9 is a configuration diagram of a multiprocessor facility using a memory sharing method according to a second embodiment of the present invention.

FIG. 10 is an explanatory diagram of a memory sharing operation between processors of the multiprocessor facility.

FIG. 11 is a configuration diagram of a multiprocessor facility using a conventional bus release type memory sharing method.

FIG. 12 is a diagram illustrating the operation of a conventional bus arbitration circuit of a multiprocessor facility.

FIG. 13 is an explanatory diagram of a memory sharing operation of a conventional multiprocessor facility.

FIG. 14 is an explanatory diagram of a memory sharing operation of a conventional multiprocessor facility.

[Explanation of symbols]

110 First processor (high-speed processor) 111, 210, 311, 321, 331 Interrupt arbitration circuit 112, 211, 312, 322, 332 Proxy transfer instruction generation circuit 113, 313, 323, 333 Proxy transfer register 120 Second processor ( 140, 314, 324, 334 Memory 150 External address bus 160 External data bus 220 Data register (register for proxy transfer) 221 Address register (register for proxy transfer) 230 Request signal 231 External address bus, external data bus 240 Address Bus 250 data bus 260 data memory 270 instruction memory 280 selector 290 first instruction register 291 first instruction decoder 292 second instruction register 293 second instruction decoder 310,320, 30 Processor 340 shared address bus 350 the shared data bus 360 request signal ring 370 response signal ring

Claims (5)

[Claims] 1. A method for sharing a memory in a facility having a plurality of processors having different memory access speeds, comprising: providing a processor having a higher memory access speed to another processor having a lower memory access speed than the processor having a higher memory access speed. Generating a memory access request from a processor; and executing the memory access of the other processor on behalf of the other processor by an interrupt function during operation of the processor based on the memory access request. Memory sharing method. 2. A multiprocessor facility comprising a plurality of processors having different memory access speeds and sharing a memory, wherein the memory is connected to a processor having a high memory access speed, and An interrupt arbitration circuit that outputs a proxy transfer instruction corresponding to memory access of another processor during operation of the processor in response to a memory access request from another processor whose memory access speed is lower than that of the high-speed processor; A proxy transfer instruction generation circuit that executes a memory access of the other processor as a proxy in response to a proxy transfer instruction; a proxy transfer register that transfers data to and from the memory; a proxy transfer register and another processor. Provide external address bus and external data bus to be connected A write / read operation to / from the memory from the other processor is performed through the external address bus, the external data bus, and the proxy transfer register in response to a proxy transfer instruction corresponding to a memory access request. Multiprocessor equipment. 3. A high-speed processor is provided with a pipeline operation function, and writes / reads from / to a memory by inserting a proxy transfer instruction output from an interrupt arbitration circuit into an instruction pipeline. The multiprocessor facility according to claim 2, wherein 4. The multiprocessor facility according to claim 2, wherein the multiprocessor facility is formed on a semiconductor substrate. 5. A multiprocessor facility comprising a plurality of processors each having a memory, wherein each of the processors corresponds to a memory access of another processor during operation of the processor in response to a memory access request from the other processor. An interrupt arbitration circuit that outputs a proxy transfer instruction to perform a transfer of the data to and from the memory; a proxy transfer instruction generation circuit that executes a memory access of the other processor as a proxy in response to the proxy transfer instruction of the interrupt arbitration circuit; A proxy transfer register to be performed; an external address bus and an external data bus connected to the proxy transfer register and another processor; a ring connecting interrupt arbitration circuits of the respective processors; and an input through the ring The proxy transfer instruction corresponding to the memory access request Part address bus,
A multiprocessor facility, wherein writing / reading to / from the memory from the other processor is performed via an external data bus and a proxy transfer register.