JP2001015644A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a semiconductor package capable of reducing a mounting area and sufficiently responding to a demand for high-density mounting. SOLUTION: First and second semiconductor chips respectively mounted on the front and back surfaces of the island portion, a plurality of first outer leads extending outward from the periphery of the island portion, and A first outer lead between the first outer leads and a second outer lead extending stepwise outward from the periphery of the island, the first and second semiconductor chips and the second The first and second outer leads were electrically connected and sealed with a sealing member.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a QFP (Quad).
The present invention relates to a semiconductor package such as a flat package and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, with regard to technologies in this kind of field,
For example, there was one as shown in FIG.

FIG. 9 is a sectional view showing the structure of a conventional QFP type semiconductor package.

[0004] This semiconductor package is a surface mount type package in which external terminals are led out from all sides in all four directions, and its assembly is performed in the following order.

First, after mounting one semiconductor chip 101 on the island 102 of the lead frame, the Al electrode of the semiconductor chip 101 and the outer lead group 103 are connected by bonding Au wires 104, respectively.

Next, the semiconductor chip 101 is molded and sealed with a resin 105, and further heat-treated to cure the resin 105.

After the outer lead group 103 led out of the cured resin 105 is plated with solder, the tip of the lead is cut and bent to obtain a semiconductor package having the structure shown in FIG. Is completed.

[0008]

However, in the above-mentioned conventional semiconductor package, since the tip of the lead is cut after plating, there is no adhesion of solder plating on the blade section of the tip of the lead. Shortage was a problem.

That is, as shown in FIG. 10, when mounting the semiconductor package on the mounting substrate 201, the bent lead end 103a is fixed on the mounting substrate 201 by soldering. At this time, since no solder plating adheres to the blade cross section 103b at the tip of the lead, a good solder fret 202 cannot be formed, resulting in insufficient mounting strength.

Further, since the semiconductor package is a package mounted on one chip, the mounting area increases as the circuit scale increases. In this case, there has been a problem that the recent demand for high-density mounting cannot be met.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to reduce the mounting area and achieve a semiconductor device which can sufficiently meet the demand for high-density mounting. To provide a package. Another object is to provide a method of manufacturing a semiconductor package in which a good solder fillet can be easily formed at the tip of a mounting lead and mounting strength can be ensured.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor package according to the first aspect.
First and second semiconductor chips respectively mounted on the front and back surfaces of the island portion, and a plurality of first outer leads extending outward from the periphery of the island portion;
A first outer chip extending between the first outer leads and a second outer lead extending stepwise outward from the island periphery; and the first and second semiconductor chips And the first and second outer leads are electrically connected and sealed with a sealing member.

In the semiconductor package according to the second aspect of the present invention, in the semiconductor package according to the first aspect, the first and second outer leads are formed in such a manner that only the distal ends of the first and second outer leads are exposed. The outer lead is sealed in the sealing member.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor package, a plurality of mounting leads mounted on the package and a plurality of fixed leads fixed to the frame portion are alternately and integrally arranged, and A first step of preparing a lead frame formed such that a tip end surface of a mounting lead on a frame portion side is exposed to a void portion; and a first step and a second step of forming a lead frame on both sides of an island portion of the lead frame.
A second step of mounting the semiconductor chip, a third step of electrically connecting the mounting leads to the first and second semiconductor chips, and a structure at the end of the third step. A fourth step of sealing with a sealing member, a fifth step of plating at least the entire frame portion side of the lead frame, and cutting each of the mounting leads by cutting a side surface of the mounting lead into the frame. And a sixth step of separating from the part is sequentially performed.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor package according to the third aspect of the present invention, the plurality of mounting leads extend outward from a periphery of the island portion. A first outer lead, and a second outer lead extending between the first outer leads and extending outward from the island peripheral portion at a level different from the first outer lead, The third step is characterized in that the electrodes of the first and second semiconductor chips are wire-bonded to the first and second outer leads.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor package according to the fourth aspect, the sizes of the first and second semiconductor chips are different.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the apparatus according to the present invention will be described.

FIG. 1 is a sectional structural view of a semiconductor package according to an embodiment of the present invention, FIG. 2 is a plan structural view of a main part thereof, and FIG.

This semiconductor package is a double-sided type multi-chip package and has two outer leads.
It is a leadless type package that has a stepped configuration and is incorporated inside the sealing resin body. Hereinafter, the structure will be specifically described.

The semiconductor package of the present embodiment has a size of, for example, □ 20 mm, a semiconductor chip mounting island 11 (eg, □ 12 mm size) is formed in the center, and further outward from the periphery of the island 11. Thus, first and second outer lead groups 12, 13 are extended. Here, each of the first and second outer leads 1
2, 13 are staggered, and the first
The outer lead group 12 is disposed at substantially the same plane position as the island 11, while the second outer lead group 13 is disposed at a position one step lower than the first outer lead group 12, and both have a gull-wing shape. Has formed.

In such a structure, a first semiconductor chip 14 having a size of, for example, □ 10 mm is mounted on the front side of the island 11 by an adhesive such as Ag (silver) paste. For example □
A second semiconductor chip 15 having a size of 6 mm is similarly mounted.

Further, each Al of the first semiconductor chip 14
(Aluminum) electrode is the first outer lead group 1
Each of the Al electrodes of the second semiconductor chip 15 is similarly wire-bonded to the second outer lead group 13 by an Au wire 17, respectively.

The entire structure including the gull wing lead portions of the first and second outer lead groups 12 and 13 is sealed with a resin 18 such as epoxy, and the first and second outer leads 12 and 13 are sealed. 13 has a shape exposed only from the resin 18 to the outside (FIG. 3).
reference).

Next, a manufacturing process of the semiconductor package having the structure shown in FIG. 1 will be described with reference to FIGS. 4, 5, 6 and 7.

First, in a first step, a lead frame having a shape as shown in FIG. 4A is prepared.

Here, the upper diagram shown in FIG. 4A is a plan view of the lead frame of the present embodiment, and the lower diagram of FIG. 4A is a cross-sectional view along AA '.

That is, as shown in FIG. 1, the lead frame is provided with mounting leads (first
And the second outer lead groups 12 and 13) and the fixed leads 10a fixed to the frame portion 10 are alternately and integrally arranged (in a cut-off state), and the end surfaces of the mounting leads on the frame portion 10 side. Has a shape that is exposed to the gap 10b. Further, while the first outer lead group 12 is arranged at substantially the same plane position as the island 11, the second outer lead group 13 is arranged at a step different from the first outer lead group 12, and both are gull wings. It is lead processed into a shape.

In the next second step, the first and second semiconductor chips 14 and 15 are mounted on the front and back surfaces of the island 11 of the lead frame, respectively. First, in order to mount the second semiconductor chip 15, a concave jig 21 is prepared as shown in FIG. 5B, and the lead frame is placed face down on the jig. Then, the frame portion 10 of the lead frame, the island 11, the first outer lead group 12, and the frame portion 12a (the island 1
1 is fixed to the frame portion 10), and the second jig 21 is supported on the back surface of the island 11 facing upward.
Is mounted with an adhesive.

Subsequently, to mount the first semiconductor chip 14, as shown in FIG.
Standing portion 22a for supporting the outer lead 12 group
Is prepared, and the lead frame is placed face-up thereon. Then, the frame portion 12a of the lead frame and the first outer lead 12
Since the group is supported by the standing portion 22a of the jig 22, the first semiconductor chip 14 is mounted on the surface of the island 11 facing upward with an adhesive.

In the next third step, the first and second outer lead groups 12 and 13 are wire-bonded to the respective electrodes of the first and second semiconductor chips 14 and 15, respectively. First, in order to perform bonding to the second semiconductor chip 15, as shown in FIG. 6D, upright portions 23a and 23b for supporting the frame portion 10 and the second outer lead group 13 are integrally formed. A jig 23 provided with a recess 23c for protecting the first semiconductor chip 14 is prepared, and the lead frame on which the first and second semiconductor chips 14 and 15 are mounted is mounted thereon. Place it down. Then, the frame portion 10 of the lead frame and the second outer lead group 13 are supported by the upright portions 23a and 23b of the jig 23, respectively, and the first semiconductor chip 14 is stored in the concave portion 23c. Each Al electrode of the second semiconductor chip 15 facing upward and the second outer lead group 13 are wire-bonded with an Au (gold) wire 17.

Subsequently, in order to wire-bond the first semiconductor chip 14, upright portions 24a and 24b for respectively supporting the first outer lead 12 group and the island 11 are formed as shown in FIG. Jig 2 integrally formed
4 is prepared, and the lead frame on which the second semiconductor chip 15 has been wire-bonded is mounted face-up thereon. Then, the first group of outer leads 12 and the island 11 of the lead frame are supported by the standing portions 24a and 24b of the jig 24, respectively, so that the Al electrodes of the first semiconductor chip 14 facing upward and the first The outer lead group 12 is bonded by Au (gold) wire 16 respectively.

In the next fourth step, the structure at the end of the third step is resin-sealed using, for example, a transfer molding method. That is, the thermosetting resin is plasticized in the heating chamber in advance, and the structure at the end of the previous process is loaded into the mold cavity attached to the dedicated molding machine,
Perform mold clamping. Then, the plasticized resin is pressed into the mold cavity heated to the molding temperature (170 ° C.) and cured. Thereby, as shown in FIG. 6F, the first and second outer lead groups 12, 13 are formed.
The entire structure including the gull wing lead is sealed with the resin 18.

In the next fifth step, for example, at least the entire frame portion 10 of the lead frame is plated with solder.

In the next sixth step, as shown in FIG. 7 (g), the side surfaces of the first and second outer lead groups 12, 13 as mounting leads (that is, the gaps 10b to 10c) are formed.
7 (g) of FIG. 7), and the first and second outer lead groups 12 and 13 are cut into the frame portion 1.
Separate from 0. As a result, as shown in FIG.
First and second outer lead groups 1 from the package body
2 and 13 are alternately derived shapes.

Thereafter, if cutting is performed so that only the second outer lead group 13 is not led out of the package body, the semiconductor package having the structure shown in FIGS. 1, 2 and 3 is completed.

As described above, in the semiconductor package of this embodiment, the mounting leads to be originally mounted and the fixing leads to be fixed to the frame portion 10 are formed in a chopped state so that the tips of the mounting leads are not cut. The tip of the mounting lead is still in a state where solder plating is attached. Therefore, a good solder fillet can be easily formed at the tip of the mounting lead, and the mounting strength can be ensured, and the inspection after mounting can be easily performed.

Further, since the semiconductor package of this embodiment is constituted by a two-chip package, the mounting area can be reduced and the mounting density can be increased by increasing the number of pins.

In the above embodiment, the first semiconductor chip 14 and the first outer lead 12 are electrically connected via the wire 16, and the second semiconductor chip 15 and the second outer lead 13 Are electrically connected via the wire 17, but as shown in FIG. 8, the first semiconductor chip 14 and the second outer lead 13 are electrically connected via the wire 16, and the second The semiconductor chip 15 and the first outer lead 12 may be electrically connected via the wire 17.

[0039]

As described above in detail, according to the semiconductor package of the first aspect, since two semiconductor chips are mounted in one package, the mounting area can be reduced by increasing the number of pins. This makes it possible to sufficiently meet the demand for high-density mounting. Further, since the outer leads have a two-stage structure of the first and second outer leads, it is possible to sufficiently cope with a narrow pitch.

According to the semiconductor package according to the second aspect of the present invention, the same effect as that of the first aspect of the present invention is provided, and the first and second outer leads are sealed in the sealing member. Therefore, the size of the entire package can be reduced.

According to the method of manufacturing a semiconductor package according to the third and fourth aspects of the present invention, since plating can be attached to the tip of the mounting lead, a good solder can be attached to the tip of the mounting lead. Fillets can be easily formed. This makes it possible to secure the mounting strength,
In addition, inspection after mounting can be easily performed.

According to the method of manufacturing a semiconductor package according to the fifth aspect of the present invention, the same effects as those of the fourth aspect of the present invention can be obtained, and the sizes of the first and second semiconductor chips can be different. Therefore, wire bonding can be easily performed.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a plan view of a main part of the semiconductor package of FIG. 1;

FIG. 3 is an external view of the back surface side of the semiconductor package of FIG. 1;

FIG. 4 is a process chart showing a manufacturing process of the semiconductor package.

FIG. 5 is a process drawing following FIG. 4;

FIG. 6 is a process drawing following FIG. 5;

FIG. 7 is a process drawing following FIG. 6;

FIG. 8 is a sectional structural view of another semiconductor package of the present invention.

FIG. 9 is a sectional view showing a structure of a conventional QFP type semiconductor package.

FIG. 10 is a sectional view showing a solder fret.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Frame part 11 Island 12 and 13 1st and 2nd outer lead group 14 1st semiconductor chip 15 2nd semiconductor chip 16 and 17 Au (gold) wire 18 Resin

Claims (5)

[Claims] A first semiconductor chip mounted on each of the front and back surfaces of the island portion; a plurality of first outer leads extending outward from a periphery of the island portion; A first outer lead provided between the first outer leads and a second outer lead extending stepwise outward from the island peripheral portion, the first and second semiconductor chips and A semiconductor package characterized by being electrically connected to first and second outer leads and sealed with a sealing member. 2. A structure in which only the distal end portions of the first and second outer leads are exposed, and the first and second outer leads are sealed in the sealing member. The semiconductor package according to claim 1, wherein: 3. A plurality of mounting leads mounted on a package and a plurality of fixed leads fixed to a frame portion are alternately and integrally arranged, and a front end surface of each of the mounting leads on a frame portion side is in a gap portion. A first step of preparing a lead frame formed in an exposed shape; a second step of mounting first and second semiconductor chips on both front and back surfaces of an island portion of the lead frame; and each of the mounting leads A third step of electrically connecting the semiconductor chip to the first and second semiconductor chips; a fourth step of sealing the structure at the end of the third step with a sealing member; A fifth step of plating at least the entirety of the frame portion side and a sixth step of cutting the side surface side of the mounting lead and separating each mounting lead from the frame portion. The method of manufacturing a semiconductor package according to claim. 4. The mounting lead includes a plurality of first outer leads extending outward from a periphery of the island portion, and a step between the first outer leads and the first outer leads between the first outer leads. A second outer lead extending outwardly from the island peripheral portion. The third step comprises: forming electrodes of the first and second semiconductor chips and the first and second electrodes. 4. The method for manufacturing a semiconductor package according to claim 3, wherein the outer leads are wire-bonded. 5. The method according to claim 4, wherein the first and second semiconductor chips have different sizes.