JP2001028394A - Semiconductor device manufacturing method, electro-optical device manufacturing method, semiconductor device and electro-optical device manufactured by these manufacturing methods - Google Patents

Abstract

(57) Abstract: In a method for manufacturing an electro-optical device through a step of performing ion implantation using a resist film, an electro-optical device having no display defects and excellent display characteristics is obtained. After arranging a scanning line on a semiconductor layer on a substrate, a gate insulating film covering the semiconductor layer, and a gate insulating film,
Impurity ions are implanted into the semiconductor layer 1 using the resist film as a mask. The resist film 406 has a shape that covers a scanning line in a region where the scanning line 3 and the data line 6 intersect in the image display region. Thus, the scanning line 3 is prevented from being etched by the developing solution used when the resist film 406 is formed, and an electro-optical device having no display defect and no short circuit between the data line 6 and the scanning line 3 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, and a semiconductor device and an electro-optical device manufactured by these methods. In particular, the present invention relates to a resist used as a mask during ion implantation. Prior to film formation, a method of manufacturing a semiconductor device, a method of manufacturing an electro-optical device, and a method of manufacturing a semiconductor device and an electro-optical device manufactured by these methods, in which a scanning line at an intersection of a scanning line and a data line is covered with a resist film. Belongs to the technical field.

[0002]

2. Description of the Related Art Generally, a thin film transistor (hereinafter referred to as TF) is used.
It is called T. In the case of an active matrix type liquid crystal device having ()) as a switching element, an electro-optical material such as a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate.

[0003] Such a TFT array substrate has a plurality of scanning lines and a plurality of data lines arranged crossing each other on the substrate, and a plurality of scanning lines and data lines arranged at intersections of the scanning lines and the data lines. The thin film transistor includes an electrically connected thin film transistor and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is configured by arranging a gate electrode in the same layer as the scanning line and electrically connected to the semiconductor layer via a gate insulating film. And
A data line is formed thereon via an insulating film.

The above-described TFT array substrate is formed through, for example, the following forming steps.

First, a semiconductor layer made of polysilicon is formed on a glass substrate, and a gate insulating film is formed so as to cover the semiconductor layer. Next, a scan line having a gate electrode is formed over the gate insulating film at a position corresponding to the channel region of the semiconductor layer. After the formation of the scanning line, ion implantation is performed on an arbitrary region of the semiconductor layer using the resist film as a mask. Next, after removing the resist film, an insulating film is formed over the gate insulating film so as to cover the scanning line and the gate electrode, and a source electrode, a drain electrode, and a data line are formed over the insulating film. Further, an interlayer insulating film is formed on this upper layer, and a pixel electrode connected to a drain electrode via a contact hole is formed on the interlayer insulating film to complete a TFT array substrate. The above-mentioned resist film is formed by applying a resist on a substrate, exposing it to light, and developing it so as to be patterned into a predetermined shape.

[0006]

In the case where such a liquid crystal device is used for a device such as a portable information terminal, there has been a strong demand in recent years to reduce the power consumption as much as possible. To reduce the power consumption of the TFT array substrate constituting the liquid crystal device, it is necessary to lower the resistance of the scanning line.
A manufacturing method using aluminum instead of materials such as r and Ta has attracted attention. Further, when a metal containing aluminum is used for the scan line, a multilayer structure in which a high melting point metal such as titanium is stacked on a metal layer containing aluminum is used in order to prevent generation of a projection called a hillock.

However, when forming a resist film used as a mask in the ion implantation step, there is a problem that the aluminum layer of the scanning line is etched by the developing solution. Hereinafter, this will be described in detail with reference to FIG. Note that FIG.
FIG. 3 is a vertical cross-sectional view near an intersection between a data line and a scanning line.

FIG. 15A shows a state in which the scanning lines 3 have been formed before the ion implantation step. The semiconductor layer 1 is disposed on the TFT array substrate 60, and the scanning lines 3 are disposed on the semiconductor layer via the gate insulating film 2. 2 scan lines
It has a layer structure, with the lower layer made of aluminum and the upper layer made of titanium.

FIG. 15B shows a state in which a resist film is disposed. The resist film is formed by applying a resist on a substrate, exposing the resist so that only a portion corresponding to a region of the semiconductor layer where ions are not implanted remains, and developing the resist. Therefore, as shown in the figure, no resist film is formed near the intersection between the scanning line 3 and the data line. When a resist film is formed in such a shape,
As shown in the figure, the side portion of the lower layer made of the aluminum layer of the scanning line is etched by a developing solution used at the time of developing the resist, so that the vertical section of the scanning line has an overhang shape.

Next, after impurity ions are implanted into the semiconductor layer 1 using the resist film as a mask, the resist film is removed.

Next, when the insulating film 4 is formed on the substrate so as to cover the above-described overhanging scanning lines, cracks 4 'are formed in the insulating film 4, as shown in FIG. appear. Therefore, as shown in FIG.
When the data line 6 is formed thereon, the scanning line 3 and the data line 6 are short-circuited by the crack 4 '. As a result, the pixel electrode electrically connected to the short-circuited scanning line 3 and data line 6 cannot perform an arbitrary display, resulting in line defects in the scanning line and the data line, thereby significantly deteriorating the display quality. There is. In addition, even if a short circuit does not occur, the data line 6 may be disconnected near the occurrence of a crack in the insulating film 4, which causes a problem of causing display defects.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and prevents the occurrence of etching of a scanning line by a developing solution used in forming a resist film, thereby forming the scanning line and an insulating film thereon. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a method for manufacturing an electro-optical device capable of preventing a short circuit failure with a data line, and a semiconductor device and an electro-optical device manufactured by these methods. .

[0013]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a region where a first wiring and a second wiring cross each other, comprising the steps of: forming a semiconductor layer; Forming the first wiring, forming a resist film on a predetermined region of the first wiring, implanting impurity ions into the semiconductor layer using the resist film as a mask, Forming the second wiring on a predetermined region of the wiring so as to intersect the first wiring.

According to this structure, in the method of manufacturing a semiconductor device having the step of implanting impurity ions into the semiconductor layer, the resist film is formed so as to cover a region where the first wiring and the second wiring intersect. Therefore, the first wiring in the intersection region between the first wiring and the second wiring is not etched by the developing solution used for forming the resist film, for example, the TMAH aqueous solution. Accordingly, it is possible to prevent the occurrence of cracks in the insulating film disposed in the vicinity of the region where the first wiring and the second wiring intersect and insulate the first wiring from the second wiring. This has an effect that a short circuit between the first wiring and the second wiring or the second disconnection can be prevented, and a semiconductor device having no defect can be obtained.

The present invention is also a method of manufacturing a semiconductor device having a region where a first wiring and a second wiring intersect,
Forming a semiconductor layer, forming the first wiring, forming a resist film on a predetermined region of the first wiring and on a predetermined region of the semiconductor layer, and masking the resist film A step of implanting impurity ions into the semiconductor layer; and a step of forming the second wiring so as to intersect the first wiring on a predetermined region of the first wiring. .

According to such a configuration, simultaneously with formation of a mask used for implanting impurity ions into the semiconductor layer,
Since the resist film is formed so as to cover the area where the first wiring and the second wiring intersect, the first wiring in the intersection area between the first wiring and the second wiring is developed with a developing solution used for forming the resist film, for example, a TMAH aqueous solution. Is not etched. Accordingly, it is possible to prevent the occurrence of cracks in the insulating film disposed in the vicinity of the region where the first wiring and the second wiring intersect and insulate the first wiring from the second wiring. This has an effect that a short circuit between the first wiring and the second wiring or the second disconnection can be prevented, and a semiconductor device having no defect can be obtained.

Further, the step of forming the resist film comprises:
A step of applying a resist on the substrate; and a step of forming the resist film by exposing and developing the resist. According to such a configuration, since the resist is applied on the substrate, a resist having a uniform film thickness can be obtained, and as a result, a resist film having a uniform film thickness distribution in the substrate surface can be obtained. it can. Thereby, ion implantation is performed uniformly in the plane,
For example, even when a plurality of thin film transistors each including a semiconductor layer are formed over a substrate, there is an effect that characteristics of the thin film transistors do not vary in a plane. here,
As a method for applying the resist, a spin coating method, a roll coater method, or the like can be used.

Further, the first wiring contains aluminum. According to such a configuration, since low-resistance aluminum is used, a wiring width can be reduced, a high-definition semiconductor device can be obtained, and a semiconductor device with low power consumption can be obtained because wiring capacitance is reduced. Can be obtained. In the case where a material containing aluminum is used as an electrode material, aluminum is more likely to be etched by a developing solution than other metals, and therefore, it is very effective to cover it with a resist film. The first wiring may be aluminum or an alloy containing aluminum as a main component, or a multilayer metal containing at least one of them.

Further, the first wiring has a multilayer structure including a lower layer containing aluminum and an upper layer containing a high melting point metal. Further, the upper layer is made of a layer containing molybdenum or titanium. According to such a configuration, since a layer containing a high melting point metal such as molybdenum or titanium is formed on a layer containing aluminum, hillocks do not occur in aluminum, and a short circuit between the first wiring and the second wiring due to the hillocks is prevented. This has the effect of preventing generation and obtaining a high-quality semiconductor device. In the case of a multilayer structure in which a layer containing a high melting point metal is arranged over such a layer containing aluminum, a layer containing a high melting point metal has higher etching resistance to a developing solution than a layer containing aluminum. When the development is performed in a state where the resist film is not formed on the gate electrode, only the lower layer is etched by the developer, and the first wiring having the overhang-shaped cross section is formed. As a result, a crack occurs in the insulating film formed over the first wiring, and there is a problem that the second wiring and the first wiring formed on the insulating film are short-circuited through the crack. However, in the present invention, even when the first wiring having the multilayer structure is used, the first wiring corresponding to the intersection between the first wiring and the second wiring is covered with the resist film, thereby forming the first wiring at the intersection. Is not etched by the developer and does not become the first wiring having an overhang-shaped cross section, and the problem that cracks occur in the insulating film covering the wiring can be avoided. This prevents a short circuit between the first wiring and the second wiring or disconnection of the second wiring, and has an effect of obtaining a high-quality semiconductor device.

Further, a method of manufacturing an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a transistor connected to the scanning lines and the data lines. A method for manufacturing an electro-optical device having a region that intersects with a data line, wherein the step of forming the scanning line, the step of forming a resist film on a predetermined region of the scanning line, and the step of masking the resist film Implanting impurity ions into a semiconductor layer forming the transistor, and forming the data line on a predetermined region of the scan line so as to intersect with the scan line. I do.

According to such a configuration, in the electro-optical device formed through the step of implanting impurity ions using the resist film as a mask, for example, simultaneously with the formation of a mask used when implanting impurity ions into the semiconductor layer, Since the resist film is formed so as to cover the region where the scanning line and the data line intersect, the scanning line in the intersection region between the scanning line and the data line is etched by the developing solution used in forming the resist film. Can be suppressed. Thereby, it is possible to prevent the occurrence of cracks in the insulating film interposed between the scanning line and the data line, which occurs near the region where the scanning line and the data line intersect, and to prevent the occurrence of a crack between the scanning line and the data line. This has the effect of preventing a short circuit or disconnection of a data line and obtaining an electro-optical device free from display defects.

In the method of manufacturing an electro-optical device according to the present invention, the step of forming the resist film and the step of injecting the impurity are respectively performed at least twice.
Each of the resist films is formed so as to cover a region where the scanning line and the data line intersect.

According to such a configuration, for example, an LDD structure in which a plurality of semiconductor regions having different impurity concentrations are formed on the same substrate, and a semiconductor region in which a plurality of different impurities are implanted are formed on the same substrate. In a manufacturing method of manufacturing an electro-optical device through a process of performing ion implantation a plurality of times using a resist film as a mask as in the case of forming a complementary transistor structure, a scanning line and data are formed in all of the plurality of implantation mask forming processes. Since the resist film is formed so as to cover the region where the line intersects, the scanning line in the intersection region with the data line is not etched by the developer used for forming the resist film. Thereby, it is possible to prevent the occurrence of cracks in the insulating film interposed between the scanning line and the data line, which occurs near the region where the scanning line and the data line intersect, and to prevent the occurrence of a crack between the scanning line and the data line. A short circuit or disconnection of a data line can be prevented, and an electro-optical device free from display defects can be obtained.

Further, in the method of manufacturing an electro-optical device according to the present invention, a plurality of scanning lines, a plurality of data lines, a transistor connected to the scanning line and the data line, and the scanning line and the data line are connected to each other. A method of manufacturing an electro-optical device having an intersecting region, comprising: forming a first semiconductor layer and a second semiconductor layer on a substrate; and forming the first and second semiconductor layers on the substrate so as to cover the first and second semiconductor layers. Forming a gate insulating film;
A scanning line having a first gate electrode on at least a position of the first semiconductor layer opposed to the channel region; and a second gate on the gate insulating film of the second semiconductor layer at least opposed to the channel region. Forming an electrode, covering a region where the scanning line and the data line intersect, and forming a first resist film corresponding to the first semiconductor layer; and forming the first resist film and the second resist film. Implanting impurity ions into the second semiconductor layer using a gate electrode as a mask, forming a second resist film corresponding to the second semiconductor layer, covering a region where the scanning line and the data line intersect; Performing the second resist film and the first resist film.
Implanting impurity ions into the first semiconductor layer using the gate electrode as a mask, forming an insulating film so as to cover the gate electrode and the scanning line, and intersecting the scanning line on the insulating film. And a step of forming a plurality of data lines.

According to such a configuration, in the case where the step of forming a semiconductor layer having different types of impurity ion regions in the same substrate using the resist film as a mask is performed, the data is formed simultaneously with the formation of the resist film as a mask. Since the resist film is formed so as to cover the scanning line corresponding to the region intersecting the line, the scanning line is protected from the developing solution, and the scanning line is not etched by the developing solution. This allows
It is possible to prevent the occurrence of cracks in the insulating film that occurs near the region where the scanning line and the data line overlap, prevent short-circuiting of the scanning line and the data line or disconnection of the data line, and eliminate display defects. An electro-optical device can be obtained.

Further, the electro-optical device has an image display area and a drive circuit area for controlling display in the image display area, and the drive circuit area has a complementary structure having the first semiconductor layer and the second semiconductor layer. A thin film transistor having a transistor structure is disposed, and the image display area includes the first thin film transistor.
A semiconductor layer is provided.

According to such a configuration, a thin film transistor for pixel display and a thin film transistor having a complementary transistor structure for a driving circuit can be formed on the same substrate in the same step. For this reason, it is not necessary to manufacture the drive circuit in a separate process and externally attach the drive circuit, which has the effect of greatly reducing the manufacturing process of the electro-optical device.

Forming a capacitance line in the same layer as the scanning line and substantially in parallel with the scanning line, wherein a region where the capacitance line intersects with the data line is covered with the resist film. It is characterized by being done. According to such a configuration, similarly to the scanning line, short-circuit between the data line and the capacitance line near the intersection of the data line and the capacitance line is prevented,
This has the effect of obtaining an electro-optical device without display defects.

Further, at least a part of the scanning line and a layer formed of the same layer as the scanning line is covered with the resist film. According to such a configuration,
In addition to the vicinity of each intersection of the data line and the scanning line or the data line and the capacitance line, the scanning line or the capacitance line can be protected from the developing solution, and the scanning line generated by being etched by the developing solution. Alternatively, the width of the capacitor line can be prevented from being reduced. Thereby, the line width of the plurality of scanning lines or capacitance lines on the display surface of the electro-optical device can be always kept constant, and thus there is an effect that an electro-optical device having good display characteristics without display variation in the surface is obtained.

The step of forming the resist film includes:
A step of applying a resist on the substrate; and a step of forming the resist film by exposing and developing the resist. According to such a configuration, since the resist is applied on the substrate, a resist having a uniform film thickness can be obtained, and as a result, a resist film having a uniform film thickness distribution in the substrate surface can be obtained. it can. Thereby, ion implantation is performed uniformly in the plane,
For example, even when a plurality of thin film transistors each including a semiconductor layer are formed over a substrate, there is an effect that characteristics of the thin film transistors do not vary in a plane. here,
As a method for applying the resist, a spin coating method, a roll coater method, or the like can be used.

Further, the scanning line and the layer composed of the same layer as the scanning line contain aluminum. According to such a configuration, since low-resistance aluminum is used, a scanning line or a capacitance line without signal delay between the signal input side and the terminal side can be obtained, and an electro-optical device with no display variation can be obtained. Further, since low-resistance aluminum is used, the wiring width can be reduced, and the wiring capacitance is reduced, so that an electro-optical device with low power consumption can be realized. Furthermore, when a material containing aluminum is used as an electrode material, aluminum is more likely to be etched by a developing solution than other metals, and therefore, it is very effective to cover the surface with a resist film.

Further, the scanning line and a layer composed of the same layer as the scanning line have a multilayer structure including a lower layer containing aluminum and an upper layer containing a high melting point metal. Furthermore,
The upper layer is made of a layer containing molybdenum or titanium.

According to such a structure, since a layer containing a high melting point metal such as molybdenum or titanium is formed on a layer containing aluminum, activation of impurity ions performed under a high temperature condition of, for example, 400 ° C. or more is performed. Even after the process, hillocks are not generated, a short circuit between the scanning lines and the data lines due to the hillocks can be prevented, and an effect of obtaining an electro-optical device with good display characteristics can be obtained. Further, when a multilayer structure in which a layer containing a high-melting point metal is arranged on such a layer containing aluminum is used as a wiring, a scanning line in an intersecting region with a data line is used as a developer in a resist film forming step. Therefore, the scanning lines do not become overhang-shaped, and the insulating film covering the scanning lines does not crack. This has the effect of preventing disconnection beforehand and obtaining an electro-optical device having good display characteristics.

A semiconductor device according to the present invention is characterized by being formed by the above-described manufacturing method. With such a configuration, there is an effect that a high-quality electro-optical device is obtained.

An electro-optical device according to the present invention is characterized by being formed by the above-described manufacturing method. With such a configuration, there is an effect that an electro-optical device having good display characteristics is obtained.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking an example in which the present invention is applied to a liquid crystal device as an electro-optical device.

The structure of the liquid crystal device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image forming area of a liquid crystal device. FIG. 2 is a plan view of a plurality of pixel groups in an image display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a longitudinal sectional view of an image display area and a peripheral driving circuit area of the liquid crystal device, and the longitudinal sectional view of the pixel area is a sectional view taken along line AA ′ of FIG. In each figure, in order to make each layer and each member a size recognizable on the drawing,
The scale is different for each layer and each member.

In FIG. 1, the liquid crystal device comprises an image display area and a peripheral drive circuit area for controlling the image display area.

The image display area includes a capacitor line 3b and a scanning line 3, which are arranged in parallel, a data line 6 which intersects with the scanning line 3, and an intersection of the scanning line 3 and the data line 6. Pixel electrodes 9a arranged in a matrix, and thin film transistors (hereinafter, TFTs) for controlling the pixel electrodes 9a.
30). The source of the TFT 30 is electrically connected to the data line 6 to which the image signal is supplied, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30, which is a switching element, for a certain period, the image signal S1 supplied from the data line 6,
.., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). .

On the other hand, the peripheral drive circuit area includes a scan line drive circuit 104, a data line drive circuit 101, a sampling circuit 301, and a precharge circuit 201. The scanning line driving circuit 104 supplies the scanning signals G1, G2,..., G to the scanning line 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY and its inverted clock, and the like.
m is applied in a pulsed manner in a line-sequential manner. Data line drive circuit 1
01 is the data line 6 based on the power supplied from the external control circuit, the reference clock CLX and its inverted clock, etc., in accordance with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,. Transfer signal X from the shift register as a sampling circuit drive signal every time
, Xn are supplied to the sampling circuit 301 at a predetermined timing via the sampling circuit drive signal line 306. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6, a precharge signal line 204 is connected to the drain or source electrode of the TFT 202, and a precharge circuit drive signal line 206 is connected to the TFT 202. Is connected to the gate electrode of In operation, a precharge signal N is supplied from an external power supply via a precharge signal line 204.
Power is supplied at a predetermined voltage required for writing the RS, and the precharge signal is supplied via the precharge circuit drive signal line 206 at the timing preceding the supply of the image signals S1, S2,. A precharge circuit drive signal NRG is supplied from an external control circuit so as to write NRS. The precharge circuit 201 preferably includes image signals S1, S2,.
Precharge signal NRS (image auxiliary signal) corresponding to n
Supply. The sampling circuit 301 includes a TFT 302
Is provided for each data line 6, and the image signal line 304
The sampling circuit driving signal line 306 is connected to the source electrode of the FT 302 and the gate electrode of the TFT 302. Then, via the image signal line 304,
When the image signals S1, S2,..., Sn are input, they are sampled. That is, transfer signals X1, X2,..., X as sampling circuit drive signals from the data line drive circuit 101 via the sampling circuit drive signal line 306.
When n is input, the image signals S1, S2,..., Sn from the respective image signal lines 304 are sequentially applied to the data lines 6a.

In this embodiment, since polysilicon is used as the semiconductor layer of the TFT 30 in the image display area, the TFT used in the peripheral driving circuit and the TFT 30 in the image display area are formed on the same substrate on the same process. However, it is also possible to form a part of the peripheral drive circuit on another substrate and attach it externally.

In FIG. 2, a plurality of transparent pixel electrodes 9a are provided in a matrix on a TFT array substrate of a liquid crystal device, and data lines 6 and scanning lines are respectively provided along vertical and horizontal boundaries of the pixel electrodes 9a. 3 (dotted line) and a capacitance line 3b (dotted line). The data line 6 is formed in a shape extending in the vertical direction, and the source electrode 6 which is a part of the data line 6 is formed.
a is electrically connected via a contact hole 5a to a source region described later in the semiconductor layer 1 made of a polysilicon film (a hatched portion falling to the left), and the data line 6 is near the source 6a and has a width. It is formed to be wide.
A conductive layer 6b formed in the same layer as the data line 6 is electrically connected to a drain region described later in the semiconductor layer 1 through a contact hole 5b, and the conductive layer 6b is further connected through a contact hole 8 It is electrically connected to the pixel electrode 9a. Further, the scanning line 3 is arranged so as to face the channel region in the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, the semiconductor layer 1 and the scanning line 3 overlap at two places. It has a double gate structure. In the drawing, a portion where the scanning line 3 and the semiconductor layer 1 overlap in a plane, that is, a semiconductor layer at a position corresponding to the gate electrode is hidden by the scanning line and is not shown. The capacitance line 3 b extends substantially linearly along the scanning line 3, and has a protruding portion protruding along the data line 6 from a portion intersecting with the data line 6. Some are located. That is, the semiconductor layer 1
Is extended under the data line 6 and the scanning line 3, and the capacitor line 3 b also extends along the data line 6 and the scanning line 3,
The semiconductor layer 1 and the capacitor line 3b are opposed to each other via an insulating film 2 which is also a gate insulating film to form a storage capacitor. The capacitance line 3b overlaps a part of the pixel electrode 9a in a plane, and also forms a storage capacitance in this region.

Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device 100 includes a liquid crystal layer 50 as an electro-optical material between the TFT array substrate 10 and an opposing substrate 80 arranged opposite thereto. I have.

In the TFT array substrate 10, in the image display area, a base film 12 made of silicon oxide and a semiconductor layer 1 made of polysilicon are arranged on a glass substrate 60. On the semiconductor layer 1, a gate insulating film 2 is arranged. On the gate insulating film 2, a scanning line 3 (not shown) having a two-layer structure in which aluminum is a lower layer and titanium is an upper layer, a gate electrode 3a which is a part of the scanning line, and a capacitance line 3b are arranged. . Then, an insulating film 4 is disposed so as to cover the scanning line 3, the gate electrode 3a, and the capacitor line 3b,
On the insulating film 4, a data line 6 formed in the same layer, a source electrode 6a which is a part of the data line 6, and a conductive layer 6b are arranged. The source electrode 6a is electrically connected to a source region of the semiconductor layer 1 described later by a contact hole 5a formed in the gate insulating film 2 and the insulating film 4, and the conductive layer 6b is formed in the insulating film 4. Contact hole 5b
Thereby, it is electrically connected to a drain region of the semiconductor layer 1 described below. Further, the data line 6 and the source electrode 6
a, an interlayer insulating film 7 is arranged to cover the conductive layer 6b, and the conductive layer 6b is formed on the interlayer insulating film 7 by ITO (Indium) by a contact hole 8 formed in the interlayer insulating film 7.
It is electrically connected to the pixel electrode 9a made of a Tin Oxide) film. Finally, an alignment film 16 made of polyimide is disposed so as to cover the pixel electrode 9a. Here, the semiconductor layer 1 of the TFT in the image display region is lightly doped (LDD).
drain) structure, details of which will be described later.

In the peripheral drive circuit area of the TFT array substrate 10, a complementary transistor structure is employed. As shown in FIG. 3, the complementary transistor structure includes an N-channel TFT 130a and a P-channel TFT
An N-channel type semiconductor layer 1 and a P-channel type semiconductor layer 1 are provided on an underlayer 12 provided on a glass substrate 60 and a gate insulating film 2 is provided so as to cover these. Have been. A gate electrode 103 is disposed on the gate insulating film 2 at a position corresponding to a channel region of the semiconductor layer. Further, the insulating film 4 is disposed so as to cover the gate electrode 103, and the source electrodes 106a and 107a and the drain electrodes 106b and 107b disposed on the insulating film 4.
Are electrically connected to the corresponding source region or drain region of the semiconductor layer 1, respectively. Then, an interlayer insulating film 7 is disposed on the TFT having the complementary transistor structure. The semiconductor layer of the N-channel TFT has an LDD structure.

On the other hand, the opposing substrate 80 is composed of a light-shielding film 23 formed in a matrix on the glass substrate 20, an opposing electrode 21 made of an ITO film sequentially formed so as to cover the same, and an alignment film 16 made of polyimide. Have been.

Next, a method of manufacturing a TFT array substrate will be described with reference to FIGS. 4 to 12 are cross sections in the image display area and the peripheral circuit area, and the image display area is a cross section taken along line AA ′ in FIG.

First, as shown in FIG. 4A, a SiO ₂ film is formed on a glass substrate 60 as a base film 12 by a PE (plasma enhanced) CVD method or an ECR (electron cyclotron resonance) CVD method. 500
It is formed with a thickness of about nm. This base film is formed by removing impurities such as dirt on the surface of the glass substrate 60 and impurities contained in the glass substrate.
It has a function of preventing the characteristics of the FT 30 from deteriorating.

Next, as shown in FIG.
An a-Si film 401a is laminated on the underlying film to a thickness of about 30 to 100 nm by the D method or the LP (low pressure) CVD method.

Next, as shown in FIG.
Excimer laser light such as KrF or XeCl
Irradiation of 100 to 600 mJ / cm ² results in a-S
The i-film is crystallized to obtain a p-Si film 401b. The irradiation intensity, irradiation time, and the like of the excimer laser light are appropriately adjusted depending on the thickness, film quality, and the like of the a-Si film. In the present embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is less expensive than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 4D, a resist film 402 is formed in a shape corresponding to the semiconductor layer of each TFT in the image display area and the peripheral drive circuit area.

Next, as shown in FIG. 5A, using the resist film 402 as a mask, the p-Si film 401b is subjected to RIE (reactive ion etching) using a chlorine-based gas.
The p-Si layer 1 is formed by etching. In addition to the dry etching such as RIE, wet etching using a chemical such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 5B, after the resist film 402 is peeled off, as shown in FIG.
TEOS (tetraethyl orthosilicate) by the method
A mixed gas of oxygen and oxygen gas as a raw material gas;
A gate insulating film 2 having a thickness of 0 nm is formed. Here, SiH ₄ and oxygen gas may be used as the source gas.

Next, as shown in FIG. 5D, a resist film 403 having a shape in which a portion corresponding to a region functioning as a capacitor in the semiconductor layer 1 in the image display region is removed is formed. Then, using this resist film 403 as a mask, phosphorus ions as impurities are 5 × 10 5 by ion implantation.
Semiconductor layer 1 at a dose of ¹⁴ to 10 ¹⁶ / cm ^2.
To form a capacitor electrode 1f. After the implantation, the resist film 403 is peeled off.

Next, as shown in FIG. 6A, a PVD (physical vapor deposition) is formed on the gate insulating film 2.
By a method, an aluminum film 405a of 400 nm and a titanium film 405b of 100 nm are further formed.

Next, as shown in FIG.
A resist film 404 having a shape corresponding to a gate electrode and a capacitance line
To form Using this as a mask, as shown in FIG. 6C, the aluminum film 405a and the titanium film 405b are etched by RIE using a fluorine-based or chlorine-based gas. After the etching, the resist film 404 is peeled off, and as shown in FIG. 6D, the scanning line 3, the gate electrodes 3a and 103, and the capacitance line having a multilayer film including a lower layer made of aluminum and an upper layer made of titanium. 3b is obtained.

Next, as shown in FIG. 7A, the P-channel type T of the peripheral circuit area covers the entire image display area.
A resist film 405 is formed in which the resist is removed only at a position corresponding to the semiconductor layer to be the FT. This resist film is made of a novolak resin, and after applying a resist on a substrate by a spin coating method, the resist is exposed to light and TMAH
It is formed by developing with an aqueous solution. Here, since the resist film 405 is formed so as to cover the image display area, the scanning lines, the capacitance lines, and the gate electrodes in the image display area are not etched by the developing solution. Thereafter, using the resist film 405 and the gate electrode 103 corresponding to the P-channel type TFT as a mask, a 5 ×
10 ¹⁴ to 10 ¹⁶ boron ions / cm ² are implanted by an ion implantation method, and a channel region 1 a self-aligned with the gate electrode 103, a source / drain region 1 g,
The semiconductor layer 1 having 1h is obtained.

Next, as shown in FIG. 7B, the resist film 405 is peeled off by a peeling solution.

Thereafter, as shown in FIG. 7C and FIG. 13, a resist film 406 is formed. Here, FIG.
FIG. 4 is a plan view showing a formation position of a resist film 406 in an image display area, in which the resist film 406 is indicated by a thick line descending to the right.

As shown in FIG. 7D, the resist film 40
6 is formed in a shape corresponding to the semiconductor layer to be the P-channel TFT 130a in the peripheral circuit region. On the other hand, as shown in FIG. 13, the resist film 406 in the image display region covers the capacitance line 3b corresponding to the region where the capacitance line 3b and the data line 6 to be formed later overlap, and The scanning line 3 is formed so as to cover the scanning line 3 corresponding to the area where the data line 6 overlaps. Here, the resist film 406 is not formed in a region where the semiconductor layer 1 and the scanning line 3 overlap, that is, a region serving as a channel region of the semiconductor layer. The resist film 406 may be formed at a position corresponding to the electrode 3a. Further, in the present embodiment, the semiconductor layer as a capacitor electrode corresponding to the region where the data line 6 and the projection of the capacitor line 3b overlap with each other is completely covered with the projection of the capacitor line 3b in plan view. Has become. For this reason, impurity ions are implanted into the semiconductor layer portion as the capacitor electrode before the capacitor line 3b is formed (FIG. 5D). Therefore, impurity ions are not implanted into the semiconductor layer portion as the capacitor electrode in the step after the formation of the capacitor line, so that even if the semiconductor layer is arranged as shown in FIG. The resist film 406 can be disposed so as to cover the capacitance line in a region where the capacitance line 6 and the capacitance line 3b overlap. The resist film 406 is made of a novolak-based resin, and a resist is applied on a substrate by a spin coating method, and the resist is exposed to TMA.
It is formed by developing with an H aqueous solution. In the present embodiment, at the time of development during the formation of the resist film, a part of the scanning line 3 and the capacitor line 3b can be protected from the developing solution by the resist film 406. There is no etching.

Next, using the resist film 406, the gate electrode 3a, the gate electrode 103 corresponding to the N-channel type TFT 130a, and the capacitor line 3b as a mask, the semiconductor layer 1 is formed on the semiconductor layer 1 at 1 × 10 ¹³ to 2 × 10 ¹⁴ / cm 3. ^Two phosphorus ions are implanted by an ion implantation method. Thus, in the peripheral circuit region, the channel region 1a self-aligned with the gate electrode 103, the high-concentration source region 1d formed later, the low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region 1e, The semiconductor layer 1 corresponding to the N-channel TFT having the drain region 1c is obtained. Further, in the image display region, two channel regions 1a (only one is shown) are formed so as to sandwich the two channel regions, and the impurity concentration is higher than that of the high-concentration source region 1d and the high-concentration drain region 1e formed later. A semiconductor 1 having a low concentration, a low concentration source region 1b and a low concentration drain region 1c is obtained. Next, the resist film 406 is stripped with a stripping solution.

Thereafter, as shown in FIGS. 8A and 14, a resist film 407 is formed. FIG. 14 is a plan view showing a portion where the resist film 407 is formed in the image display area. In the drawing, the resist film 407 is indicated by a thick line falling to the right.

As shown in FIG. 8A, the resist film 40
7 is an N-channel TFT 130a in the peripheral drive circuit area
Of the gate electrode 103 and the gate electrode 3a in the image display area
And a P-channel type TFT 1
It has a shape that covers the semiconductor layer 30b. FIG.
As shown in FIG. 4, the resist film 407 covers the capacitance line 3b corresponding to the region where the capacitance line 3b and the data line 6 to be formed later overlap, and the region where the scanning line 3 and the data line 6 to be formed later overlap. Are formed so as to cover the scanning lines 3 corresponding to. The resist film 407 is made of a novolak resin, and is formed by applying a resist on a substrate by a spin coating method, exposing the resist to light, and developing the resist with an aqueous solution of TMAH. In the present embodiment, during this development, a part of the scanning line 3 and the capacitor line 3b can be protected from the developing solution by the resist film 407, so that the scanning line 3 and the capacitor line 3b are etched. There is no.

Next, as shown in FIG. 8A, using the resist film 407 as a mask, 5 × 10 ¹⁴ to 1 × 10
0 ¹⁶ phosphorus ions / cm ² are implanted by an ion implantation method. After that, the resist film 407 is peeled off by a peeling liquid. As a result, as shown in FIG. 8B, the TFTs in the image display area and the N-channel type TFs in the peripheral drive circuit area are formed.
T is a lightly doped source region 1b and a lightly doped drain region 1c
And a high-concentration source region 1 having an impurity concentration higher than these.
d, a semiconductor layer having an LDD structure having the high-concentration drain region 1e can be obtained.

Next, as shown in FIG. 8C, PECVD is performed so as to cover the gate electrodes 103 and 3a and the capacitance line 3b.
An insulating film 4 made of SiO _{2 having} a thickness of 500 nm is formed by a method using TEOS and ozone gas as source gases. Thereafter, to activate impurity ions, 4
An activation heat treatment (activation annealing treatment) is performed at a temperature of 00 ° C. Here, the scanning line and the capacitance line at the intersection of the data line, the scanning line, and the capacitance line, which are formed later, are not etched by the developer used for forming the resist film in the previous process. The cross section of the capacitance line does not become overhanging, and no crack occurs in the insulating film.

Next, as shown in FIG. 8D, a contact hole for connecting the source / drain region of each TFT in the peripheral circuit region to a source / drain formed later, and a TFT in the image display region. Resist film patterned into a shape corresponding to a contact hole for connecting a source region of the TFT and a source formed later, and a contact hole for connecting a drain region of a TFT in an image display region and a drain formed later. 409 are formed.

As shown in FIG. 9A, the resist film 40
Using the mask 9 as a mask, the insulating film 4 is etched to form contact holes 5, 5a, 5b. After that, the resist film 409 is peeled off to obtain the structure of FIG.

Next, as shown in FIG.
An aluminum-titanium multilayer film 410 having a thickness of 300 to 1000 nm is formed thereon by a PVD method. Further, as shown in FIG. 9D, a resist film 411 is formed on the aluminum / titanium multilayer film 410 in such a manner that portions corresponding to data lines, sources, and drains are removed.

Next, as shown in FIG. 10A, using the resist film 411 as a mask, the aluminum / titanium multilayer film 410 is etched by RIE using a chlorine-based gas, and then the resist film 411 is peeled off. As a result, as shown in FIG. 10B, in the peripheral circuit region, the sources electrically connected to the source regions 1d and 1g and the drain regions 1e and 1h of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively. The electrodes 106a and 107a and the drain electrodes 106b and 107b are obtained. In the image display area, a data line 6 serving also as a source 6a and a conductive layer 6b electrically connected to the source region 1d and the drain region 1e of the semiconductor layer are obtained. Here, since no crack occurs in the insulating film 4, the data line and the scanning line or the capacitor line do not short-circuit through the crack, and there is no disconnection of the data line due to the crack.

Next, as shown in FIG.
An insulating film 7 covering the drain and the data line is formed by a PECVD method using a mixed gas of TEOS and oxygen gas as a source gas. Here, as a method of forming the interlayer insulating film 7,
An atmospheric pressure CVD method may be used, and as a source gas,
A mixed gas of TEOS and ozone gas, or a mixed gas of SiH ₄ and oxygen gas may be used. Further, not only an inorganic film but also an organic film such as an acrylic film can be used. In this case, a film having a larger thickness can be easily obtained as compared with the inorganic film, and thus can be used as a flattening film.

Next, as shown in FIG. 10D, a resist film 413 in which a resist corresponding to a contact hole connecting the conductive layer 6b and a pixel electrode to be formed later is removed is formed on the interlayer insulating film 7. To form Then, FIG.
As shown in (a), the resist film 413 is used as a mask to etch the interlayer insulating film 7 by RIE or wet etching, and the resist film 413 is peeled off.
As shown in FIG. 11B, an interlayer insulating film 7 having a contact hole 8 is obtained.

Next, as shown in FIG. 11C, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by a sputtering method. Then, FIG.
(A), a resist film 415 corresponding to the pixel electrode shapes on the ITO film 414 is formed, an ITO film 414 as a mask, or wet etching in aqua regia or HBr, or CH ₄ or By performing dry etching by RIE using a gas such as HI, a pixel electrode 9a is obtained as shown in FIG.

As described above, in this embodiment, simultaneously with the formation of the resist film as a mask for ion implantation,
By forming a resist film so as to cover the scanning line or the capacitance line in an area where the scanning line or the capacitance line and the data line overlap, a short circuit between the scanning line or the capacitance line and the data line, and a disconnection of the data line can be prevented. Since this can be prevented beforehand, it is possible to obtain a liquid crystal device having good display characteristics without display variation in a plane.

In this embodiment, the scanning line layer has a multilayer structure in which the lower layer is made of aluminum and the upper layer is made of titanium, whereby generation of hillocks can be prevented, and short-circuiting between the scanning line layer and the data line layer due to hillocks can be prevented. Can be prevented. Further, in the present embodiment, cracks in the insulating film due to the overhang shape, which is a problem in such a multilayer structure, can be prevented.

In the above embodiment, a multilayer film of aluminum and titanium was used for the scanning line. However, instead of aluminum, an aluminum alloy such as an Al—Nd alloy or an Al—Si alloy, or molybdenum instead of titanium was used. Alternatively, a layer containing a high melting point metal such as an alloy thereof for preventing generation of hillocks can be used. Alternatively, a multilayer film in which a layer containing aluminum is an upper layer, or a single-layer film made of aluminum or an alloy thereof can be used as a scan line.

In the above-described embodiment, the resist films 406 and 407 are formed so as to cover the scanning lines and the capacitance lines corresponding to the intersections between the data lines and the scanning lines and the intersections between the data lines and the capacitance lines. However, a resist film may be formed so as to cover each of the scanning line and the capacitor line.
Accordingly, since the scanning line and the capacitance line are not etched by the developing solution, the wiring width is not reduced, and a uniform wiring width can be obtained in a screen, and the liquid crystal device has good display characteristics without display variation. Can be obtained.

However, even in this case, a resist film cannot be formed on the semiconductor layer in the region where the ion is implanted.

Although the above embodiment has been described using a liquid crystal device, the present invention is not limited to this, and the present invention can be applied to a semiconductor device or various electro-optical devices such as electroluminescence.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image forming area in a liquid crystal device according to an embodiment.

FIG. 2 is a plan view of a TFT array substrate on which data lines, scanning lines, and pixel electrodes are formed in an image display area of the liquid crystal device according to the embodiment.

FIG. 3 is a longitudinal sectional view of a peripheral circuit region and an image display region of the liquid crystal device of the embodiment, and the longitudinal sectional view of the image display region is a sectional view taken along line AA ′ of FIG. .

FIG. 4 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 5 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 6 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 8 is a process diagram (part 5) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 9 is a process diagram (part 6) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 10 is a process view (part 7) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 11 is a process view (part 8) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 12 is a process view (part 9) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 13 is a plan view showing the shape of a resist film 406 in an image display area in the step of FIG. 7D.

FIG. 14 is a plan view showing the shape of a resist film 407 in an image display area in the step of FIG. 8A.

FIG. 15 is a partially enlarged view of a thin film transistor for describing a problem in a conventional liquid crystal device manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor layer 2 ... Gate insulating film 3 ... Scanning line 3a ... Gate electrode 4 ... Insulating film 6 ... Data line 6a ... Source electrode 9a ... Pixel electrode 60 ... Substrate 406, 407 ... Resist film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA29 GA34 JA24 JA34 JA37 JA46 JB22 JB31 JB67 KA04 KA10 MA10 MA15 MA27 NA01 NA13 PA02 5F033 GG04 HH08 HH09 HH10 HH18 HH20 HH38 JJ01 JJ08 JJ10 KK10 KK10 KK10 KK10 KK20 MM05 PP14 PP15 QQ08 QQ09 QQ13 QQ19 QQ59 QQ65 QQ73 QQ83 RR04 RR21 SS12 SS15 XX16 XX17 XX31 5F110 AA30 BB02 DD02 DD13 DD24 EE03 EE04 EE14 EE42 FF02 FF30 GG02 J03 H23 GG13 GG13 GG23 GG13

Claims (18)

[Claims] 1. A method of manufacturing a semiconductor device having a region where a first wiring and a second wiring intersect, wherein: a step of forming a semiconductor layer; a step of forming the first wiring; and a step of forming the first wiring Forming a resist film on a predetermined area of the semiconductor device; implanting impurity ions into the semiconductor layer using the resist film as a mask; intersecting the first wiring on a predetermined area of the first wiring Forming the second wiring as described above. 2. A method of manufacturing a semiconductor device having a region where a first wiring and a second wiring intersect, wherein: a step of forming a semiconductor layer; a step of forming the first wiring; and a step of forming the first wiring Forming a resist film on a predetermined region of the semiconductor layer and a predetermined region of the semiconductor layer; implanting impurity ions into the semiconductor layer using the resist film as a mask; and forming a predetermined region on the first wiring Forming the second wiring so as to intersect the first wiring on the semiconductor device. 3. The step of forming the resist film includes a step of applying a resist on the substrate, and a step of forming the resist film by exposing and developing the resist. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The method according to claim 1, wherein the first wiring includes aluminum. 5. The method according to claim 4, wherein the first wiring has a multilayer structure including a lower layer containing aluminum and an upper layer containing a high melting point metal. 6. The method according to claim 5, wherein the upper layer comprises a layer containing molybdenum or titanium. 7. An electro-optical device having a plurality of scanning lines, a plurality of data lines, a transistor connected to the scanning lines and the data lines, and having a region where the scanning lines intersect with the data lines. A method of manufacturing a device, comprising: forming the scanning line; forming a resist film on a predetermined region of the scanning line; and using the resist film as a mask, forming impurities on a semiconductor layer forming the transistor. A method of manufacturing an electro-optical device, comprising: a step of implanting ions; and a step of forming the data line on a predetermined region of the scanning line so as to intersect the scanning line. 8. The method according to claim 1, wherein the step of forming the resist film and the step of implanting the impurity are performed at least twice each, and each of the resist films covers a region where the scanning line and the data line intersect. The method for manufacturing an electro-optical device according to claim 7, wherein 9. A plurality of scanning lines, a plurality of data lines, a transistor connected to the scanning lines and the data lines,
A method for manufacturing an electro-optical device having a region where the scanning line and the data line intersect, comprising: forming a first semiconductor layer and a second semiconductor layer on a substrate; and the first and second semiconductor layers. Forming a gate insulating film on the substrate so as to cover the first semiconductor layer; a scan line having a first gate electrode on the gate insulating film at a position corresponding to at least a channel region of the first semiconductor layer; Forming a second gate electrode on at least a position of the gate insulating film opposite to the channel region; and covering a region where the scanning line and the data line intersect, and corresponding to the first semiconductor layer. Forming a first resist film; implanting impurity ions into the second semiconductor layer using the first resist film and the second gate electrode as a mask; intersecting the scan line with the data line; Forming a second resist film corresponding to the second semiconductor layer, and implanting impurity ions into the first semiconductor layer using the second resist film and the first gate electrode as a mask. Forming an insulating film so as to cover the gate electrode and the scanning line; and forming a plurality of data lines on the insulating film so as to intersect the scanning line. A method for manufacturing an electro-optical device. 10. The electro-optical device includes an image display area and a drive circuit area for controlling display in the image display area, wherein the drive circuit area has the first semiconductor layer and the second semiconductor layer. The method according to claim 8, wherein a thin film transistor having a transistor structure is disposed, and the first semiconductor layer is disposed in the image display region. 11. A step of forming a capacitance line in the same layer as the scanning line and substantially parallel to the scanning line, wherein a region where the capacitance line intersects with the data line is covered with the resist film. The method of manufacturing an electro-optical device according to claim 6, wherein the method is performed. 12. The scanning line according to claim 6, wherein at least a part of the scanning line and a layer formed of the same layer as the scanning line are covered with the resist film. Of manufacturing an electro-optical device. 13. The method of forming a resist film, comprising: applying a resist on the substrate; and exposing and developing the resist to form the resist film. The method for manufacturing an electro-optical device according to claim 6, wherein: 14. The scanning line and a layer formed of the same layer as the scanning line contains aluminum.
A method for manufacturing an electro-optical device according to any one of claims 1 to 13. 15. The scanning line and a layer composed of the same layer as the scanning line have a multilayer structure including a lower layer containing aluminum and an upper layer containing a high melting point metal.
3. The method for manufacturing an electro-optical device according to claim 1. 16. The method according to claim 15, wherein the upper layer comprises a layer containing molybdenum or titanium. 17. A semiconductor device manufactured by the manufacturing method according to claim 1. Description: 18. An electro-optical device manufactured by the manufacturing method according to claim 7. Description: