JP2001034231A - EL display device - Google Patents

Abstract

(57) Abstract: Provided is an EL display device in which a pixel that should not emit light does not emit light due to light emission of an adjacent pixel. SOLUTION: The display device of the present invention has a display pixel forming layer in which a plurality of unit display pixels each having at least a pixel electrode (34), a light emitting film (32), and a cathode (33) are two-dimensionally arranged. (3)
And supplying a power (VH) at a light emission level to the pixel electrode selected from the plurality of unit display pixels (Sn) and supplying the power to the pixel electrode not selected from the plurality of unit display pixels (Sn-1). A switch circuit that supplies power (VL) at a non-light emitting level
(S) is provided. Thus, the potential of the pixel electrode of the non-selected display pixel is clamped to the non-light emitting level, thereby preventing light emission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EL (electro lumines
cence) The present invention relates to an improvement in a display device, and particularly to an EL display device in which light emission of a non-selected pixel due to a current leak is prevented.

[0002]

2. Description of the Related Art The structure of an EL display device will be described with reference to FIG. FIG. 1 is an explanatory view schematically illustrating an EL device by a cross-sectional view, and is roughly divided into a substrate 1, an integrated circuit layer 2 on which a circuit for controlling light emission of pixels is formed, and EL light-emitting pixels arranged in a matrix. The display pixel forming layer 3 is formed.

[0003] The substrate 1 is a transparent glass substrate that transmits light of the light emitting layer. The integrated circuit formation layer 2 integrates a selection circuit and the like composed of a group of switch circuits S for lighting each pixel at a specified arrangement position (address). The display pixel formation layer 3 is formed by patterning an ITO film on the integrated circuit formation layer 2, a plurality of transparent pixel electrodes (anodes) 34 arranged in a matrix, and the pixel electrode 34 and the integrated circuit formation layer. And a light emitting layer 32 formed by depositing an organic EL on the hole transport layer 31.
And a cathode 33 formed on the light emitting layer 32.

[0004] In such a configuration, the output of the decoder (not shown), for example, closing the switch circuit S _n of the selection circuit. Thereby, the power source E is applied to the pixel electrode 34, current I _a flows toward the cathode 33 from the pixel electrode 34. The organic EL light emitting layer 32 between the pixel electrode 34 and the cathode 33 emits light. The light generated in the light emitting layer 32 passes through the transparent pixel electrode 34, the integrated circuit forming layer 2, and the glass substrate 1 and is emitted to the outside. Also, the switch circuit S _{n + 1} that does not close
The voltage required for light emission is not applied between the pixel electrode 34 and the cathode 32 to which is connected, and the light emitting layer 32 sandwiched between them does not emit light. In this way, a two-dimensional image is formed by individually controlling the light emission of each pixel arranged in a matrix.

[0005]

However, in the EL display device having the above structure, the light emitting layer 32 is not formed as an independent region for each pixel. Emitting layer 32 has a high resistance, since the hole transport layer 31 is a low resistance, flows to the adjacent pixels a part of the drive current I _a of the light emitting pixel is off as leakage current i _0. As a result, the potential of some of the pixel electrodes 34 is increased, and there is a problem that (weak) light emission is generated from a pixel portion that should not emit light (off). This causes a decrease in contrast and blurring of the outline.

Accordingly, it is an object of the present invention to provide an EL display device in which a pixel which should not emit light does not emit light due to light emission of an adjacent pixel.

[0007]

In order to achieve the above object, an EL display device according to the present invention has a display in which a plurality of unit display pixels each having at least a pixel electrode, a light-emitting film, and a cathode are stacked two-dimensionally. A pixel formation layer, a pixel selection circuit that supplies power of a light emission level to a pixel electrode of a selected one of the plurality of unit display pixels, and a non-light emission level of a pixel electrode of a non-selected one of the plurality of unit display pixels. A light emission suppression circuit for supplying power.

The EL display device of the present invention further comprises a display pixel forming layer in which a plurality of unit display pixels each having at least a pixel electrode, an EL light emitting film, and a cathode are stacked two-dimensionally.
A pixel selection circuit for supplying power of a light emission level to a pixel electrode of a selected one of the plurality of unit display pixels, and light emission for supplying power of a non-light emission level to a pixel electrode of a non-selected one of the plurality of unit display pixels And an integrated circuit layer on which the suppression circuit is formed.

With this configuration, the potential of the pixel electrode (anode) of the pixel that does not emit light (off) is forcibly clamped to the non-emission level, and the potential of the pixel electrode is prevented from floating, thereby preventing the non-selected pixel from being turned off. To prevent light emission.

Further, even when a hole transport layer having a lower resistance is formed between the EL light emitting film and the pixel electrode, the current flowing through the hole transport layer is controlled by controlling the potential of the pixel electrode. It becomes possible.

[0011] Preferably, the integrated circuit layer includes a switching element constituted by a TFT.

Preferably, the pixel selection circuit and the light emission suppression circuit are formed by complementary TFT circuits. Thus, it is possible to reduce the number of elements and the number of wirings and to improve the aperture efficiency.

Preferably, the integrated circuit layer includes a bus line for applying a first potential (for example, a high potential) for supplying power of a light emission level to the pixel electrode, and a power supply of a non-light emission level for the pixel electrode. Second potential (eg, low potential)
And an application bus wiring. This ensures application of the predetermined potential. In addition, it is possible to individually optimize the applied potential according to the TFT characteristics and the organic EL characteristics.

Preferably, each of the unit display pixels includes:
A plurality of scanning lines extending in one direction in parallel with each other, a plurality of data lines orthogonal to an extending direction of each scanning line, and a plurality of regions defined by the plurality of scanning lines and the plurality of data lines Inside, the display information is updated for each row arranged in a matrix, and as the second potential application bus wiring,
A data line to which the unit display pixel column of the previous row is connected is used.

In this manner, in the EL display for performing the line scanning type display, since the control signal of the scanning lines other than the selected scanning line is at the non-light emitting (light-out) level, the scanning line is located before the selected scanning line. Alternatively, it is possible to use a scanning line in a later row as a clamp potential. As a result, the number of bus lines can be reduced and the area of the pixel electrode can be increased, so that the aperture efficiency is improved. The yield can be expected to improve due to the decrease in wiring.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram illustrating an embodiment of the present invention.

In FIG. 1, the EL display device includes a substrate 1, an integrated circuit layer 2 on which a circuit for controlling light emission of pixels is formed, and a display pixel forming layer 3 formed by two-dimensionally arranging EL light emitting pixels in a matrix. Be composed. The substrate 1 is a transparent glass substrate that transmits light of the light emitting layer. Further, the integrated circuit forming layer 2 integrates a selection circuit including a group of switch circuits S for lighting each pixel at a specified arrangement position (address). The display pixel forming layer 3 is formed by patterning an ITO film on the integrated circuit forming layer 2 and a plurality of transparent pixel electrodes (anodes) 34 arranged in a matrix. A hole transport layer 31 deposited on the formation layer, and the hole transport layer 31
The light emitting layer 32 is formed by depositing an organic EL thereon, and further includes a cathode 33 formed on the light emitting layer 32. In this way, one pixel of the display pixel forming layer 3 formed by lamination corresponds to a unit display pixel.

An integrated circuit for controlling the light emission of the display pixels.
Switch circuit S for operating each display pixel of the road forming layer 2
Are normally open contacts that relay signals when activated, and
Switches that generate complementary outputs of normally closed contacts that relay signals
It is a switch circuit. Normally open contact of each complementary switch circuit
On the side, there is enough power to activate the light emitting layer from the power supply circuit
For example, the high voltage V_HIs supplied. Always
On the closed contact side, deactivate the light emitting layer from the power supply circuit
As a sufficient potential, for example, a low voltage V_LIs supplied.
A pixel to emit light is selected by a decoder (not shown).
Control the corresponding one or more complementary switch circuits.
A control signal is supplied. The complementary switch to which the control signal is supplied
Switch switches the output to the normally open contact side and activates the light emitting layer
High voltage V_HIs supplied to the pixel electrode. It
Thus, the selected display pixel emits light. Also selected
For pixels that do not, the complementary switch circuit
Low voltage V to maintain bell relay and deactivate light emitting layer
_LIs supplied to the pixel electrode. Therefore, unselected tables
The potential (or voltage) of the pixel electrode of the indicated pixel is forced to V
_LThe floating state of the potential of the pixel electrode is avoided.
Thereby, the gas flows through the hole transport layer 3 having a relatively low resistance.
Current can be controlled. In addition, current leakage from the pixel electrode
Light emission due to arcs is suppressed. Luminescent pixels become non-luminous pixels
As a result, the pixels are placed closer together.
Can be installed, and the pixel density can be increased.
Becomes The normally open contact side circuit of the complementary switch circuit is shown in the unit table.
Equivalent to the selection circuit that makes the indicated pixel emit light, normally closed contact side circuit
Corresponds to a light emission suppression circuit that does not cause the unit display pixels to emit light.
You. If the equivalent function is exhibited, the complementary switch circuit
It is good regardless.

FIG. 2 shows a configuration example of the complementary switch circuit S for one pixel. In the figure, transistors Q _{1 to} Q ₄ are N-type TFTs. A high-potential bus line B _H and a low-potential bus line B _L are arranged in the vertical direction on the left side of FIG. The right vertical, data lines x _n where complementary signals are supplied, / x _n, the scanning lines y _n are arranged on the lower left and right directions. Data line x _n, / x _n, the scanning lines y _n are driven by a decoder (not shown). In the figure, _one of the source / drain regions of the transistor Q1 is connected to the anode (pixel electrode) A of the EL element. The other is connected to the high potential bus line _BH . One of the source and drain regions of the transistor Q ₂ is connected to the anode A of the EL light emitting element. The other is connected to low potential bus line _BL . Between the high potential bus line B _H and the data line x _n mutually the capacitor C ₁ and the transistor Q ₃ for potential holding is connected in series. Connection point of the capacitors C ₁ and the transistor Q ₃ are connected to the gate of the transistor Q _1. Further, between the low-potential bus line B _L and the data line / x _n mutually, capacitor C ₂ and the transistor Q ₄ for the potential holding it is connected in series. Connection point of the capacitors C ₂ and the transistor Q ₄ are connected to the gate of the transistor Q _2. The gates of the transistors Q ₃ and Q ₄ are connected to the scan line y _n.

[0020] In such a configuration, in the case where the light emitting elements EL _n of the selected sequence, the decoder scanning lines y _n in the selected row, thereby turning on the transistor Q _3, Q ₄ "H" level Set to. Also, data lines x _n ,
/ X _n is set to an “H” level for turning on the transistor Q ₁ and an “L” level for turning off the transistor Q ₂ . By scanning lines y _n becomes "H" level, the transistors Q ₃ and Q ₄ are turned together. Thereby, the capacitors C ₁ and C ₂ are charged by the potentials of the data lines x _n and / x _n , respectively, and the corresponding potentials are held until the next scanning (writing). Also, the transistor Q ₁
And each "H" level gates of Q _2, is set to "L" level. Transistor Q ₁ is turned, the electric potential V _H on the high potential bus line B _H is applied to the anode A, and supplies the operating current. Transistor Q ₂ are non-conductive, relay to the anode A of the potential V _L on the low potential bus line B _L is interrupted. The light emitting element EL _n by the high voltage V _H is applied to the pixel electrode from the high potential bus line B _H to the light emitting element EL _n emits light.

On the other hand, the light emitting elements EL of the selected row_nDepart
If the light is not to be emitted, the decoder uses the data line x_n, / X_n
"L" level to make each transistor non-conductive
Set to “H” level to make it conductive. Scan line y_n
Is at "H" level, so that the transistor Q_ThreeAnd Q_FourIs
Both are conducting. Thereby, the potential holding capacitor C
₁And C_TwoAre set to “L” level and “H” level respectively.
Is held until the next scanning (writing). Also, tiger
Transistor Q₁And Q_TwoEach gate of "L" level
Set to “H” level. Transistor Q₁Is unguided
And the high-potential bus line B_HPotential V_HAnode A
The supply of the drive current to is stopped. On the other hand, transistor Q
_TwoIs conductive and the low potential bus line B_LPotential V_LBecomes anode A
Will be relayed. The potential of the anode A is a low potential maintained at a constant potential
Bus line potential V_LIs clamped to. Light emitting element EL_n
Low voltage V_LDoes not emit light when is applied. What
In the above embodiment, each transistor is configured as an N-type transistor.
Can be configured as a P-type.

FIG. 3 shows an integrated circuit pattern of the complementary switch circuit shown in FIG. In the figure, A is E
This is the anode (pixel electrode) of the L light emitting element. Since the reference numerals corresponding to those in FIG. 2 are given to the functional element portions, the description of the configuration is omitted. The connection between the wiring films is made by a contact hole.

FIG. 4 shows an example in which the switch circuit shown in FIG. 2 is composed of complementary TFT transistors using an N-type TFT (Q ₁₁ ) and a P-type TFT (Q ₁₂ ).
By using the complementary TFT, the signal / x _n of the data line, the capacitor C ₂ and the transistor Q shown in FIG.
₄ becomes unnecessary.

[0024] Stated operation of this circuit, when the "H" level signal is applied to the scanning lines y _n, N-type TFT
Transistor Q ₁₃ is conductive. Thereby, the potential holding capacitor C is set according to the signal level of the data line _xn.
11 is charged and held until the next scan. Further, "H" level of the data line x _n is the conduction transistors Q _11, and non-conducting transistor Q _12. The pixel electrode A of the EL light emitting element is clamped at a low level, and light emission is blocked.

On the other hand, the scanning lines y _n is "H" level, the data line x _n is "L" level (or a negative level)
If it is, the non-conductive transistor Q _11, and conducts the transistor Q _12. As a result, the level clamp is released, the high level V _H is applied from the high potential bus line B _H to the pixel electrode A of the EL light emitting element, and the drive current flows to emit light.

FIG. 5 shows an example of a switch circuit which does not require the low potential bus line _BL described in FIG. The other configuration is the same as that of FIG. In this example, when the screen display is updated by the progressive scanning type, the scanning line y _n
Is accessed, scan line y _{n-1 of the} previous row
Is non-access (“L” level). Connect one of the drain-source region of the transistor Q ₁₁ to the scan line y _n-1, connecting the other to the anode A of the light emitting element.

FIG. 6 shows an integrated circuit pattern of the switch circuit of FIG. The same components are denoted by the same reference numerals, and description thereof will be omitted. Compared with the wiring pattern shown in FIG. 3, the number of bus lines is reduced, and the anode (pixel electrode) A of the EL light emitting element is reduced.
Area can be increased. Further, it is possible to increase the pixel density.

According to the above-described embodiment, light emission due to current leakage can be suppressed, so that pixels can be arranged closer to each other, and the density of pixels can be increased. Further, by using the scanning lines of the adjacent pixels as the clamp potential, the number of wirings is reduced, the area of the pixel electrode can be increased, and the aperture efficiency is improved.

The present invention can be applied not only to an organic EL display device but also to a light emitting device using a general organic semiconductor film in the case where current leakage from an adjacent pixel electrode is prevented.

[0030]

As described above, according to the display device of the present invention, the potential of the pixel electrode of the non-display pixel is clamped to a predetermined potential, so that the light emission due to the current leak from the adjacent pixel electrode. Is suppressed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a display device of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a switch circuit.

FIG. 3 is an explanatory diagram illustrating an integrated circuit pattern of the switch circuit illustrated in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of another switch circuit using complementary TFTs.

FIG. 5 is a circuit diagram illustrating a switch circuit example in which a part of the switch circuit in FIG. 4 is modified;

FIG. 6 is an explanatory diagram showing an integrated circuit pattern of the switch circuit shown in FIG. 5;

FIG. 7 is an explanatory diagram for explaining a defect of the EL light emitting display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Integrated circuit formation layer 3 Display pixel formation layer 31 Hole transport layer 32 Light emitting layer 33 Cathode

Claims (8)

[Claims] A display pixel forming layer in which a plurality of unit display pixels each having at least a pixel electrode, a light-emitting film, and a cathode are stacked two-dimensionally; and a pixel of a selected one of the plurality of unit display pixels. A two-dimensional display device, comprising: a pixel selection circuit that supplies power of a light emission level to an electrode; and a light emission suppression circuit that supplies power of a non-light emission level to a pixel electrode of an unselected one of the plurality of unit display pixels. 2. A display pixel forming layer in which a plurality of unit display pixels each having at least a pixel electrode, an EL light emitting film, and a cathode are stacked two-dimensionally, and a display pixel forming layer selected from the plurality of unit display pixels. An integrated circuit layer formed with a pixel selection circuit that supplies power of a light emission level to a pixel electrode, and a light emission suppression circuit that supplies power of a non-light emission level to a pixel electrode of an unselected one of the plurality of unit display pixels; EL display device comprising: 3. The EL display device according to claim 1, wherein the display pixel forming layer further has a low-resistance hole transport layer between the EL light emitting film and the pixel electrode. 4. The E-cell according to claim 2, wherein said integrated circuit layer includes a switching element constituted by a TFT.
L display device. 5. The EL display device according to claim 2, wherein the pixel selection circuit and the light emission suppression circuit are formed by N-type and P-type complementary TFT circuits. 6. The integrated circuit layer includes a first potential applying bus line for supplying a light emitting level power supply to the pixel electrode, and a second potential applying power supply for supplying a non-light emitting level power supply to the pixel electrode. The EL display device according to claim 2, further comprising: a bus wiring. 7. Each of the unit display pixels includes a plurality of scanning lines extending in one direction in parallel with each other, a plurality of data lines orthogonal to an extending direction of each scanning line, and a plurality of scanning lines. In a plurality of regions defined by the plurality of data lines,
7. The EL according to claim 6, wherein display information is updated for each row by being arranged in a matrix, and a data line to which a unit display pixel column of a previous row is connected is used as the second potential application bus line. 8. Display device. 8. The display device according to claim 1, wherein said pixel selection circuit and said light emission suppression circuit are constituted by switch circuits for generating complementary outputs.