JP2001143465A - Dynamic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dynamic random access memory(DRAM), capable of controlling the cycle of self-refresh operation. SOLUTION: When a monitor trigger signal MON is applied from the outside in addition to a self-refresh signal SRF from a timing generator 12, a self-refresh timer circuit 100 generates an internal timing signal TIM in a fixed cycle with a ring oscillation circuit provided therein and outputs a monitor output signal MOT corresponding to the first cycle of this internal timing signal TIM. The monitor output signal MOT is passed through an output circuit 200 and outputted from an output electrode as an output signal OUT for measurement. The ring oscillation circuit inside the self-refresh timer circuit 100 has an inversion amplifier capable of increasing/decreasing delay times by cutting a fuse and in a wafer check process, the cycle of the internal timing signal TIM can be controlled suitably, on the basis of the measured result of the output signal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM"),
In particular, it relates to cycle control of a refresh operation of a DRAM having a self-refresh function.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram of a conventional DRAM having a self-refresh function. This DRAM
Has a row address buffer 1 and a column address buffer 2 to which time-division multiplexed address signals A0 to A9 are applied. The row address buffer 1 holds a row address. A word line of the memory cell array 5 is connected to an output side of the row address buffer 1 via a row decoder 3 and a word driver 4. The memory cell array 5 is a memory cell array in which memory cells that need to be periodically rewritten for holding stored contents are arranged in a matrix. The column address buffer 2 holds a column address, and a column decoder 6 is connected to the output side. The sense amplifier 7 is connected to the output side of the column decoder 6.
, The bit lines of the memory cell array 5 are connected. The sense amplifier 7 reads and writes data stored in the memory cell array 5 corresponding to the bit line selected by the column decoder 6. The input / output selector 8 is connected to the sense amplifier 7.
Are connected to an input data buffer 9 and an output data buffer 10 via an internal data bus. The input data buffer 9 and the output data buffer 10 exchange data signals DQ1 to DQ16 with an external data bus.

This DRAM has a RAS (row address strobe) for identifying a row address and a column address.
Two control signals, a signal and a CAS (column address strobe) signal, are provided. The CAS signal is input / output controller 11 and timing generator 12
The RAS signal is supplied to the timing generator 12. The input / output controller 11 responds to the write enable signal WE and the read enable signal
It controls the input / output selector 8, the input data buffer 9, and the output data buffer 10.

[0004] A timing generator 12 generates a self-refresh signal S for starting a self-refresh operation for maintaining the contents stored in the memory cell array 5 correctly based on the timing conditions of the RAS signal and the CAS signal.
It outputs RF. The self-refresh timer circuit 13 is formed of, for example, a ring oscillation circuit or the like, and generates a timing signal TIM for performing a self-refresh operation when a self-refresh signal SRF is applied. The timing signal TIM is provided to the refresh control clock 14. The refresh control clock 14 generates a refresh clock signal based on the timing signal TIM and the control from the timing generator 12, and supplies the generated clock signal to the internal address controller 15. The internal address controller 15 generates a row address for refresh at the time of the self-refresh operation, and supplies the generated row address for refresh to the row address buffer 1. In such a DRAM, first, RAS
The row address is taken into the row address buffer 1 by the signal, decoded by the row decoder 3, and a specific word line is selected and activated by the word driver 4. Next, the column address is taken into the column address buffer 2 by the CAS signal, decoded by the column decoder 6, and a specific bit line is selected. In this manner, the information of the specific memory cell specified by the address signals A0 to A9 is read by the sense amplifier 7, and the input / output selector 8
Through the output data buffer 10. In the case of writing, the input data buffer 9 is operated by the write enable signal WE, and the data signals DQ1 to DQ16 on the external data bus are specified via the input / output selector 8 by the address signals A0 to A9. Are stored in the memory cells.

On the other hand, when the RAS signal and the CAS signal satisfy predetermined conditions, a self-refresh operation is started.
For example, after the CAS signal is activated, the RAS signal is activated. If the activated state continues for 10 μs, the self-refresh signal S
RF is output. As a result, the self-refresh timer circuit 13 operates, and the timing signal TIM is generated at a period of, for example, 100 μs. In the refresh control clock 14, a clock signal for refresh is generated based on the control of the timing generator 12 and the timing signal TIM.
Given to. In the internal address controller 15, the address counter is counted up by a clock signal provided from the refresh control clock 14, and the count value is output to the row address buffer 1. Thus, the word lines of the memory cell array 5 are sequentially activated, and the refresh operation of the memory cells connected to the activated word lines is performed.

[0006]

However, the conventional DRAM has the following problems. That is, the self-refresh timer circuit 13 uses a ring oscillation circuit or the like to generate the timing signal TIM of a predetermined cycle. The ring oscillation circuit is configured such that an inverting amplification circuit such as an inverter is connected in an odd-numbered stage loop to form a feedback circuit, and oscillates at a cycle based on the loop delay time. The delay time of the inverting amplifier circuit varies greatly depending on the manufacturing process, and generally cannot be adjusted. For this reason, if the cycle of the timing signal TIM is longer than a predetermined time, it is difficult to maintain the memory contents of the memory cell, and the stored contents may be lost. If the cycle is short, the refresh is performed more frequently than necessary. There is a problem that the operation is performed and power consumption increases. An object of the present invention is to solve the problem of the prior art and provide a DRAM capable of adjusting the cycle of a self-refresh operation.

[0007]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a method for storing the contents of a memory cell when an externally applied control signal satisfies a predetermined condition. In a DRAM that generates an internal timing signal at a fixed cycle to perform a refresh operation to maintain the DRAM,
An input electrode for externally applying a start signal for forcibly generating the internal timing signal, and when the control signal satisfies the predetermined condition and when the start signal is applied, Timer means for generating an internal timing signal; output means for generating a monitor output signal corresponding to the first cycle of the internal timing signal generated by the timer means after the start signal is applied; And an output electrode for outputting a signal to the outside.

[0008] According to the first invention, as described above, the DRA
Since M is configured, the following operation is performed. When a start signal is externally applied to the input electrode, an internal timing signal having a fixed period is generated by the timer means, and a refresh operation is performed. On the other hand, after the start signal is applied in the output means, during the first cycle of the internal timing signal,
A monitor output signal is generated and output from the output electrode.
According to a second invention, a ring oscillator is formed by connecting the timer means in the first invention to an odd number of inverting amplifiers including at least one variable delay inverting amplifier capable of adjusting a propagation delay time in a loop, The internal timing signal having a constant period is generated. According to a third invention, the variable delay inverting amplifier according to the second invention is connected in parallel to the delay circuit comprising a capacitor and first, second, and third resistors connected in series, and the first resistor. A first fuse that short-circuits the first resistor, and a fuse circuit that is connected in parallel with the second resistor and that short-circuits the second resistor when the second fuse is blown. It has a configuration. According to the second and third aspects, the following operation is performed by the timer means. An internal timing signal having a cycle corresponding to the ring delay time is generated by a feedback operation of a ring oscillator in which an odd number of inverting amplifiers including a variable delay inverting amplifier are connected in a loop. Therefore, the delay time of the variable delay inverting amplifier is set to, for example, the first or the second.
And the period of the internal timing signal can be adjusted.

[0009]

FIG. 1 is a block diagram of a DRAM having a self-refresh function according to an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by the same reference numerals. This DRAM is provided with timer means (for example, a self-refresh timer circuit) 100 provided with a measurement and adjustment function in place of the self-refresh timer circuit 13 in FIG. 2, and outputs an output signal OUT for measuring a refresh cycle. The output unit (for example, output circuit) 200 is added. This DRAM
Has a row address buffer 1 and a column address buffer 2 to which time-division multiplexed address signals A0 to A9 are applied, similarly to the DRAM of FIG. The row address buffer 1 stores an address signal A0 given as a row address.
.. A9, and a word line of the memory cell array 5 is connected to the output side via a row decoder 3 and a word driver 4. The memory cell array 5 is a memory cell array in which memory cells that need to be rewritten periodically to retain stored contents are arranged in a matrix at intersections of word lines and bit lines. The row decoder 3 decodes a row address, and the word driver 4 drives a word line of the memory cell array 5 corresponding to the decoded row address.

The column address buffer 2 holds address signals A0 to A9 given as column addresses, and a column decoder 6 is connected to the output side. The column decoder 6 decodes a column address. The output side of the column decoder 6 is connected to a bit line of the memory cell array 5 via a sense amplifier 7. The sense amplifier 7 reads and writes data stored in a memory cell corresponding to the bit line selected by the column decoder 6. An input / output selector 8 for switching input / output of data to / from the memory cell array 5 is connected to the sense amplifier 7, and an input data buffer 9 and an output data buffer 10 are connected to the input / output selector 8 via an internal data bus. Have been. Input data buffer 9 and output data buffer 10
Are the data signals DQ1 to DQ1 with the external data bus.
6 is delivered. This DRAM has a RAS for externally identifying a row address and a column address.
Two control signals, a signal and a CAS signal, are provided. The CAS signal is given to the input / output controller 11 and the timing generator 12, and the RAS signal is given to the timing generator 12. The input / output controller 11 controls the input / output selector 8, the input data buffer 9, and the output data buffer 1 according to the write enable signal WE and the read enable signal OE.
0 is controlled. Timing generator 1
Reference numeral 2 denotes a self-refresh signal SRF for starting a self-refresh operation for maintaining the stored contents of the memory cell array 5 correctly based on the timing conditions of the RAS signal and the CAS signal, and supplying the self-refresh signal SRF to the self-refresh timer circuit 100. is there.

The self-refresh timer circuit 100
When the self-refresh signal SRF is applied, a timing signal TIM for performing a self-refresh operation at a predetermined cycle is generated. Further, when an activation signal (for example, a monitor trigger signal) MON is externally supplied to measure the cycle of the timing signal TIM, the self-refresh timer circuit 100 outputs the monitor output signal MO corresponding to the timing signal TIM.
It has a function of outputting T. Timing signal TIM
Is supplied to the refresh control clock 14, and the monitor output signal MOT is supplied to the output circuit 200. The refresh control clock 14 generates a refresh clock signal based on the timing signal TIM and the control from the timing generator 12, and supplies the refresh clock signal to the internal address controller 15. The internal address controller 15 generates a row address for refresh at the time of the self-refresh operation, and supplies the row address for refresh to the row address buffer 1 instead of a row address externally given as address signals A0 to A9. is there. The output circuit 200 corresponds to the cycle of the timing signal TIM based on the monitor trigger signal MON, the monitor output signal MOT, the data output enable signal DOE output from the input / output controller 11, and the data signal DAT on the internal data bus. It generates and outputs an output signal OUT.

FIG. 3 is a circuit diagram showing an example of the self-refresh timer circuit 100 in FIG. The self-refresh timer circuit 100 includes an input electrode 101 for externally applying a monitor trigger signal MON. The input electrode 101 is connected to a first input terminal of a two-input NOR gate (hereinafter, referred to as “NOR”) 110, and a second input terminal of the NOR 110 is supplied with a self-refresh signal SRF. It has become. The output side of the NOR 110 is connected to the oscillator 120 and the frequency divider 1
40, and a reset signal R
ST is provided. The oscillating unit 120
It comprises a two-input NOR 121 to which a reset signal RST is applied to a first input terminal, and a ring oscillation circuit in which an even number of inverting amplifier circuits 130 cascaded to the output side of the NOR 121 are connected in a loop. The output signal of the final-stage inverting amplifier circuit 130 is fed back to the second input terminal of the NOR 121 to generate the oscillation signal OSC, and the oscillation signal OSC is supplied to the frequency divider 140 and the pulse generator 150. It has become.

The frequency divider 140 includes three cascaded flip-flops (hereinafter, referred to as “FFs”) 141 and 14.
2,143. A reset signal RST is commonly applied to reset terminals of the FFs 141 to 143, and an oscillation signal OSC is applied to the first-stage FF 141. Then, 1/8 from the last FF 143
TIM is output. The pulse generation unit 150 is connected to the cascaded 4
Inverters 151, 152, 153, 154 and 2
An input NAND gate (hereinafter, referred to as “NAND”) 155 is provided, and an oscillation signal OSC is provided to an input side of the inverter 151. Inverter 15
1, 154 are connected to the input side of the NAND 155, and when the oscillation signal OSC falls, this NAN
A pulse signal PLS having a pulse width corresponding to the delay time of the inverters 152 to 154 is output from the output side of D155. The output of NAND 155 is F
It is connected to the reset terminal of F160. FF160
Is composed of two NANDs 161 and 162, and a set terminal receives a monitor trigger signal MON. An inverter 170 is connected to the output side of the FF 160, and the monitor output signal M
OT is output.

FIG. 4 is a circuit diagram showing an example of the inverting amplifier circuit 130 in FIG. This inverting amplifier circuit 130 is a P-channel MOS transistor (hereinafter, referred to as “PMOS”) whose conduction state is complementarily controlled by an input signal I.
131 and an N-channel MOS transistor (hereinafter referred to as
132 (referred to as “NMOS”). PMOS1
31 and the source of the NMOS 132 are connected to the power supply potential V, respectively.
It is connected to CC and the ground potential GND, and the drain is connected via resistors 133a, 133b, 133c connected in series. The drain of the NMOS 132 is connected to the power supply potential VCC via the capacitor 134, and the output signal O is output from the drain.
A fuse circuit 135 that short-circuits the resistor 133b by cutting the fuse is connected in parallel to the resistor 133b. The fuse circuit 135 includes the fuse 1
One end of the fuse 135a is connected to the power supply potential VCC, and the other end of the fuse 135a is connected to the NMOS 135b, 1.
35c is connected to the drain. NMOS 135
The sources of b and 135c are connected to the ground potential GND via a common high resistance 135d. NMOS 135b
Is connected to the power supply potential VCC. The other end of the fuse 135a is connected to the gate of the NMOS 135c via the inverter 135e. An inverter 135f is further connected to the output side of the inverter 135e, and a PMOS transistor is connected to the output side of the inverter 135f.
135g, NMOS 135h, and inverter 135i
Is connected. Then, the analog switch PMOS 135g and NMOS 135g
135h is connected in parallel with the resistor 133b. Further, a fuse 136 is connected in parallel to the resistor 133c.

In such an inverting amplifier circuit 130, when the fuse 135a is not blown, the inverter 1
The input signal of the terminal 35e is at the level "H", the output signal is at the level "L", and the analog switches PMOS 135g and NMOS 135h are turned off. As a result, the resistor 133b is in a state of being inserted in series with the resistor 133a. Further, by cutting the fuse 135a, the input signal of the inverter 135e becomes "L" and the output signal becomes "H", and the PMOS 135g and the NMOS 135h of the analog switch are turned on, and the resistor 133b is turned on.
Are shorted. Further, the resistor 133c is short-circuited in a state where the fuse 136 is not blown, and this fuse 136
Is disconnected, the resistor 133c is inserted in series with the resistor 133a. Therefore, the fuses 135a and 136
, The values of the series resistors 133a to 133c can be adjusted, and the series resistors 133a to 133c can be adjusted.
The delay time of the capacitor c and the capacitor 134 can be changed.

FIG. 5 is a circuit diagram showing an example of the output circuit 200 in FIG. The output circuit 200 has a NA to which the monitor trigger signal MON and the monitor output signal MOT are input.
An ND 201 and a NAND 202 to which a data output enable signal DOE and a data signal DAT are input are provided. The output side of NAND 201 and 202 is NAND 203
, And the output side of the NAND 203 is connected to the gate of the PMOS 205 via the inverter 204. The data output enable signal DOE and the data signal DAT inverted by the inverter 206 are connected to the NAND20.
7, the monitor trigger signal MON and the inverter 2
08 is inverted by the NAND 21
0 is input. The output side of the NAND 210 is connected to the gate of the NMOS 211. P
The sources of the MOS 205 and the NMOS 211 are connected to the power supply potential VCC and the ground potential GND, respectively, and the drains of the PMOS 205 and the NMOS 211 are commonly connected to the output electrode 220. And the output electrode 2
20 outputs an output signal OUT.

Next, the operation of such a DRAM will be described by dividing it into an operation (I) for measuring and adjusting the self-refresh cycle, an operation (II) during normal access, and a self-refresh operation (III). (I) Operation at Measurement and Adjustment of Self-Refresh Period This measurement and adjustment of the self-refresh period
This is performed in a wafer check during the manufacturing process of M. FIG. 6 is a signal waveform diagram at the time of measuring the self-refresh cycle in the DRAM of FIG. Hereinafter, referring to FIG.
The operation at the time of measuring and adjusting the self-refresh cycle of the DRAM of FIG. 1 will be described. First, a jig capable of switching and outputting “L” and “H” signals at an arbitrary timing is prepared, and is connected to the input electrode 101 for inputting the monitor trigger signal MON on the wafer. The output circuit 20
A product test memory tester or the like capable of monitoring and measuring the timing and the like of the output signal OUT of 0 is connected to the output electrode 220 for the output signal OUT.

Next, at time t0 in FIG. 6, the required power is turned on to put the DRAM under test into a standby state, and the monitor trigger signal MON is set to "L".
Set to. Thereby, self-refresh signal SR
F and the data output enable signal DOE become “L”,
The data output signal DAT is undefined. Further, the monitor output signal MOT output from the self-refresh timer circuit 100 becomes "L". These signals MON, MO
T, DOE, and DAT are provided to the output circuit 200. In the output circuit 200 of FIG. 5, the signal S204 on the output side of the inverter 204 becomes "H" and the signal S210 on the output side of the NAND 210 becomes "L".
The output side of 0 is in a high impedance (Hi-Z) state. At time t1, when the monitor trigger signal MON rises to “H”, the reset signal RST output from the NOR 110 in FIG. 3 changes from “H” to “L”,
The operation of the oscillating unit 120 starts. Thereby, NOR1
A signal S121 that repeats “H” and “L” at a predetermined cycle is obtained from the output side of S21. The output side of the oscillating unit 120 has an oscillation signal O whose polarity is inverted from that of the signal S121.
SC is output. Further, the oscillation signal OSC is supplied to the frequency divider 14.
The frequency is divided by 1/8 by 0 to generate a timing signal TIM. At this time t1, the state of the FF 160 does not change, and the monitor output signal MOT remains “L”.
On the other hand, in the output circuit 200, the monitor trigger signal MO
When N changes to "H", the signals S204 and S210 both become "H". Thus, the output signal OUT of the output circuit 200 becomes “L”.

At time t2, the oscillation signal OSC becomes "H".
At time t3, the oscillation signal OS
When C falls to “L”, the pulse signal PLS output from the pulse generation unit 150 goes to “L” for a certain time. As a result, the state of the FF 160 changes, and the monitor output signal MOT becomes “H”. On the other hand, in the output circuit 200, when the monitor output signal MOT changes to “H”,
The signals S204 and S210 both become "L". As a result, the output signal OUT of the output circuit 200 becomes “H”.
After that, the output signal OUT is maintained at “H” unless the monitor trigger signal MON is changed.

The period of the oscillation signal OSC can be obtained by measuring the time during which the output signal OUT is "L", that is, the time from time t1 to time t3, using a memory tester or the like. Further, the cycle of the timing signal TIM can be calculated by multiplying the cycle of the oscillation signal OSC by eight. If the calculated period of the timing signal TIM is within a predetermined range, there is no need to adjust the delay time of the inverting amplifier circuit 130. If the timing signal TI
If the period of M is longer than a predetermined range, the inverting amplifier circuit 1
The fuse 135a in 30 is cut. As a result, the resistor 133b is short-circuited, and the delay time of the inverting amplifier circuit 130 is shortened. If the cycle of the timing signal TIM is shorter than the predetermined range, the fuse 136 in the inverting amplifier circuit 130 is cut. As a result, the resistor 133c is connected in series with the resistor 133a, and the delay time becomes longer. As described above, while measuring the time of one cycle of the oscillation signal OSC, the fuse in the inverting amplifier circuit 130 is appropriately cut to adjust the cycle of the timing signal TIM to fall within a predetermined range. The adjusted DRAM chip is cut out from the wafer, housed in a package, and completed as a product.

(II) Normal Access Operation The normal access operation when the completed DRAM is incorporated in a computer or the like is the same as that of a conventional DRAM. That is, first, the row address is taken into the row address buffer 1 by the RAS signal, decoded by the row decoder 3, and a specific word line is selected and activated by the word driver 4. Next, the column address is taken into the column address buffer 2 by the CAS signal, decoded by the column decoder 6, and a specific bit line is selected. In this way, the information of the specific memory cell designated by the address signals A0 to A9 is read by the sense amplifier 7, and is output via the input / output selector 8 to the output data buffer 10.
Sent to In the case of writing, the input data buffer 9 is operated by the write enable signal WE, and the data signals DQ1-DQ16 on the external data bus are operated.
Address signals A0 to A9 via the input / output selector 8.
Is stored in a specific memory cell designated by.

(III) Self-Refresh Operation When the RAS signal and the CAS signal satisfy predetermined conditions, a self-refresh operation is started. For example, after the CAS signal is activated, the RAS signal is activated. If the activated state continues for 10 μs, the timing generator 12 outputs the self-refresh signal SRF,
It is provided to a self-refresh timer circuit 13. As a result, the self-refresh timer circuit 100 operates, and the timing signal TIM is generated at a period of, for example, 100 μs and supplied to the refresh control clock 14. In the refresh control clock 14, a clock signal for refresh is generated based on the control of the timing generator 12 and the timing signal TIM, and is output to the internal address controller 15. In the internal address controller 15, the refresh control clock 14
The internal address counter is counted up by the clock signal supplied from the memory device, and the count value is output to the row address buffer 1. Thus, the word lines of the memory cell array 5 are sequentially activated, and the refresh operation of the memory cells connected to the activated word lines is performed.

As described above, in the DRAM of this embodiment, the cycle of the oscillation signal OSC is adjusted by externally supplying the monitor trigger signal MON for measuring the cycle of the oscillation signal OSC, and by cutting the fuse. And a self-refresh timer circuit 100 including an oscillating unit 120 that can perform the operation. Further, the DRAM has an output circuit 200 for outputting an output signal OUT corresponding to one cycle of the oscillation signal OSC, and an output electrode 220. Thereby, there is an advantage that the cycle of the oscillation signal OSC can be adjusted to an appropriate value.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications (a) to (g). (A) In order to unify the description of the operation, all the elements are configured by positive logic, but negative logic may be used. In an actual DRAM, negative logic is often used for signals such as RAS, CAS, WE, and OE. (B) The timing and the like differ depending on the storage capacity of the DRAM. (C) The configuration of the self-refresh timer circuit 100 is not limited to FIG. For example, the cycle of the oscillation signal OSC may be increased by increasing the total delay time of the oscillation unit 120, and the oscillation signal OSC may be output as the timing signal TIM. As a result, the frequency divider 140 can be omitted. (D) Inverting amplifier circuit 130 that constitutes oscillating section 120
Need not all be capable of adjusting the delay time as shown in FIG. As long as the delay time can be adjusted within a certain range, the delay time of the other inverting amplifier circuits 130 may be fixed. (E) The configuration of the inverting amplifier circuit 130 capable of adjusting the delay time is not limited to the circuit in FIG. For example, a series resistor 133 divided into four or more
The delay time may be adjusted by short-circuiting 33 with a plurality of fuse circuits 135 and fuses 136. (F) The configuration of the output circuit 200 is not limited to the circuit of FIG. For example, FIG. 7 is a circuit diagram of another output circuit 200A.

The output circuit 200A includes an inverter 212 to which the monitor output signal MOT is input, and N to which the output signal of the inverter 212 and the monitor trigger signal are input.
AND213. And this NAND
From 213, an output signal OUT is output. The output circuit 200A has the same function as the output circuit 200, but has a simplified configuration with few components. (G) The output circuit 200 is configured as a separate circuit from the output data buffer 10.
One bit (for example, DQ1) in 0 may be replaced by this output circuit 200. This simplifies the configuration and allows the self-refresh cycle to be measured as a series of tests in the conventional memory test.

[0026]

As described above in detail, according to the first aspect, the timer means for generating the internal timing signal in accordance with the start signal, and the first one of the internal timing signal
Output means for generating a monitor output signal corresponding to the cycle is provided. Further, it has an input electrode for applying a start signal and an output electrode for outputting a monitor output signal to the outside. This makes it possible to easily measure the self-refresh cycle in the wafer check step in the DRAM manufacturing process. According to the second invention, the timer means in the first invention uses at least one variable delay inverting amplifier for the inverting amplifier constituting the ring oscillator. Thus, the cycle of the internal timing signal can be adjusted based on the measurement result of the refresh cycle.
According to the third invention, the variable delay inverting amplifier according to the second invention is a variable delay inverting amplifier for short-circuiting and inserting a resistor of a delay circuit.
And a second fuse. Accordingly, by appropriately cutting the fuse in the wafer check step, it is possible to easily adjust the refresh cycle so as to obtain a predetermined refresh cycle.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DRAM having a self-refresh function according to an embodiment of the present invention.

FIG. 2 shows a conventional DRA having a self-refresh function.
FIG. 2 is a schematic configuration diagram of M.

FIG. 3 is a self-refresh timer circuit 100 shown in FIG. 1;
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 4 is a circuit diagram illustrating an example of an inverting amplifier circuit 130 in FIG. 3;

FIG. 5 is a circuit diagram showing an example of an output circuit 200 in FIG.

FIG. 6 is a signal waveform diagram when a self-refresh cycle is measured in the DRAM of FIG. 1;

FIG. 7 is a circuit diagram of another output circuit 200A.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Self-refresh timer circuit 101 Input electrode 120 Oscillator 130 Inverting amplifier circuit 200 Output circuit 220 Output electrode

Claims (3)

[Claims] 1. A dynamic random access memory for generating a refresh operation by generating an internal timing signal at a constant period to maintain the memory contents of a memory cell when a control signal supplied from the outside satisfies a predetermined condition. An input electrode for externally applying a start signal for forcibly generating the internal timing signal; and the constant when the control signal satisfies the predetermined condition and when the start signal is applied. Timer means for generating an internal timing signal of a cycle; output means for generating a monitor output signal corresponding to the first cycle of the internal timing signal generated by the timer means after the activation signal is applied; An output electrode for outputting a monitor output signal to an external device. Sesumemori. 2. The timer means comprises a ring oscillator formed by connecting an odd number of inverting amplifiers including at least one variable delay inverting amplifier capable of adjusting a propagation delay time to form a ring oscillator. 2. The dynamic random access memory according to claim 1, wherein a timing signal is generated. 3. The variable delay inverting amplifier includes: a delay circuit including a capacitor and first, second and third resistors connected in series; and a first delay circuit connected in parallel to the first resistor. A first fuse that short-circuits a resistor; and a fuse circuit that is connected in parallel to the second resistor and that short-circuits the second resistor when the second fuse is cut. The dynamic memory according to claim 2,
Random access memory.