JP2001144590A - Clock duty detection and correction circuit - Google Patents

Abstract

(57) Abstract: The present invention aims to automatically detect a change in the duty of a clock, correct the change, and accurately receive even when a change or distortion occurs in the clock waveform. An object of the present invention is to provide a duty detection and correction circuit for correcting a clock duty and supplying a good clock to a subsequent circuit. A low-pass filter for smoothing a clock, a sample-and-hold circuit for outputting a voltage obtained by sampling and holding a high-level voltage and a low-level voltage of the clock for each cycle of the clock, and a circuit for outputting a voltage output from the sample-and-hold circuit. A voltage averaging circuit that outputs an average value or a weighted average value, and detects a change in the duty of the clock based on a magnitude relationship between an output voltage of the voltage averaging circuit and an output voltage of the low-pass filter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duty detection and correction technique.

[0002]

2. Description of the Related Art FIG. 13 shows a general clock duty correction circuit. Reference numeral 1 denotes a clock transmitting unit, which includes an oscillator 2 that oscillates a voltage signal having a reference frequency, a variable reference voltage generation circuit 3 that generates a reference voltage to be input to a voltage comparator 4 described later, an output of the oscillator 2 and a variable reference voltage. It comprises a voltage comparator 4 to which a reference voltage output from the generation circuit 3 is input and a buffer 5 to which an output of the voltage comparator 4 is input. Reference numeral 6 denotes a clock receiving unit, which includes a buffer 7 that receives an output of the buffer 5 as an input, and an output terminal 8 that outputs a clock output from the buffer 7 to a subsequent circuit.

A voltage signal having a reference frequency oscillated from an oscillator 2 is supplied to a variable reference voltage generation circuit 3 by a voltage comparator 4.
Is compared with the reference voltage output from the second clock and converted into a binary clock. The clock output from the voltage comparator 4 is output from the clock transmitting unit 1 via the buffer 5.
The clock output from the transmitting unit 1 is received by the clock receiving unit 6 via the buffer 7 and supplied from the output terminal 8 to the subsequent circuit. At this time, the clock supplied to the subsequent circuit includes distortion in the oscillator, voltage offset, the difference between the delay time from high level to low level and the delay time from low level to high level of the signal in the transmission / reception buffer, The duty ratio fluctuates due to the influence of distortion or the like. If the duty of the clock supplied to the subsequent circuit fluctuates beyond the allowable range, the normal operation of the subsequent circuit is affected. Therefore, the clock output from the buffer 7 in the clock receiving unit 6 is observed with an oscilloscope or the like. By adjusting the reference voltage output from the variable reference voltage generation circuit 3, the duty ratio of the clock is corrected. This is shown in FIG. As shown in FIG. 14, by adjusting the magnitude of the reference voltage, the duty of the clock output from the voltage comparator 4 is adjusted.

[0004]

In the clock duty correction circuit as described above, the received clock output from the buffer provided in the clock receiving unit 6 is observed with an oscilloscope, and the duty of the received clock becomes a predetermined value. As described above, the reference voltage output from the variable reference voltage generation circuit 3 must be adjusted, and there is a problem that the adjustment operation requires a large number of steps. Even if the duty of the clock is adjusted in the above-described manner, the influence of the temperature drift of the oscillator and the transmission / reception buffer, the fluctuation of the power supply voltage, the distortion of the signal due to the change of the peripheral conditions of the transmission line and the delay fluctuation, etc. Fluctuates. Further, even if the duty of the clock is adjusted by the method described above, there is a problem that the duty shifts due to aging of the variable reference voltage generating circuit 3 and the like, and the readjustment is required.

As a method of automatically correcting the fluctuation of the duty of the received clock, a difference value of a voltage obtained by smoothing a received clock and an inverted clock obtained by inverting the received clock by a low-pass filter is fed back to a clock transmitting unit. A method of correcting the duty by adjusting the transmission clock so that the difference becomes 0 is introduced in Japanese Patent Laid-Open No. 5-252007. However, in this method, when the high-level or low-level voltage of the reception clock changes due to the fluctuation of the power supply voltage, or when the reception clock waveform is distorted due to the peripheral conditions of the transmission line, the difference fed back to the clock transmission unit is obtained. Since the value also fluctuates, the detection accuracy deteriorates, and the fluctuation of the duty of the reception clock cannot be accurately corrected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to automatically detect a change in the duty of a clock and to correct the change. It is an object of the present invention to provide a duty detection and correction circuit that accurately corrects the duty of a received clock even when such a situation occurs and supplies a good clock to a subsequent circuit.

[0007]

A first clock duty detection circuit according to the present invention comprises a voltage signal oscillated from an oscillator and a reference voltage set between a maximum value and a minimum value of an amplitude voltage of the voltage signal. A clock generation circuit that generates a clock having both a high level and a low level, a low-pass filter that smoothes the clock output from the clock generation circuit, and a high level and a low level of the clock. A sample-and-hold circuit that outputs a voltage obtained by sampling and holding a voltage for each cycle of the clock; and a voltage averaging circuit that outputs an average value or a weighted average value of the voltages output from the sample-and-hold circuit, Based on the magnitude relationship between the output voltage of the circuit and the output voltage of the low-pass filter, the duty of the clock is determined. It is intended to detect the variation of the tee.

A clock duty correction circuit according to the present invention includes a first clock duty detection circuit, compares an output voltage of a voltage averaging circuit with an output voltage of a low-pass filter, and outputs a voltage signal indicating a magnitude relationship between the two voltages. A voltage comparator is provided, and the duty of the clock is corrected by adjusting a reference voltage based on an output of the voltage comparator. Further, the clock duty correction circuit according to the present invention includes a first duty detection circuit, compares the output voltage of the voltage averaging circuit with the output voltage of the low-pass filter, and outputs a voltage signal indicating a magnitude relationship between the two voltages. A counter for changing the count value based on the output of the voltage comparator, and a D / A converter for converting the count value of the counter into a voltage.
The duty of the clock is corrected by adjusting a reference voltage based on an output of the A-converter. In the clock duty correction circuit according to the present invention, the voltage signal indicating the magnitude relationship between the output voltage of the voltage averaging circuit and the output voltage of the low-pass filter output from the voltage comparator is a binary voltage signal.

A second clock duty detection circuit according to the present invention compares a voltage signal oscillated from an oscillator with a reference voltage set between a maximum value and a minimum value of an amplitude voltage of the voltage signal, and outputs the first signal. A clock generation circuit that generates a clock having both the first voltage level and the second voltage level, and a first transition point at which the voltage level of the clock transitions from the first voltage level to the second voltage level And a delay circuit for delaying the clock by providing a delay amount such that a voltage level of the clock transitions from the second voltage level to the first voltage level substantially coincides with the second transition point. Detecting a change in the duty of the clock based on a phase difference between a second transition point of the clock and a first transition point of the clock delayed by the delay amount. .

A clock duty correction circuit according to the present invention includes a second clock duty detection circuit, and a first transition point of the clock output from the clock generation circuit and a second transition of the clock delayed by the delay circuit. A point at which a voltage signal representing the amount of delay or advance of the phase of the first transition point of the clock delayed by the delay circuit with respect to the second transition point of the clock, starting from the point substantially coincident with the point. A phase difference detection circuit is provided, and the duty of the clock is corrected by adjusting a reference voltage based on a voltage signal output from the phase difference detection circuit. The clock duty correction circuit according to the present invention further includes a voltage holding circuit that includes a second clock duty detection circuit and generates and holds a voltage value based on a voltage signal output from the phase difference detection circuit. The duty of the clock is corrected by adjusting the reference voltage based on the output. Also, the clock duty correction circuit according to the present invention includes a second clock duty detection circuit, and a first transition point of the clock output from the clock generation circuit and a second transition point of the clock delayed by the delay circuit. The count value is determined based on whether the phase of the first transition point of the clock delayed by the delay circuit with respect to the second transition point of the clock is a lagging phase or a leading phase, starting from the point where And a D / A converter for converting the count value of the counter into a voltage value.
The duty of the clock is corrected by adjusting the reference voltage based on the output voltage of the / A converter.

In the second clock duty detection circuit according to the present invention, the first voltage level and the second voltage level are respectively a high level voltage and a low level voltage of a clock output from the clock generation circuit, or a high level. Any combination of the voltage and the low level voltage. In the clock duty correction circuit according to the present invention, the voltage signal output from the phase difference detection circuit is a binary voltage signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. Embodiment 1 FIG. FIG. 1 shows a clock duty detection and correction circuit according to a first embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a clock transmitting unit, 2 denotes an oscillator that oscillates a voltage signal of a reference frequency, and 4 denotes a voltage comparison using an output of the oscillator 1 and a reference voltage output from an upper / lower limit circuit 18 described later as an input. Each of the devices 5 and 5 is constituted by a buffer which receives an output of the voltage comparator 4 as an input. Reference numeral 6 denotes a clock receiving unit. Reference numeral 7 denotes a buffer to which the output of the buffer 5 is input. Reference numeral 8 denotes an output terminal for outputting the clock output from the buffer 7 to a subsequent circuit. Reference numeral 9 denotes a delay of the output of the buffer 7. A delay circuit 10 that receives the output of the delay circuit 9 as an input, 11 a first sample and hold circuit that receives the output of the buffer 7 and the non-inverted output of the driver 10, and 12 a output of the buffer 7 and the driver 10. The second sample-hold circuit 13/14 receives the inverted output of the first sample-hold circuit, the resistors 13 and 14 add the resistance of the outputs of the first sample-hold circuit and the second sample-hold circuit, and the low-pass 15 receives the output of the buffer 7 as an input. A filter 16, a voltage comparator that receives the added output of the resistors 13 and 14 and the output of the low-pass filter 15 as inputs, and 17 an integration circuit that receives the output of the voltage comparator 16 as inputs , 18 are upper and lower limit circuits to which the output of the integrating circuit 17 is input.

The voltage signal of the reference frequency oscillated by the oscillator 2 is compared by a voltage comparator 4 with a reference voltage output from an upper / lower limit circuit 18 to be described later, and is converted into a binary clock. The clock output from the voltage comparator 4 is
The clock is output from the transmission unit 1 via the buffer 5. The clock output from the transmitting unit 1 is received by the clock receiving unit 6 via the buffer 7 and supplied from the output terminal 8 to the subsequent circuit. The delay circuit 9 makes the received clock output from the buffer 7 sufficiently longer than the hold setup time in the first sample-hold circuit 11 and the second sample-hold circuit 12 described later and sufficiently shorter than the high-level period or low-level period of the clock. Delay time. The delayed clock output from the delay circuit 9 is input to a driver 10, and the driver 10 outputs an inverted output and a ratio inverted output of the delayed clock, respectively. The first sample and hold circuit 11 and the second sample and hold circuit 12 hold the voltage level of the received clock at the rising timing of the inverted output and the non-inverted output of the delayed clock output from the driver 10, respectively. This is shown in FIG. Accordingly, the high-level voltage and the low-level voltage of the reception clock are output from the first sample-hold circuit and the second sample-hold circuit, respectively.

The high-level and low-level holding voltages of the clocks output from the first sample-hold circuit and the second sample-hold circuit correspond to the resistance 13 and the resistance 1.
4, a voltage obtained by averaging or weighting the two voltages (hereinafter referred to as an average voltage) is applied to the voltage comparator 16
Is input to Here, the weighted average of the high-level voltage and the low-level voltage of the clock is performed based on the duty specified in the subsequent circuit. For example, if the duty of the clock specified by the subsequent circuit is larger than 50%, the resistors 13 and 14 are output so that the weighted average value is output to the high level voltage side if the clock duty is smaller than 50% and to the low level voltage side if the duty is smaller than 50%. adjust. From the low-pass filter 15, a voltage (hereinafter, referred to as a smoothed voltage) obtained by smoothing the reception clock output from the buffer 7 is input to the voltage comparator 16. The voltage comparator 16 compares the average voltage with the smoothed voltage. If the smoothed voltage is higher than the average voltage, that is, if the high-level period of the received clock is longer than a predetermined value, the voltage comparator 16 outputs H.
If the smoothed voltage is lower than the average voltage, that is, if the high level period of the received clock is shorter than a predetermined value, the L level voltage is output.

According to the above operation, when the high level period of the received clock is longer than the predetermined value, the H level voltage is input from the voltage comparator 16 to the integration circuit 17 and the integration circuit 1
The reference voltage output from 7 rises. As a result, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high-level period of the clock is shortened. When the high-level period of the received clock is shorter than the predetermined value, the L-level voltage is input from the voltage comparator 16 to the integration circuit 17, and the reference voltage output from the integration circuit 17 decreases. Thereby, as shown in FIG. 3, the reference voltage is guided toward c, and the duty is corrected so that the high-level period of the clock becomes longer. Upper and lower limit circuit 1
Reference numeral 8 denotes an integrating circuit 1 so that a clock is continuously output.
7 limits the range of the reference voltage set based on the output of 7. As described above, according to the first embodiment, the average voltage of the high level and the low level voltage of the reception clock is compared with the smoothed voltage of the reception clock, and the reference voltage is adjusted based on the magnitude relationship, thereby adjusting the reception clock. Since the average voltage follows the level fluctuation even when the level fluctuation occurs in the clock voltage,
Fluctuations in duty can be accurately detected and corrected.

Embodiment 2 FIG. 4 shows a clock duty detection and correction circuit according to a second embodiment of the present invention. In the figure, reference numeral 19 denotes an initial value input to an up / down counter 20 described later, and 20 denotes a buffer 5
Is an up / down counter to which the output of the voltage comparator 16 and the initial value 19 are input, and 21 is a digital / analog converter to which the output of the up / down counter 20 is input.

An arbitrary initial value 19 is set in the up / down counter 20 at the same time when the power is turned on. When the output voltage of the voltage comparator 16 is at the H level, the up / down counter 20 adds a predetermined value, for example, 1 to the count value by using the transmission clock output from the buffer 5 as a trigger, and the output of the voltage comparator 16 becomes L In the case of the level, a predetermined value, for example, 1 is subtracted from the count value using the transmission clock output from the buffer 5 as a trigger. Digital / analog converter 2
1 outputs to the voltage comparator 4 a voltage obtained by converting the count value of the up / down counter 20 into an analog value as a reference voltage. The voltage comparator 4 compares the reference voltage output from the digital / analog converter 21 with the voltage signal of the reference frequency oscillated by the oscillator 2 and converts it into a binary signal clock.

With the above operation, when the high-level period of the reception clock output from the buffer 7 is longer than a predetermined value, the count value is incremented by one for each reception clock by the up / down counter 20 and the digital / analog converter 21 The reference voltage output from the terminal increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high-level period of the clock is shortened. When the high-level period of the reception clock output from the buffer 7 is shorter than a predetermined value, the up / down counter 20 sets the count value to 1 for each reception clock.
Then, the reference voltage output from the digital / analog converter 21 is decreased, the reference voltage is guided toward c as shown in FIG. 3, and the duty is corrected so that the H level period of the clock becomes longer. You.

Embodiment 3 FIG. 5 shows a clock duty detection and correction circuit according to a third embodiment of the present invention. In the figure, reference numeral 22 denotes a multi-output delay circuit for delaying the reception clock output from the buffer 7 by an arbitrary minute time and outputting a plurality of clocks shifted in phase, and 23 denotes a multi-output delay circuit according to a count value of an up / down counter 29 described later. A selection circuit for selecting a clock with a phase shift outputted from the multi-delay output circuit 22; a first driver 24 receiving the output of the buffer 7 as an input; and a second driver 25 receiving the output of the selection circuit 23 as an input. Driver, 26 is the first
The first phase comparator 27 receives the non-inverted output of the driver 24 and the inverted output of the second driver 25 as inputs, and the input 27 receives the inverted output of the first driver 24 and the non-inverted output of the second driver 25 as inputs. A second phase comparator, 28 is an initial value input to an up / down counter described later, 29 is an up / down counter to which the output of the first phase comparator and the initial value 28 are input, and 30 is a second phase comparator. This is a charge pump that receives the output of the comparator as an input.

The operation of the duty detection and correction circuit shown in FIG. 5 will be described below. The received clock output from the buffer 7 is input to the first driver 24 and the multi-output delay circuit 22. The first driver 7 inputs a non-inverted output and an inverted output of the received clock to a first phase comparator 26 and a second phase comparator 27, respectively. The multi-output delay circuit 22 delays the reception clock by an arbitrary minute time and outputs a plurality of reception clocks having different phases. The selection circuit 23 includes a multi-output delay circuit 2 according to a count value of an up / down counter 29 described later.
2. Select the delay clock output from 2. Selection circuit 2
3 is input to the second driver 25. The second driver 25 compares the inverted output and the non-inverted output of the delayed clock with a first phase comparator 26 and a second phase comparator 26, respectively. Input to the container 27.

The first phase comparator 26 receives the non-inverted output of the received clock and the inverted output of the delayed clock selected by the selection circuit 23 via the first and second drivers 24 and 25, respectively. You. Here, as an example of the first and second phase comparators 26 and 27 described below,
FIG. 6 shows a general configuration of a phase comparator that responds to a rise of a pulse. The phase difference signals Pu1 and Pd1 when the non-inverted output of the received clock output from the first driver 24 and the inverted output of the delayed clock output from the second driver 25 are fp1 and fr1, respectively.
FIG. 7 shows an example of the input / output timing of FIG. According to the phase comparator shown in FIG. 6, the first phase comparator detects the rising phase difference of the delayed clock fr1 with respect to the non-inverted output fp1 of the received clock as shown in FIG. Are output, respectively. These phase difference signals Pu1 and Pd1 output from the first phase comparator are input to the up / down counter 29.

An arbitrary initial value 28 is input to the up / down counter 29 at the same time when the power is turned on. Based on the phase difference signals Pu 1 and Pd 1 input from the first phase comparator 26, the clock is used as a trigger to generate a count value. Add or subtract one by one. The count value of the up / down counter 29 is input to the selection circuit 23, and the selection circuit 23 generates a delay clock that reduces the phase difference detected by the first phase comparator 26 in accordance with the count value. 22 outputs. With the above operation, the rising edge of the received clock input to the first phase comparator 26 and the rising edge of the inverted signal of the received clock are substantially the same. That is, the selection circuit 23 selects and outputs a delayed clock whose falling edge coincides with the rising edge of the received clock from the outputs of the multi-output delay circuit 23.

An inverted output of the received clock and a non-inverted output of the delayed clock selected by the selection circuit 23 are input to the second phase comparator 27 via first and second drivers 24 and 25, respectively. You. Due to the operation of the first phase comparator 26 described above, the falling edges of the two clock waveforms input to the first phase comparator 27 substantially match. The second phase comparator determines the rising phase of the delayed clock with respect to the rising of the inverted output of the received clock starting from the inverted output of the received clock output from the first and second drivers 24 and 25 and the falling of the delayed clock. And outputs a phase difference signal indicating the amount of delay or the amount of advance. Here, when the high-level period of the received clock is longer than the low-level period, the rising of the inverted output of the received clock output from the first driver 24 corresponds to the non-inverted output of the delayed clock output from the second driver 25. , And a phase difference signal representing the amount of delay is output. Conversely, when the high-level period of the received clock is shorter than the low-level period, the rising of the inverted output of the received clock output from the first driver 24 corresponds to the non-inverted output of the delayed clock output from the second driver 25. And a phase error signal representing the amount of advance is output.

These phase difference signals output from the second phase comparator 27 are input to the charge pump 30.
The charge pump 30 outputs a positive-polarity pulse when the phase difference signal is a delay amount, and outputs a negative-polarity pulse signal when the phase difference signal is a lead amount. FIG. 8 shows a configuration example of the charge pump 30. The phase difference signal Pu2 when the inverted output of the received clock output from the first driver 24 and the non-inverted output of the delayed clock output from the second driver 25 are fp2 and fr2, respectively.
FIG. 9 shows a timing chart of Pd2 and the control signal Pout output by the charge pump 30.

According to the above operation, when the high-level period of the reception clock output from the buffer 7 is longer than the low-level period, a positive-polarity pulse is input from the charge pump to the integration circuit 17. The output reference voltage rises. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high-level period of the clock is shortened. Also,
When the high-level period of the reception clock output from the buffer 7 is shorter than the low-level period, a negative-polarity pulse is input from the charge pump to the integration circuit 17, and at this time, the reference voltage output from the integration circuit 17 decreases. . Thereby, the reference voltage is guided toward c as shown in FIG.
The duty is corrected so that the high-level period of the clock is shortened.

As described above, the clock duty detection and correction circuit according to the third embodiment uses the phase difference between the rising edge of the delayed clock obtained by delaying the falling edge of the receiving clock to coincide with the rising edge and the falling edge of the received clock. , The fluctuation of the duty of the reception clock is detected based on the above, so that even when the signal waveform of the reception clock has distortion or the like, the fluctuation of the duty can be accurately detected and corrected. Further, the variation of the duty can be similarly detected by the phase difference between the falling edge of the delayed clock obtained by delaying the rising edge of the receiving clock so that the rising edge coincides with the falling edge and the rising edge of the receiving clock.

Embodiment 4 FIG. 10 shows a clock duty detection and correction circuit according to a fourth embodiment of the present invention. In the figure, reference numerals 31 and 32 denote an inversion circuit which receives a phase difference signal output from a second phase comparator, respectively, and reference numeral 33 denotes an RS flip-flop which receives a phase difference signal inverted by the inversion circuits 31 and 32 as an input. It is. FIG. 11 shows the phase difference signals Pu2 and Pd2 output from the second phase comparator 27 and
4 is a timing chart showing an output of an RS flip-flop 33 to which outputs Pu2 ′ and Pd2 ′ inverted by 1 and 32 are input. As shown in FIG.
Reference numerals 1 and 32 invert and output the phase difference signals Pu2 and Pd2 output from the second phase comparator 27. The RS flip-flop 33 sets the RS flip-flop when the phase difference signal Pu2 is output and outputs an H-level voltage, and resets the RS flip-flop when the phase difference signal Pd2 is output and outputs an L-level voltage. .

Accordingly, when the phase difference signal Pu2 is output, that is, when the high level period of the reception clock output from the buffer 7 is longer than the low level period, R
The H level voltage is output from S flip-flop 33, and the reference voltage output from integration circuit 17 rises.
Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high-level period of the clock is shortened. When the phase error signal Pd2 is output, that is, when the high-level period of the reception clock output from the buffer 7 is shorter than the low-level period, R
The L level voltage is output from S flip-flop 33, and the reference voltage signal output from integration circuit 17 falls. Thereby, as shown in FIG. 3, the reference voltage is guided toward c, and the duty is corrected so that the high-level period of the clock is shortened.

Embodiment 5 FIG. 12 shows a clock duty detection and correction circuit according to a fifth embodiment of the present invention. In the figure, reference numeral 34 denotes an initial value input to an up / down counter 35 described later, and 35 denotes a count value based on the phase difference signal output from the second phase comparator 27 with the initial value 34 as an initial value. It is an up / down counter that adds or subtracts a predetermined value, for example, 1.

An arbitrary initial value 34 is set in the up / down counter 35 at the same time when the power is turned on. When the phase difference signal Pu2 is input from the second phase comparator 27, that is, when the high-level period of the reception clock output from the buffer 7 is longer than the low-level period, the up / down counter 35 counts in the reception clock cycle. When the phase difference signal Pd2 is input, that is, when the high-level period of the reception clock output from the buffer 7 is shorter than the low-level period, the value is subtracted by one from the count value in the reception clock cycle. The digital / analog converter 21 outputs the voltage obtained by converting the count value of the up / down counter 35 to an analog amount to the voltage comparator 4 as a reference voltage. The voltage comparator 4 compares the voltage signal of the reference frequency oscillated by the oscillator 2 with the reference voltage output from the digital / analog converter 21 to convert the voltage signal into a binary signal clock.

With the above operation, when the high level period of the reception clock output from the buffer 7 is shorter than the low level period, the reference voltage output from the digital / analog converter 21 increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high-level period of the clock is shortened. When the high level period of the reception clock output from the buffer 7 is shorter than the low level period, the analog reference voltage output from the digital / analog converter 21 decreases.
As a result, the reference voltage is guided in the direction c as shown in FIG. 3, and the duty is corrected so that the high-level period of the clock is shortened.

Since the present invention is configured as described above, it has the following effects.

According to the clock duty detection circuit of the present invention, an average voltage or a weighted average of both voltages obtained by adding a high level voltage and a low level voltage of a clock, and the clock by a low-pass filter. Since the change in the duty of the clock is detected based on the magnitude relationship with the smoothed voltage, it is possible to reduce the deterioration of the detection accuracy due to the level change of the clock voltage.

The clock duty correction circuit according to the present invention compares the voltage signal oscillated from the oscillator with a reference voltage set between the maximum value and the minimum value of the voltage signal. A voltage signal indicating a magnitude relationship between an average voltage or a weighted average voltage of the two voltages obtained by adding the high-level and low-level voltages of the generated clock and a voltage obtained by smoothing the clock with a low-pass filter. , The reference voltage is adjusted based on the above, so that the fluctuation of the duty of the clock can be automatically corrected.

The clock duty correction circuit according to a fourth aspect of the present invention is configured such that an average voltage or a weighted average of both voltages obtained by adding a high level voltage and a low level voltage of a clock generated by a clock generator is obtained. A voltage signal representing the magnitude relationship between the applied voltage and a voltage obtained by smoothing this clock with a low-pass filter is represented by 2
Since the value is fed back to the clock generator as a voltage signal, the fluctuation of the duty of the clock can be automatically corrected.

According to a fifth aspect of the present invention, there is provided a clock duty detecting circuit for changing a clock having both a first voltage level and a second voltage level from a first voltage level to a second voltage level. The first transition point at which the transition is made and the second transition point at which the transition is made from the second voltage level to the first voltage level are delayed by giving a delay amount such that they substantially coincide with each other. Since the configuration is such that the variation of the duty of the clock is detected based on the phase difference between the delayed clock and the first transition point, deterioration of the detection accuracy due to the level variation of the clock voltage, distortion of the signal waveform, etc. is reduced. be able to.

Further, the clock duty correction circuit according to any one of claims 6 to 9 according to the present invention is configured to convert a voltage signal oscillated from an oscillator and a reference voltage set between a maximum value and a minimum value of the voltage signal. A first transition point at which a clock having both a first voltage level and a second voltage level, which are generated by comparison, transitions from the first voltage level to the second voltage level; The delay is given by giving a delay amount such that the second transition point that transitions from the second voltage level to the first voltage level substantially coincides with the second transition point, and the first transition point of the clock and the second transition point of the delayed clock are A reference voltage is adjusted based on a voltage signal representing a delay amount or an advance amount of the phase of the first transition point of the delayed clock with respect to the second transition point of the clock, starting from a point substantially coincident with the transition point. Because of the clock It is possible to automatically correct for variations in Yuti.

According to a tenth aspect of the present invention, there is provided a clock duty correction circuit for generating a clock having a first voltage level and a second voltage level output from a clock generation circuit, the first voltage level being the first voltage level and the second voltage level being the first voltage level. And a second transition point at which the second transition level transitions from the second voltage level to the first voltage level. Starting at a point where the first transition point of the clock substantially coincides with the second transition point of the delayed clock, the phase of the first transition point of the delayed clock with respect to the second transition point of the clock Is fed back to the clock generation circuit as a binary voltage signal as a binary voltage signal, so that the fluctuation of the clock duty can be automatically corrected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock duty detection and correction circuit according to a first embodiment of the present invention.

FIG. 2 shows first and second embodiments in the first embodiment of the present invention.
FIG. 4 is a diagram showing the operation of the sample hold circuit of FIG.

FIG. 3 is a diagram illustrating a method of correcting a duty of a clock according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a clock duty detection and correction circuit according to a second embodiment of the present invention;

FIG. 5 is a block diagram illustrating a configuration of a clock duty detection and correction circuit according to a third embodiment of the present invention.

FIG. 6 shows first and second embodiments according to the third embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration example of a phase comparator of FIG.

FIG. 7 shows first and second embodiments according to the third embodiment of the present invention.
FIG. 4 is a diagram showing a timing chart of the phase comparator of FIG.

FIG. 8 is a diagram illustrating a configuration example of a charge pump according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a timing chart of a charge pump according to a third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a clock duty detection and correction circuit according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a timing chart of an RS flip-flop according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a clock duty detection and correction circuit according to a fifth embodiment of the present invention.

FIG. 13 is a block diagram showing a conventional clock duty correction circuit.

FIG. 14 is a diagram showing a conventional method of correcting the duty of a clock.

[Explanation of symbols]

2 oscillator, 3 variable reference voltage generating circuit, 4 voltage comparator, 9 delay circuit, 11 first sample and hold circuit, 12 second sample and hold circuit, 13, 14
Addition resistor, 15 low pass filter, 16 voltage comparator, 17 integrator, 18 upper / lower limit circuit, 19 initial value, 20 up / down counter, 21 digital / analog converter, 22 multi-output delay circuit, 23 selection circuit, 24 first Driver, 25 second driver,
26 first phase comparator, 27 second phase comparator, 2
8 Initial value, 29 Up / down counter, 30 Charge pump, 31 Inverting circuit, 32 Inverting circuit, 33
RS flip-flop, 34 initial value, 35 up / down counter.

Claims (10)

[Claims] A voltage signal oscillated from an oscillator and a reference voltage set between a maximum value and a minimum value of an amplitude voltage of the voltage signal are compared to generate a clock having both a high level and a low level. A clock generation circuit for generating, a low-pass filter for smoothing the clock output from the clock generation circuit, and a voltage obtained by sampling and holding the high-level and low-level voltages of the clock for each cycle of the clock A sample-and-hold circuit, and a voltage averaging circuit that outputs an average value or a weighted average value of voltages output from the sample-and-hold circuit, and a magnitude relationship between an output voltage of the voltage averaging circuit and an output voltage of the low-pass filter is provided. A clock duty detection circuit for detecting a change in the duty of the clock based on the clock duty. . 2. A voltage comparator including the clock duty detection circuit according to claim 1, which compares an output voltage of a voltage averaging circuit with an output voltage of a low-pass filter and outputs a voltage signal indicating a magnitude relationship between the two voltages. And a clock duty correction circuit for correcting a duty of the clock by adjusting a reference voltage based on an output of the voltage comparator. 3. A voltage comparator that includes the clock duty detection circuit according to claim 1, compares the output voltage of the voltage averaging circuit with the output voltage of the low-pass filter, and outputs a voltage signal indicating a magnitude relationship between the two voltages. A counter that changes the count value based on the output of the voltage comparator, and a D / A converter that converts the count value of the counter into a voltage, based on the output of the D / A converter. A clock duty correction circuit for correcting a duty of the clock by adjusting a reference voltage. 4. The clock duty correction circuit according to claim 2, wherein the voltage signal indicating the magnitude relationship between the output voltage of the voltage averaging circuit output from the voltage comparator and the output voltage of the low-pass filter is a binary signal. A clock duty correction circuit, which is a voltage signal. 5. A method of comparing a voltage signal oscillated from an oscillator with a reference voltage set between a maximum value and a minimum value of the amplitude voltage of the voltage signal to compare the first voltage level and the second voltage level. A clock generation circuit that generates a clock having both levels; a first transition point at which the voltage level of the clock transitions from the first voltage level to the second voltage level; And a delay circuit that delays the clock by giving a delay amount such that a second transition point that transitions from the voltage level to the first voltage level substantially coincides with the second transition point of the clock. A clock duty detection circuit that detects a change in duty of the clock based on a phase difference between the clock and a first transition point delayed by the delay amount. 6. The clock duty detection circuit according to claim 5, wherein a first transition point of the clock output from the clock generation circuit and a second transition point of the clock delayed by the delay circuit are substantially equal to each other. A phase difference detection circuit that outputs a voltage signal representing the amount of delay or advance of the phase of the first transition point of the clock delayed by the delay circuit with respect to the second transition point of the clock with the coincident point as the starting point And a clock duty correction circuit for correcting a duty of the clock by adjusting a reference voltage based on a voltage signal output from the phase difference detection circuit. 7. A voltage holding circuit including the clock duty correction circuit according to claim 6, wherein the voltage holding circuit generates and holds a voltage value based on a voltage signal output from the phase difference detection circuit.
A clock duty correction circuit, wherein a duty of the clock is corrected by adjusting a reference voltage based on an output of the voltage holding circuit. 8. The clock duty detection circuit according to claim 5, wherein a first transition point of the clock output from the clock generation circuit and a second transition point of the clock delayed by the delay circuit are substantially equal to each other. The count value is changed based on whether the phase of the first transition point of the clock delayed by the delay circuit with respect to the second transition point of the clock starting from the coincident point is the lagging phase or the leading phase. A counter, and a D / A converter for converting a count value of the counter into a voltage value, wherein the duty of the clock is corrected by adjusting a reference voltage based on an output voltage of the D / A converter. Characteristic clock duty correction circuit. 9. The clock duty detection circuit according to claim 5, wherein the first voltage level and the second voltage level are respectively a high level voltage and a low level voltage of a clock output from the clock generation circuit, or a high level. A clock duty detection circuit, which is any combination of a voltage and a low level voltage. 10. The clock duty correction circuit according to claim 6, wherein the voltage signal output from the phase difference detection circuit is a binary voltage signal.