JP2001144742A - Data communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide data communication equipment including an error correction circuit in which throughput does not fall in a packet communication and packet data omission is also hardly generated. SOLUTION: A transmitting part is provided with a data outputting means 11 which outputs a data string in which 1 continues in a period when a preamble code is transmitted and a convolutional encoder 12 which outputs a symbol data string in which 0 and 1 are alternately repeated when the data string in which 1 continues is inputted. A receiving part is provided with a symbol period dividing means 6 which divides the received symbol data string into a 1st symbol period and a 2nd symbol period, a ratio calculating means 7 which calculates a ratio in which the sum of the number of 0s included in the 1st symbol period and the number of 1s included in the 1st symbol period occupies the number of all symbols, a symbol synchronizing means 8 that outputs a synchronizing signal on condition that the ratio surpasses a prescribed reference value and a Viterbi decoder 5 that decodes transmitted data from the received symbol data string on the synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device, and more particularly to an error correction circuit for transmitted / received data in a data communication device used for data communication such as packet communication where transmitted / received data is intermittent.

[0002]

2. Description of the Related Art An error correction circuit represented by a combination of a convolutional encoder and a Viterbi decoder is applied to a data communication apparatus in a situation where communication quality is deteriorated in an environment with multipath fading or a lot of noise. Since the error rate can be suppressed, the communication performance of the data communication device can be improved and the communication distance can be extended. Here, the convolutional encoder is used for encoding transmission data in the transmission unit of the data communication device, and the Viterbi decoder is used for decoding reception data in the reception unit of the data communication device. is there.

Heretofore, there has been a data communication apparatus such as a cellular phone in which transmission / reception data is continuous, in which the above-described error correction circuit is used. FIG. 6 is a block diagram of an example of a receiving unit built in such a data communication device.
In this receiving section, the received data received by antenna 100 is sent to baseband processing section 103 via RF section 101 and demodulating section 102. Baseband processing unit 103
Is the Viterbi decoder 104, the start code determination unit 10
5. Send the received data to the symbol synchronization circuit 106.

[0004] Under the condition that a continuous data string is received, the symbol synchronization circuit 106 first regards a certain symbol as the head and causes the Viterbi decoder 104 to perform an error correction process for a predetermined period, thereby improving the error rate. Is not found, it is determined that symbol synchronization has not been achieved, the head of the symbol is shifted, the Viterbi decoder 104 performs error correction processing again, and the above operation is repeated until the error rate is improved. .

A start code determining unit 105 determines a start code indicating the head of the received data sent from the baseband processing unit 103. This determination process is performed by an error correction circuit, that is, a Viterbi decoder 104. It was performed based on the received data before passing. this is,
This is because all the trellis path search memories of the Viterbi decoder 104 are initialized to 0 after the start code determination unit 105 determines the start code.

FIG. 7 is a diagram showing the relationship between the received data received by the receiving section and the operating state of the Viterbi decoder 104. In the receiving unit, the Viterbi decoder 104 does not operate during reception of the preamble code and the start code of the received data, and resets the Viterbi decoder 104 to start the operation after receiving the start code. Was.

FIG. 8 is a block diagram showing an internal configuration of a convolutional encoder 110 provided in a transmission section built in the data communication apparatus. The convolutional encoder 110 has a constraint length K = 5 and a coding rate R = 1/2. The convolutional encoder 110 includes a shift register 107, a first mod2 adder 108, and a second mod2 adder 109. The input to the convolutional encoder 110 is input to the first-stage register 107a in the shift register 107, which sequentially outputs the second-stage register 107b, the third-stage register 107c, the fourth-stage register 107d, and the fifth-stage register 107d. It is sent to the eye register 107e. First mod2 adder 108
The output S4 of the first-stage register 107a, the output S3 of the second-stage register 107b, and the fourth-stage register 107
The output S1 of the first stage register 107a, the output S4 of the first stage register 107a, and the output S0 of the third stage register 107e are input to the second mod2 adder 109.
c output S2, output S1 of the fourth-stage register 107d,
The output S0 of the fifth-stage register 107e is input. Also, from the convolutional encoder 110, the first m
The output G0 of the mod2 adder 108 and the output G1 of the second mod2 adder 109 are output alternately.

FIG. 9 is a state transition table for explaining the operation of the convolutional encoder 110. For example, as described in the first row of the table, (S3, S2, S1, S0) =
In the state of (0,0,0,0), the first-stage register 107
When 0 is input to a and S4 = 0, the first mod
The outputs (G0, G1) of the two adders 108 and the second mod2 adder 109 are (0, 0). At this time, the next state of (S3, S2, S1, S0) is also (0,
0,0,0).

Further, (S3, S2, S1, S0) =
If S4 = 1 in the state of (0,0,0,0), the output (G0, G1) = (1,1). At this time, the next state of (S3, S2, S1, S0) is (1, 0, 0,
0).

As described in the last row of the table, (S
3, S2, S1, S0) = (1, 1, 1, 1), and if S4 = 0, the output (G0, G1) = (1,
1), and the next state of (S3, S2, S1, S0) is (0, 1, 1, 1).

Further, (S3, S2, S1, S0) =
If S4 = 1 in the state of (1,1,1,1), the output (G0, G1) = (0,0), and the next (S3, S3)
The state of (2, S1, S0) is also (1, 1, 1, 1)
Becomes That is, when “1” is continuously input to the convolutional encoder 110, the output (G0, G1, G0, G1,...) Of the convolutional encoder 110 becomes (0, 0, 0, 0,.
…).

[0012]

As described above, the conventional error correction circuit using a convolutional encoder and a Viterbi decoder has been used in a data communication device such as a cellular phone, in which transmission / reception data is continuous. If this error correction circuit is applied to packet communication where transmission and reception data is intermittent, continuous transmission and reception data is not used in this packet communication, so that it is difficult to synchronize symbols by the above-described processing method. .

Therefore, in order to use the above-described error correction circuit for packet communication, a long preliminary period for performing symbol synchronization processing, that is, a long preamble code which is not related to the data body to be transmitted / received is required. There is a problem that transmission / reception throughput is reduced.

Further, in packet communication, there are many usage modes in which a plurality of transmitting terminals exist, and once symbol synchronization is established with a certain transmitting terminal, symbol synchronization is again performed when communicating with another transmitting terminal. Need to do so, further reducing throughput.

Further, if correct data cannot be received,
There is also a problem that it is difficult to distinguish whether the symbol is not synchronized or there is no terminal transmitting data.

Conventionally, the process of determining the start code indicating the head of the received data is performed on the uncorrected data before passing through the error correction circuit. Therefore, the error correction is not performed on the start code itself. However, there has been a problem that erroneous determination of a start code is apt to occur and packet data is likely to be lost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention has been made in consideration of the above problems, and has been made in view of the above. An apparatus is provided.

[0018]

According to the present invention, there is provided a data communication apparatus having a transmitting unit and a receiving unit, wherein the transmitting unit comprises:
Data output means for outputting a data string in which 1s are continuous during a period in which a preamble code is transmitted as transmission data; and when a data string in which 1s are continuous is input from the data output means, 0 and 1 alternate. A convolutional encoder that outputs a repeated symbol data sequence and a transmission unit that transmits the symbol data sequence output by the convolutional encoder are provided. The receiving unit may include a receiving unit that receives the symbol data sequence transmitted by the transmitting unit, and a symbol data sequence received by the receiving unit that follows the first symbol period and the first symbol period. The symbol period dividing unit that divides the symbol into the second symbol period, and the sum of the number of 0s included in the first symbol period and the number of 1s included in the second symbol period divided by the symbol period dividing unit is: A ratio calculating means for calculating a ratio of the total number of symbols, a symbol synchronizing means for starting symbol synchronization on condition that the ratio calculated by the ratio calculating means exceeds a predetermined reference value, and outputting a synchronizing signal; A Viterbi decoder for decoding transmission data from the symbol data sequence received by the receiving means based on a synchronization signal obtained from the symbol synchronization means. The features.

According to the above configuration, when a data string in which 1s are consecutively input to the convolutional encoder during a period in which the transmission section transmits the preamble code as transmission data, the symbol data which is the output of the convolutional encoder is transmitted. Is a pattern in which 0 and 1 are repeated. When this pattern is received by the receiving unit, the symbol period dividing means incorporated in the receiving unit
The symbol data sequence is divided into a first symbol period and a second symbol period, and the sum of the number of 0s included in the first symbol period and the number of 1s included in the second symbol period is calculated for all symbols. The ratio calculation means calculates the ratio to the number, and the Viterbi decoder serving as an error correction circuit starts symbol synchronization based on the calculation result. Therefore, symbol synchronization becomes easy, and a long preamble code is not required.

Further, in the data communication device according to the present invention, the data output means outputs data corresponding to a start code after outputting a data string in which 1s are continuous during a period in which a preamble code is transmitted as transmission data. Wherein the receiving unit is provided at a stage subsequent to the Viterbi decoder,
It is characterized by comprising a start code determining means for determining the presence or absence of a start code from the transmission data sequence decoded by the Viterbi decoder.

According to the above configuration, the start code judging means is provided in the receiving section after the Viterbi decoder, so that when the receiving section receives the start code,
After the start code is corrected for error by the Viterbi decoder, the start code is sent to the start code determining means, and a determination process is performed. Therefore, erroneous determination of the start code can be prevented, so that packet data loss can be prevented.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a data communication apparatus according to an embodiment of the present invention will be described with reference to the block diagram of FIG. This data communication device has a receiving unit and a transmitting unit. First, the configuration of the receiving unit will be described. Reference numeral 1 denotes an antenna for receiving a signal.
It is connected to the. The output of the RF unit 2 is input to a demodulation unit 3 that demodulates the received signal, and the output of the demodulation unit 3 is input to a baseband processing unit 4.

The output of the baseband processing unit 4 is input to a Viterbi decoder 5 for decoding received data and a symbol period dividing unit 6 for dividing the received data into a first symbol period and a second symbol period. Have been. The output of the symbol period dividing means 6 is input to the ratio calculating means 7.
The ratio calculating means 7 counts the number of data "0" included in the first symbol period and the number of data "1" included in the second symbol period for a predetermined period, and, based on the count result, both data. Calculates the ratio of the total number of data to the total number of data, and outputs the calculation result.

The first and second symbol periods will be described. For example, assume that the received data input from the baseband processing unit 4 to the symbol period dividing means 6 is D1, D2, D3, D4,. However, D1 and the like are data of one symbol. Then
The data classified into the first symbol period is D1, D
, D5,... And data classified into the second symbol period are D2, D4, D6,.

For example, the symbol period dividing means 6
If received data in which only "0" is repeated, such as 00, is input, all data included in the first symbol period and data included in the second symbol period become "0". This division result is sent to the ratio calculating means 7, which calculates the number A of data "0" included in the first symbol period and the number of data "1" included in the second symbol period. The ratio of the sum of B to the number N of all symbols (A + B) / N is calculated, where A = N /
2. From B = 0, the calculation result is ０, and this calculation result is output from the ratio calculation means 7.

For example, in the symbol period dividing means 6, 11
Assuming that received data in which only “1” is repeated, such as 11, is input, all data included in the first symbol period and data included in the second symbol period are “1”. Therefore, the number A of data “0” included in the first symbol period and the number B of data “1” included in the second symbol period are A = 0 and B = N, respectively.
/ 2, and the ratio calculation result 1/2 is output from the ratio calculation means 7.

For example, in the symbol period dividing means 6, 01
If data in which “0” and “1” are repeated as in “0101...” Is input, all data included in the first symbol period becomes “0”, and data included in the second symbol period is “0”. All become "1". Therefore, the number A of data “0” included in the first symbol period and the second
Since the number B of data "1" included in the symbol period of A is A = N / 2 and B = N / 2, the ratio is (A
+ B) / N = (N / 2 + N / 2) / N = 1, and this ratio 1 is output from the ratio calculating means 7.

The output of the ratio calculation means 7 is input to a symbol synchronization circuit 8. The symbol synchronization circuit 8 outputs a synchronization signal, and the output synchronization signal is input to the Viterbi decoder 5. Note that the synchronization signal is a Viterbi decoder 5
Are signals for synchronizing the symbol data input from the baseband processing unit 4 to the Viterbi decoder 5.

The Viterbi decoder 5 continuously decodes the symbol data sent from the baseband processing unit 4 based on the input of the synchronization signal from the symbol synchronization circuit 8. The baseband processing unit 4 and the Viterbi decoder 5 operate irrespective of symbol synchronization, but the symbol synchronization circuit 8 updates the symbol timing of the Viterbi decoder 5 as necessary. That is, the Viterbi decoder 5 decodes the symbol data while taking timing with the synchronization signal. The received data decoded by the Viterbi decoder 5 is sent to the microcomputer 9.

The microcomputer 9 has a built-in start code judging means 10 for judging a start code in the received data as a component of the receiving section. The decoded received data sent from the Viterbi decoder 5 is input to the start code determining means 10.

Next, the configuration of the transmitting section will be described. The microcomputer 9 includes a data output unit 11 as a component of the transmission unit. This data output means 11 outputs transmission data, and the output transmission data is
The transmitted data is input to a convolutional encoder 12 that encodes the data. The convolutional encoder 12 encodes the input transmission data and outputs encoded transmission data, that is, symbol data.

The feature of the convolutional encoder 12 is that when data "1" is continuously input to the convolutional encoder 12, the convolutional encoder 12 outputs a symbol "0" and a symbol "1". It is to be output alternately and repeatedly.

The encoded transmission data (symbol data) output from the convolutional encoder 12 is input to the modulator 13. The modulator 13 modulates the input transmission data and outputs the modulated transmission data. The output transmission data is input to the RF unit 2. The antenna 1 is connected to the RF unit 2. That is, the antenna 1 and the RF unit 2 are components commonly used for the transmission unit and the reception unit.

Next, the operation of this embodiment will be described. In the following description, it is assumed that communication is performed between two data communication devices having the same configuration, and one data communication device performs transmission and the other data communication device performs reception. Therefore, the data communication device of the present embodiment includes both the transmission unit and the reception unit, but the transmission unit in the transmission-side data communication device and the reception unit in the reception-side data communication device operate. It is assumed that

When the transmission section in the data communication device on the transmission side transmits data, first, the data output means 11 outputs transmission data. The data output first from the data output means 11 as transmission data is data in which "1" corresponding to the preamble code added to the head of the transmission data is continuous.

The data output means 11 outputs a start code after the preamble code, outputs a data body next to the start code, and finally outputs a CRC (Cyclic Redundancy).
Check) code is output.

Hereinafter, the description will be made on the assumption that the data output unit 11 outputs data in which "1" s corresponding to the preamble code are continuous.

"1" output from the data output means 11
Are input to the convolutional encoder 12. The convolutional encoder 12 encodes the input data in which "1" is continuous, converts the data into symbol data in which "0" and "1" are alternately repeated, and outputs the converted symbol data.

The symbol data output from the convolutional encoder 12 is input to a modulator 13, which modulates the input symbol data, converts the modulated symbol data into a modulated signal, and outputs the modulated signal. The output modulated signal is sent to the antenna 1 via the RF unit 2, and the antenna 1 transmits the modulated signal sent from the RF unit 2.

When the transmitted modulated signal is received by the receiving unit in the data communication device on the receiving side, first, the antenna 1 of the data communication device on the receiving side receives the modulated signal and receives the modulated signal. The signal is sent to the demodulation unit 3 via the RF unit 2. The demodulation unit 3 demodulates the transmitted modulated signal to return to the original symbol data, and sends the returned symbol data to the baseband processing unit 4. The baseband processing unit 4 sends the symbol data sent from the demodulation unit 3 to the Viterbi decoder 5 and the symbol period dividing unit 6.

The symbol period dividing means 6 divides the symbol data sent from the baseband processing section 4 into a first symbol period and a second symbol period. Here, as described above, it is assumed that the transmission data corresponding to the preamble code is currently output from the data output unit 11 in the transmission-side data communication device. Since the preamble code is transmitted and the transmitted preamble code is received by the data communication device on the receiving side, the preamble code is also input from the baseband processing unit 4 to the symbol period dividing means 6.

The preamble code is, as described above,
010101... Are data strings in which data “0” and data “1” are alternately repeated. Therefore, when this data string is divided into a first symbol period and a second symbol period for each bit, "1"
Only “0” is classified, and “1” is used in the second symbol period.
Are just classified. Note that, depending on the timing of symbol period division, only “1” may be classified in the first symbol period and only “0” may be classified in the second symbol period. The symbol period dividing means 6 sends this division result to the ratio calculating means 7.

Based on the division result sent from the symbol period dividing unit 6, the ratio calculating unit 7 calculates the number A of data "0" included in the first symbol period and the data A included in the second symbol period. The number B of “1” is counted for a predetermined period, and the number (A +
The ratio (A + B) / N between B) and the number N of all symbols is calculated. As described above, at this time, the data communication apparatus on the receiving side has received the preamble code, and the preamble code is also sent from the baseband processing unit 4 to the symbol period dividing means 6. The data included in the symbol period is only "0", and the data included in the second symbol period is only "1". Therefore,
The ratio of the number of synchronized symbols to the total number of symbols is A
= N / 2 and B = N / 2, (A + B) / N = (N / 2
+ N / 2) / N = 1. The ratio calculation means 7 sends the calculated ratio 1 to the symbol synchronization circuit 8. On the other hand, as described above, depending on the symbol division timing, the first
In some cases, the data included in the symbol period is only "1", and the data included in the second symbol period is only "0". At this time, the ratio of the number of synchronized symbols to the total number of symbols is given by A = 0 and B = 0.
(A + B) / N = 0 / N = 0. Ratio calculation means 7
Sends the calculated ratio 0 to the symbol synchronization circuit 8.

The symbol synchronization circuit 8 determines whether or not the ratio sent from the ratio calculation means 7 falls within a predetermined range. When it is determined that the ratio falls within the predetermined range, the Viterbi decoder 5 Outputs a synchronization signal to Specifically, the symbol synchronization circuit 8 determines the ratio (A +
B) / N is (A + B) /N≧0.9 or (A + B)
It is determined whether or not /N≦0.1. Here, as described above, when the ratio sent from the ratio calculating means 7 is 1, since 0.9 ≦ (A + B) / N = 1, the ratio falls within a predetermined range. Therefore, the symbol synchronization circuit 8 outputs a synchronization signal to the Viterbi decoder 5. When the ratio sent from the ratio calculation means 7 is 0, 0.1 ≧ (A + B) / N =
Since it is 0, the symbol synchronization circuit 8 sends a synchronization signal to the Viterbi decoder together with the information that the timing is inverted. In the present embodiment, the “predetermined range” is defined by the numerical value (A + B) /N≧0.9 or (A + B) / N ≦
Although the value is set to 0.1, the present invention is not limited to this, and another numerical value may be used.

As described above, when the data communication device on the receiving side receives the preamble code, the symbol synchronization circuit 8 outputs a synchronization signal to the Viterbi decoder 5.

When the input of the synchronizing signal from the symbol synchronizing circuit 8 is started, the Viterbi decoder 5 updates the symbol synchronizing timing serving as a reference for decoding the symbol data sent from the baseband processing unit 4, Continue decoding the data. That is, the Viterbi decoder 5 decodes the symbol data while taking the timing with the synchronization signal, and restores the original data. The restored packet data becomes the same as the transmission data output by the data output means 11 in the data communication device on the transmission side if there is no error in all of the transmission and reception packet periods. Whether the decoding of the packet data is normal or not is determined based on the above-described CRC code, and communication control is performed based on the validity of the packet data. For example, as a result of checking the CRC code, if the packet data is valid, the Viterbi decoder 5 sends the decoded data to the microcomputer 9;
Communication control is performed such that the transmitting side retransmits the packet data. The control of this communication may be performed mainly by the microcomputer 9.

Since the Viterbi decoder 5 has a function of correcting an error in the input symbol data, even if the input symbol data has an error less than an allowable ratio, it is necessary to correct the error. Thus, the original data can be restored.

The Viterbi decoder 5 sends the decoded data to the microcomputer 9. Microcomputer 9
Performs post-processing of data transmitted from the Viterbi decoder 5, that is, received data. At this time, the received data sent from the Viterbi decoder 5 to the microcomputer 9 is also input to the start code determination means 10 built in the microcomputer 9.

Here, it has been assumed that the data currently transmitted / received is the preamble code, but the start code is transmitted / received next to the preamble code. When the start code is received by the receiving data communication device,
The start code determination means 10 in the data communication device on the receiving side determines the reception of the start code. When the start code determining means 10 determines that the start code has been received, the circuit subsequent to the start code determining means 10 prepares for receiving the data body so that the data body transmitted following the start code can be received. Command. The circuit at the subsequent stage of the start code judging means 10 receives
When the reception of the start code is completed and the subsequent data body starts to be received, the reception processing of this data body is started.

According to the above configuration, the data input to the start code determination means 10 is always data after passing through the Viterbi decoder 5 which is an error correction circuit. It passes through a certain Viterbi decoder 5. Therefore, the start code is error-corrected in the same manner as other data, so that errors in the start code determination by the start code determination means 10 can be reduced.

Next, with reference to FIG. 2, the relationship between the received data input to the receiving unit of the data communication apparatus according to the present embodiment and the operation state of the Viterbi decoder 5 in the receiving unit will be described. The Viterbi decoder 5 completes the reception of the start code and the data body from the time when the preamble code is received as the reception data, and executes the CRC (Cyclic Redun).
dancy Check) It operates continuously including the time when the code is received.

That is, after the Viterbi decoder 5 determines the symbol synchronization during the reception of the preamble code, the start code transmitted following the preamble code is sent to the start code determination means 10. 5
Is entered via Then, the start code judging means 10 detects the start code, and performs the following data reception processing.

That is, since the Viterbi decoder 5 can perform error correction processing on the start code, the probability of a bit error in the start code is greatly reduced, thereby preventing packet loss and erroneous determination. be able to.

Since the preamble code is a data sequence suitable for the Viterbi decoder 5, the path memory in the Viterbi decoder 5 is filled with substantially correct data when the reception of the preamble code is completed. It is. Therefore, the Viterbi decoder 5 can correctly decode the start code transmitted following the preamble code without initializing the path memory at the start of the start code reception.

Next, the internal configuration of the convolutional encoder 12 in the transmitting section of the present embodiment will be described with reference to the block diagram of FIG. The convolutional encoder 12 has a constraint length K = 5,
The coding rate R = 1/2. The convolutional encoder 12 includes a shift register 14, a first mod2 adder 15, and a second mod2 adder 16. Shift register 1
4 is a first stage register 14a, a second stage register 14
b, third-stage register 14c, fourth-stage register 14
d, a fifth-stage register 14e is built in.

The input to the convolutional encoder 12 is input to a first-stage register 14a in the shift register 14, which sequentially outputs a second-stage register 14b, a third-stage register 14c, and a fourth-stage register 14d. 5th stage register 1
4e. The first mod2 adder 15 has 1
The output S4 of the register 14a of the second stage and the register 1 of the second stage
4b, the output S3 of the third-stage register 14c,
The output S0 of the register 14e at the fifth stage is input.
The output S4 of the first-stage register 14a and the output S4 of the fourth-stage register 14d are provided to the second mod2 adder 16.
The output S0 of the register 14e at the first and fifth stages is input. Also, from the convolutional encoder 12, the first mod2
The output G0 of the adder 15 and the output G1 of the second mod2 adder 16 are output alternately.

Pulled out from the shift register 14,
The number of taps input to the first mod2 adder 15 is 4
Here, the number of taps input to the second mod2 adder 16 is three. That is, the number of taps drawn from the shift register 14 is an even number on one side and an odd number on the other side.

Here, a case is considered where the data taken out from the taps are all "1". When the number of taps is even, the output of the mod2 adder for inputting data "1" from these even taps is the exclusive OR of the input to the mod2 adder, and is "0". Become. Also,
When the number of taps is odd, the output of the mod2 adder that inputs data from these odd taps is "1".

Specifically, the registers 14a, 14b, 1
4c, 14d, 14e (S4, S3, S2, S
(1, S0) = (1,1,1,1,1), (S4, S3, S2, S0) = (1, 1,
(1) The output G of the first mod2 adder 15 for inputting 1)
0 becomes “0”, and (S4, S1, S0) =
The output G1 of the second mod2 adder 16 to which (1,1,1) is input becomes "1".

Since the convolutional encoder 12 outputs the outputs G0 and G1 of the mod2 adder alternately, the output of the convolutional encoder 12, that is, the symbol data is "0" and "1".
1 "are alternately repeated.

In this embodiment, the constraint length K = 5
However, the same effect can be obtained even when the constraint length is longer. Also, as in the case of the coding rate of 1/2, in the case of the coding rate of 1/3, the number of taps to be input to the mod2 adder is either an even number or an odd number for only the first symbol, and is followed by the first symbol. Regarding the remaining symbols, the number of taps to be input to the mod2 adder may be either an odd number or an even number, which is the reverse of the leading symbol.

Next, the operation of the convolutional encoder 12 will be described with reference to the state transition table of FIG. For example, as described in the first row of the table, (S3, S2, S1, S0) =
In the state of (0,0,0,0), the first stage register 14a
Is input to S4 and S4 = 0, the first mod2
The output of the adder 15 and the second mod2 adder 16 (G
(0, G1) = (0, 0). At this time, the next (S
The state of (3, S2, S1, S0) is also (0, 0,
0,0).

Further, (S3, S2, S1, S0) =
If S4 = 1 in the state of (0,0,0,0), the output (G0, G1) = (1,1). At this time, the state of the next (S3, S2, S1, S0) is (1, 0, 0,
0).

As described in the last row of the table, (S
3, S2, S1, S0) = (1, 1, 1, 1), and if S4 = 0, the output (G0, G1) = (1,
0), and the state of the next (S3, S2, S1, S0) is (0, 1, 1, 1).

Also, (S3, S2, S1, S0) =
If S4 = 1 in the state of (1,1,1,1), the output (G0, G1) = (0,1), and the next (S3, S3)
The state of (2, S1, S0) is also (1, 1, 1, 1)
Becomes That is, when “1” is continuously input to the convolutional encoder 12, the output (G
0, G1, G0, G1,...) Are (0, 1, 0, 1,...)
Becomes

That is, when data having consecutive "1" s is input to the convolutional encoder 12 in this embodiment, "0" is used as symbol data as shown in FIG.
And "1" are output alternately.

It should be noted that the data output means 11 in the data communication device on the transmission side transmits the data
It is also conceivable to output a continuous "1" by chance.
Such transmission data is converted by the convolutional encoder 12 into "
Since "0" and "1" are converted into symbol data appearing alternately, when the symbol data is received by the data communication device on the receiving side, the symbol synchronization circuit 8 in the data communication device on the receiving side is used. , A synchronization signal is output during a period that is not a preamble code, and this causes the Viterbi decoder 5 to start symbol synchronization, but even in such a case, the Viterbi decoder 5 does not Since there is only synchronization at the same timing as the synchronized timing, there is no substantial effect.

Also, the pattern of the symbol data is (G0, G1, G0, G1,
..) = (1, 0, 1, 0,...) May be adversely affected when the transmission data is output from the data output unit 11 on the transmission side. However, since the convolutional code by the convolutional encoder 12 is obtained by a recursive operation,
It is unlikely that a continuous reverse pattern will occur. Further, the position of the tap may be selected so that such an inverse pattern does not occur.

The circuit for realizing the present invention has almost no difference in circuit scale from a circuit using a conventional convolutional encoder and a Viterbi decoder, so that the data communication apparatus becomes large. Never.

The determination of the symbol data input to the Viterbi decoder may be 1 or 0, that is, a hard decision, or a multi-bit soft decision.

The present invention is not limited to the radio apparatus using radio waves as in the above embodiment, but can be applied to a transmission / reception apparatus using a power line, an infrared transmission / reception apparatus, and the like.

[0072]

According to the present invention, when a convolutional coder and a Viterbi decoder are applied to packet communication, a long preamble code is not required, so that efficient packet communication becomes possible and throughput is reduced. Can be prevented.
Therefore, an effective error correction circuit can be applied to packet communication, and communication performance in packet communication can be improved.

If a start code determining means is provided at the subsequent stage of the Viterbi decoder, the start code transmitted following the preamble code passes through the Viterbi decoder which is an error correction circuit. , And stable communication with little packet loss becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data communication device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between received data input to a receiving unit of the data communication device according to an embodiment of the present invention and an operation state of a Viterbi decoder 5 in the receiving unit.

FIG. 3 is a block diagram showing an internal configuration of a convolutional encoder 12 in a transmission unit of the data communication device according to one embodiment of the present invention.

FIG. 4 is a state transition table for explaining the operation of the convolutional encoder 12 in the transmission unit of the data communication device according to one embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between data input to a convolutional encoder 12 and symbol data output from the convolutional encoder 12 in a transmission unit of a data communication device according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a receiving unit of a data communication device according to the related art.

FIG. 7 is a diagram showing a relationship between reception data received by a reception unit of a data communication device and an operation state of a Viterbi decoder 104 according to a conventional technique.

FIG. 8 is a block diagram showing an internal configuration of a convolutional encoder 110 provided in a transmission unit of a data communication device according to a conventional technique.

FIG. 9 is a state transition table for explaining the operation of the convolutional encoder 110 provided in the transmission unit of the data communication device according to the related art.

[Explanation of symbols]

Reference Signs List 1 antenna 2 RF unit 3 demodulation unit 4 baseband processing unit 5 Viterbi decoder 6 symbol period division unit 7 ratio calculation unit 8 symbol synchronization circuit (symbol synchronization unit) 9 microcomputer 10 start code determination unit 11 data output unit 12 convolutional code 13 Modulator 14 Shift register 14a First-stage register 14b Second-stage register 14c Third-stage register 14d Fourth-stage register 14e Fifth-stage register 15 First mod2 adder 16 Second mo
d2 adder 100 antenna 101 RF unit 102 demodulation unit 103 baseband processing unit 104 Viterbi decoder 105 start code determination unit 106 symbol synchronization circuit 107 shift register 107a first stage register 107b second stage register 107c third stage register 107d Fourth-stage register 107e Fifth-stage register 108 First m
mod2 adder 109 second mod2 adder 110 convolutional encoder

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04L 29/02 H04L 13/00 301B F-term (Reference) 5J065 AB01 AC02 AD10 AH18 5K014 AA01 BA11 EA04 FA10 5K028 AA11 AA15 BB04 KK01 KK32 MM05 MM10 NN01 NN05 NN12 5K034 AA01 AA04 AA06 CC06 HH01 HH02 HH05 HH07 HH09 HH12 MM01 PP06 PP07 5K047 AA12 BB01 CC01 HH01 HH03 HH12 HH21 HH53 HM57 JJ02

Claims (2)

[Claims] 1. A data communication device comprising a transmission unit and a reception unit, wherein the transmission unit outputs a data string in which 1s are continuous during a period in which a preamble code is transmitted as transmission data; A convolutional coder that outputs a symbol data sequence in which 0s and 1s are alternately repeated when a data sequence of consecutive 1s is input from the output means, and transmits a symbol data sequence output by the convolutional coder. Transmitting means for receiving the symbol data sequence transmitted by the transmitting means; a symbol data sequence received by the receiving means for a first symbol period; The second following the symbol period
A symbol period dividing unit that divides the symbol period into two symbol periods, and the sum of the number of 0s included in the first symbol period and the number of 1s included in the second symbol period divided by the symbol period dividing unit is all symbols A symbol calculating means for calculating a ratio of the number of the symbols, a symbol synchronizing means for starting symbol synchronization on condition that the ratio calculated by the ratio calculating means exceeds a predetermined reference value, and outputting a synchronizing signal; Based on the synchronization signal obtained from the symbol synchronization means,
A data communication device comprising: a Viterbi decoder that decodes transmission data from a symbol data sequence received by the receiving unit. 2. The data output means outputs data corresponding to a start code after outputting a data string in which 1s are continuous during a period in which a preamble code is transmitted as transmission data. 2. The data communication apparatus according to claim 1, further comprising a start code determining unit that determines the presence or absence of a start code from a transmission data string decoded by the Viterbi decoder, at a stage subsequent to the Viterbi decoder.