JP2001184696A - Current output interface circuit and optical disk device - Google Patents

Abstract

(57) Abstract: In a current output interface circuit, an AC output current signal is used as a differential signal and a DC offset when a current value is 0 is almost eliminated. A plurality of first variable current sources having different current values are provided corresponding to the plurality of first variable current sources, and an on / off state is switched and controlled, respectively. A first current output node OUT1 / second current output node corresponding to an on / off state of a corresponding first variable current source
A plurality of switch circuits 35, 36, and 37 connected to OUT2 and a DC correction current connected to a first current output node so that a difference current signal between both nodes becomes 0 when each switch circuit is in an off state. And correction current sources 39, 41, and 43 for flowing current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input / output interface circuit and, more particularly, to a current transfer type current output interface circuit using a current value as a signal, for example, an optical disk apparatus for recording image data. It is used in laser emission control circuits for laser beam printers, plain paper copiers (PPC), etc.

[0002]

2. Description of the Related Art In recording in an optical disk device, information is recorded by forming pits (recording marks) on an optical disk according to a period during which a laser beam is emitted. At this time, as the recording waveform, for example, as shown in FIG. 6A, the laser emission power is switched in a plurality of stages to form a recording mark having an ideal shape as shown in FIG. 6B.

In order to increase the recording density, the output signal current of the laser drive circuit for giving the laser emission power must have a sharp current change, and the laser emission for controlling the laser drive circuit must be increased. The change in the output signal current of the control circuit must be sharp.

In addition, since the speed of the medium is different between the inner circumference and the outer circumference, and the speed is higher on the outer circumference, in order to form pits having the same shape on the inner circumference and the outer circumference, the pits on the outer circumference are required. The emission power of the laser must be higher than that on the inner circumference side, and the emission power of the laser must be controlled in accordance with the track position of the medium.

Therefore, a current output interface circuit for turning on / off a variable current source by a high-speed switch circuit is used as a laser emission control circuit. By performing the laser emission control in the current mode, there is an advantage that the transmission band can be widened and the influence of the background noise is small.

FIG. 7 shows a current output interface circuit used in a laser emission control circuit of a conventional optical disk device.

In FIG. 7, reference numeral 1 denotes an output circuit of a recording waveform generating integrated circuit, 2 denotes an input circuit of a laser control integrated circuit including a laser drive circuit, and 3 denotes an output circuit of an output circuit 1 for inputting an output current. 2 is the signal wiring to be transmitted.

First, the output circuit 1 in FIG. 7 will be described.

7, 8, and 9 are DACs (digital, analog,
Converters) are connected to switch circuits 4, 5, and 6, respectively. The switch circuits 4, 5, and 6 select a current output node OUT / VCC (power supply potential) node according to the ON / OFF state. The current output node OUT is connected to the signal wiring 3 via an output terminal (not shown).

In the output circuit 1 having the above-described configuration, the switch circuits 4, 5, and 6 connect the variable current sources 7, 8, and 9 to the current output node OUT when turned on, and the variable current sources 7, 8 when turned off.
, 9 to the VCC node. As a result, the output current is 0 when all of the switch circuits 4, 5, and 6 are off, and the output current is on when the switch circuits 4, 5, and 6 are alternatively selected to be on. It becomes the current value of the variable current source connected to the switch circuit in the state.

FIG. 8 shows an example of the waveform of the output current signal of the output circuit 1 of FIG.

When only the switch circuit 4 is turned on, the current value of the variable current source 7 becomes I1. When only the switch circuit 5 is turned on, the current value becomes I2 of the variable current source 8 and only the switch circuit 6 is turned on. In this case, the current value of the variable current source 9 becomes I3.

Next, the input circuit 2 in FIG. 7 will be described.

The current input node IN is connected to the emitter of a common-base transistor 13 biased by a constant voltage source 16, the emitter of which is further connected to a constant current source 15, and the collector of which is connected to a load. The resistor 11 is connected. The constant current source 14 is connected to the emitter of the common base transistor 12 biased by the constant voltage source 16, and the collector is connected to the load resistor 10. Load resistance 10, transistor 12, and constant current source 14
The load resistor 11, transistor 13 and constant current source 15 are connected in parallel with each other between a VCC (power supply potential) node and a GND (ground node). The current values of the constant current sources 14 and 15 are equal, the resistance values of the load resistors 10 and 11 are equal, and the shapes of the transistors 12 and 13 are made equal. Then, the voltage difference between the load resistors 10 and 11 is extracted as an output signal via the signal lines 17 and 18.

In the input circuit 2 having the above configuration, the load resistance
10, 11, transistors 12, 13 and constant current sources 14 and 15 are equal to each other, so when the output current value of output circuit 1 is 0, the voltage drops of load resistors 10 and 11 are equal, and the difference voltage signal is 0V. Become. Assuming that the output current value of the output circuit 1 is I, the voltage drop of the load resistor 11 is increased by the product of the resistance value R of the load resistor 11 and the output current value I. I × load resistance value R is obtained.

The current output interface circuit shown in FIG. 7 shows a case where three switch circuits 4, 5, 6 and three variable current sources 7, 8, 9 are used. The number of switch circuits and the number of variable current sources corresponding to the number of steps (for example, 5) of the light emission level are connected in parallel.

By the way, in order to realize a high recording density on a recording medium, the current change of the output current must be sharp, but in an actual device, the inductance of the signal transmission line such as the signal wiring 3 between the input and the output is reduced. There is a problem that there are components and parasitic capacitance, which become a filter, and that even if the switch circuit of the output circuit 1 is operated at a high speed, the current change is limited by the impedance of the transmission line.

FIG. 9 shows a model of a signal transmission line in the current output interface circuit of FIG.

FIGS. 10A and 10B show an example of an output current signal waveform and an input current signal waveform in the current output interface circuit of FIG.

In FIG. 9, the inductance 21 of the signal wiring 3 is about 1 nH per 1 mm, the inductance component of the signal wiring 3 is 5 nH (corresponding to 5 mm), and the parasitic capacitance 19 of the input part and the parasitic capacitance 20 of the output part are each 20 pF. Figure 1
For a steep output current signal waveform as shown in FIG. 10A, a gradual input current signal waveform as shown in FIG.

The impedance of the transmission line can be reduced by reducing the length of the signal line 3, but this is subject to mounting restrictions.

[0022]

The conventional current output interface circuit as described above has a single-end type circuit configuration in which the output current is transferred by one signal wiring. , To reduce the effects of noise entering from the transmission path,
Consider making an AC output signal differential (output current is a differential current signal and input current is a differential signal).

Here, in the current output interface circuit shown in FIG. 7, all of the currents of the variable current sources 7, 8, and 9, which do not flow as output currents, flow to the VCC node. The circuit shown in FIG. 11 is conceivable if it is attempted to simply make a difference by paying attention to the fact that the current flowing is in the opposite phase to the output current.

FIG. 11 shows a circuit plan in the case of simply trying to make the current output interface circuit shown in FIG. 7 differential. This circuit differs from the circuit shown in FIG.
The other selected node of each of the switch circuits 4, 5, and 6 of the output circuit 1 is connected not to the VCC node but to the signal line 22 via the output node OUT '. This signal wiring 22 is connected to the emitter of the NPN transistor 12 via the input IN ′ of the input circuit 2. The other parts are denoted by the same reference numerals corresponding to the same parts in FIG.

In FIG. 11, I1 represents the current value of the variable current source 7, I2 represents the current value of the variable current source 8, and I3 represents the current value of the variable current source 9. Now, when the current of the variable current source (the output current of one signal wiring 3) connected to the switch circuit that is turned on at time t is represented by It, It is one of the values of I1, I2, and I3. Take. The other signal wiring 22 at time t
Is I1 + I2 + I3-It.

Therefore, the value of the difference current between the pair of signal wirings 3 and 22 is 2 * It- (I1 + I2 + I3). Here, I1 + I2 + I3 is the sum of the currents of the variable current sources 7, 8, and 9, and
As long as the current settings of 7, 8, and 9 are fixed, they will be constant.
Therefore, the AC amplitude of the difference current signal is 2 * It, which is twice the amplitude of the output signal of the conventional example.

However, as described above, I1 + I2 + I3 is added to the difference current signal as a DC component. For example, when the switch circuits 7, 8, and 9 are all off, the difference current signal is such that the output current of one signal wiring 3 is 0, while the output current 22 of the other signal wiring 22 is I1 Since it is + I2 + I3, the value of the difference current signal becomes-(I1 + I2 + I3) and does not become zero. In other words, the circuit shown in FIG. 11 cannot realize the differential operation.

The present invention has been made in order to solve the above-mentioned problems. An AC output current signal is used as a differential signal, and a DC offset (DC offset) when the current value is 0 is eliminated. It is an object of the present invention to provide a current output interface circuit which can be hardly affected by the impedance of a transmission path between input / output circuits and the influence of noise mixed in from the transmission path.

[0029]

A current output interface circuit according to the present invention is provided in correspondence with a plurality of first current sources and the plurality of first current sources, and each of the on / off states is controlled by switching. A plurality of switch circuits for connecting a corresponding first current source to a first node / a second node corresponding to an on / off state, and at least one of the first node and the second node; And the difference current signal between the first output node and the second output node is substantially zero when each of the switch circuits is off.
And a correction current source through which a DC correction current flows.

An optical disk drive according to the present invention comprises: a light emission power control device for controlling the light emission power of a semiconductor laser; and a laser drive device for emitting a semiconductor laser based on a signal from the light emission power control device. The control device has a current output interface circuit according to any one of claims 1 to 6 as an output circuit, and the laser driving device has a current difference between the first output node and the second output node. It is characterized by having a differential input type input circuit for inputting a signal.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment ... Current Output Interface Circuit> FIG. 1 shows a case where a current output interface circuit according to a first embodiment of the present invention is used in a laser emission control circuit of an optical disk device. ing.

In FIG. 1, reference numeral 31 denotes an output circuit of a recording waveform generating integrated circuit, 32 denotes an input circuit of a laser control integrated circuit including a laser drive circuit, and 33 and 34 connect between the two integrated circuits. This is the signal wiring.

First, the output circuit 31 in FIG. 1 will be described.

Reference numerals 38, 39, 40, 41, 42, and 43 denote variable current sources that can be controlled by using a DAC or the like, and the variable current sources 38 and 39 are controlled to have the same current value. Have been.
Similarly, the variable current sources 40 and 41 and the variable current sources 42 and 43 are controlled to have the same current value, respectively.

The variable current sources 38, 40 and 42 are connected to the switch circuits 35, 36 and 37, respectively. The switch circuits 35, 36 and 37 are connected to the first /
Current output node OUT1 / second current output node OUT2. The first current output node OUT1 is connected to a first signal line 33 via an output terminal (not shown) of the integrated circuit, and the second current output node OUT2 is connected to an output terminal of the integrated circuit (not shown). ) Is connected to the second signal wiring 34.

The variable current sources 39, 41, and 43 for DC correction are connected between the first output node OUT1 and the ground node, respectively. Here, the variable current sources 38 and 39 and the variable current source 40
The variable current sources 41 and 43 are controlled so as to have the same current direction.

In the output circuit 31 having the above configuration, the switch circuits 35, 36, 37 connect the variable current sources 38, 40, 42 to the first signal line 33 via the first current output node OUT1 when turned on. In the off state, the variable current sources 38, 40, and 42 are connected to the second signal line 34 via the second current output node OUT2. The variable current sources 39, 41, and 43 are connected to the first current output node OUT1.
, So that the output current always flows through the first signal wiring 33.

Here, the current values of the variable current sources 38 and 39 are represented by (I1 /
2) Set the current values of the variable current sources 40 and 41 to (I2 / 2)
The current values of 2, 43 are represented by (I3 / 2). Switch circuit 35, 3
The current of the variable current source connected to the switch circuit that is on at the time t when the switches 6 and 37 are alternatively selected to be on is represented by (It / 2).

When the switch circuits 35, 36, and 37 are all off, the value of the current flowing through the first signal wiring 33 is
Since (I1 + I2 + I3) / 2, and the value of the current flowing through the second signal wiring 34 is (I1 + I2 + I3) / 2, the value of the difference current signal is zero.

On the other hand, at time t, the value of the current flowing through the first signal wiring 33 is (I1 + I2 + I3 + It) / 2,
The value of the current flowing through the second signal wiring 34 is (I1 + I2 + I3-It) / 2
Therefore, the value of the difference current signal is (I1 + I2 + I3 + It) / 2- (I1 + I2
+ I3-It) / 2 = It.

This value corresponds to the value of the conventional output circuit 1 shown in FIG.
Equal to the current signal value of From this, the output circuit of FIG.
It can be seen that 31 differentials have been realized.

The variable current sources 38, 39, 40, 41, 42, 43
Is equal to I1 + I2 + I3, and this value is equal to the sum of the current values of the variable current sources 7, 8, and 9 of the conventional output circuit 1 shown in FIG.

Next, the input circuit 32 in FIG. 1 will be described.

The first current input node IN1 to which the first signal wiring 33 is connected is connected to the emitter of the common base transistor 47 biased by the constant voltage source 50. A constant current source 49 is connected, and a load resistor 45 is connected to its collector.
The second current input node IN2 to which the second signal wiring 34 is connected is connected to the emitter of the common base transistor 46 biased by the constant voltage source 16, and the emitter of the transistor 46 is further connected to the constant current source IN2. A current source 48 is connected, and a load resistor 44 is connected to its collector. A load resistor 44, a transistor 46 and a constant current source 48,
Load resistance 45, transistor 47 and constant current source 49 are VC
They are connected in parallel with each other between the C (power supply potential) node and GND (ground node). The current values of the constant current sources 48 and 49 are equal, the resistance values of the load resistors 44 and 45 are equal,
The shapes of 46 and 47 are made equal. And load resistance
Signal line 5 uses the difference between the voltage drops of 44 and 45 as the differential voltage output signal.
Take out via 1,52.

In the input circuit 32 having the above configuration, the load resistance
44 and 45, transistors 46 and 47, and constant current sources 48 and 49 are equal to each other, so that the current value of the first signal
When the current value of the signal wiring 34 is equal (when the value of the difference current signal of the output circuit 31 is 0), the voltage drops of the load resistors 44 and 45 are equal, and the difference voltage output signal is 0V.

When the value of the difference current signal between the first signal wire 33 and the second signal wire 34 is It, the difference voltage output signal
× Load resistance value R is obtained.

At time t, the first signal wiring 33
The value of the output current flowing through is (I1 + I2 + I3 + It) / 2,
The value of the output current flowing through the signal wiring 34 is (I1 + I2 + I3-It) / 2
Therefore, the input circuit 32 must operate even when there is a current input of (I1 + I2 + I3 + It) / 2. That is, the input circuit 32 uses the current input (I1 + I2 + I3 + It) / 2 to
It is necessary to set the value of the load resistor 45 small so that the transistor 47 does not saturate due to the voltage drop occurring at 45. Therefore, there is a restriction that the amplitude of the differential voltage output signal of the input circuit 32 cannot be extremely increased.

As described above, according to the current output interface circuit shown in FIG. 1, the output signal is differentiated, and the differential signal transmission lines (signal lines 33 and 34) are arranged adjacent to each other, whereby the transmission line The mutual inductance makes it possible to reduce the self-inductance of the transmission line. Also,
The noise mixed in from the transmission path is added to both transmission paths as in-phase noise, and therefore cancel each other as differential signals. For this reason, by making the output signal differential, noise mixed in from the transmission path can be removed.

Further, according to the current output interface circuit shown in FIG. 1, the output signal is differentiated, so that the current values of the variable current sources 38, 40, and 42 are changed to the conventional output circuit shown in FIG.
The same signal output as that of the conventional output circuit 1 shown in FIG.
9, 41 and 43 are added, but the conventional output circuit 1 shown in FIG.
And the power consumption does not change.

In the above embodiment, the plurality of switch circuits 35, 36, and 37 correspond to recording waveforms that control the level of the emission power of the semiconductor laser at the time of writing in the optical disk device to a multilevel value over time. Selectively controlled, multiple sets of variable current sources (38, 39), (40, 41), (42, 43)
An example has been described in which the current value differs according to the multi-valued level of the light emission power and the current value is variable in order to control the light emission power of the laser according to the track position of the optical disc to be recorded.

However, the current output interface circuit of the present invention is applicable to a case where a fixed current source is used instead of a variable current source. In this case, a plurality of switch circuits are selectively controlled by, for example, a signal obtained by decoding a binary code digital signal, and as a plurality of sets of current sources,
If the current value is set to be different according to the output level obtained by converting the digital signal into analog, the D / A
It is possible to realize a current output interface circuit that outputs a converted output as a differential current. Further, the current values of a plurality of sets of current sources (variable current sources or fixed current sources) are set to be the same, and the number of switch circuits to be turned on among the plurality of switch circuits is switched to obtain a multi-valued current output level. It is also possible.

<Second Embodiment: Current Output Interface Circuit> In the first embodiment, as described above, the input circuit 32 is loaded by the current input (I1 + I2 + I3 + It) / 2. It is necessary to set the value of the load resistor 45 small so that the transistor 47 does not saturate due to the voltage drop generated in the resistor 45, and there is a restriction that the amplitude of the differential voltage output signal of the input circuit 32 cannot be extremely increased.

This restriction is particularly caused by an increase in the number of current setting levels of the output circuit 31 and an increase in the number of variable current sources, whereby the difference between the current value of one variable current source and the sum of the current values of the variable current sources is increased. And the problem that the voltage amplitude can no longer be obtained.

A second embodiment for solving this problem will be described below.

FIG. 2 shows a current output interface circuit according to a second embodiment of the present invention.

In FIG. 2, reference numeral 61 denotes an output circuit of a recording waveform generating integrated circuit, 62 denotes an input circuit of a laser control integrated circuit including a laser drive circuit, and 63 and 64 connect between the two integrated circuits. These are a first signal wiring and a second signal wiring.

The current output interface circuit of FIG.
Compared with the current output interface circuit described above with reference to FIG. 1, the variable current sources 69 and 7 for DC component correction of the output circuit 61 are provided.
1, 73 are different, others are the same.

That is, in the output circuit 61, 68, 69, 70,
Reference numerals 71, 72, and 73 denote variable current sources that can be controlled by using a DAC or the like, and the variable current sources 68 and 69 and the variable current sources 70
And 71, and the variable current sources 72 and 73 are controlled to have the same current value, respectively.

The variable current sources 68, 70, 72 are connected to switch circuits 65, 66, 67, respectively. The switch circuits 65, 66, 67 select the first current output node OUT1 / the second current output node OUT2 according to the ON / OFF state. The first current output node OUT1 is connected to a first signal line 63 via an output terminal (not shown) of the integrated circuit, and the second current output node OUT2 is connected to an output terminal of the integrated circuit (not shown). ) Is connected to the second signal wiring 64.

The variable current sources 69, 71, and 73 for DC component correction are connected between the VCC node and the second output node OUT2, respectively. Here, the variable current sources 68, 70, 72 are output circuits
Output current flows in the direction of drawing current to 61,
The variable current sources 69, 71, and 73 for DC component correction supply an output current in the direction in which current flows from the output circuit 61, and the variable current sources 68, 70, and 72 and the variable current source 69 for DC component correction. , 71 and 73 have opposite polarities (current directions are opposite).

In the output circuit 61 having the above configuration, the switch circuits 65, 66, 67 connect the variable current sources 68, 70, 72 to the first signal wiring 63 via the first current output node OUT1 when turned on. In the off state, the variable current sources 68, 70 and 72 are connected to the second signal wiring 64 via the second current output node OUT2. Then, the variable current sources 69, 71, and 73 connected to the second current output node OUT2 always supply the output current to the second signal wiring 64, respectively.

Here, the current values of the variable current sources 68 and 69 are represented by (I1 /
2) Set the current values of the variable current sources 70 and 71 to (I2 / 2)
The current values of 2, 73 are represented by (I3 / 2). Switch circuit 65, 6
The current of the variable current source connected to the switch circuit that is on at the time t at which the switches 6 and 67 are alternatively selected to be in the on state is represented by It / 2.

When the switch circuits 65, 66, and 67 are all off, the value of the current flowing through the first signal wiring 63 is
It becomes 0, and the value of the current flowing through the second signal wiring 64 becomes 0, so that the value of the difference current signal is 0.

On the other hand, at time t, the value of the current flowing through the first signal wiring 63 is It / 2, and the value of the current flowing through the second signal wiring 64 is (I1 + I2 + I3-It- I1-I2-I3) / 2 = -It
/ 2, so the value of the difference current signal is It.

This value is equal to the current signal value of the output circuit 31 shown in FIG. This indicates that the output circuit 61 of FIG. 2 is realized as a differential circuit.

The sum of the current values of the variable current sources 68, 70, and 72 (current consumption of the output circuit 61) is (I1 + I2 + I3) / 2, which is the value of the conventional output shown in FIG. Variable current source 7 for circuit 1
, 8, and 9 of the current value.

On the other hand, the input circuit 62 in FIG. 2 has the same circuit configuration as the input circuit 32 in FIG. 1, but is assigned a different reference numeral from that in FIG. That is, 80 is a constant voltage source, 76 and 77 are grounded base transistors, 78 and 79 are constant current sources, respectively, and 74 and 75 are load resistors. Here, the constant current sources 78 and 79 have the same current value, the load resistors 74 and 75 have the same resistance value, and the transistors 76 and 77 have the same shape. Then, the voltage difference between the load resistors 74 and 75 is
As an output signal.

As described above, the current output interface circuit of FIG. 2 is different from the input circuit 32 of FIG. 1 in that when the switch circuits 65, 66, and 67 are selectively turned on, the first The output current values of the signal wiring 63 and the second signal wiring 64 are (It / 2) and (-It / 2), and a current larger than the amplitude of the difference current does not flow. There is no problem that the amplitude of the signal cannot be increased.

However, the output current of the second signal wiring 64 is (-It
/ 2). That is, the second signal wiring 64
The output current flows in the direction in which the current flows from the output circuit 61 to the input circuit 62. Therefore, the current value of the current source 78 of the input circuit 62 needs to be set to a value sufficiently larger than It / 2.

<Third Embodiment: Current Output Interface Circuit> In the second embodiment, as described above, the variable current sources 68 and 69, 70 and 71, and 72 and 73 have the same current value, respectively. However, the direction of the flowing current is opposite, and a current source cannot be formed with the same circuit configuration. If the current value of the variable current source 68 is I1 / 2,
Assuming that the current value of 69 is (−I1 / 2) + ΔI1, the value of the difference current is It−ΔI1, and this error appears as an offset of the difference current.

A third embodiment for solving this problem will be described below.

FIG. 3 shows a current output interface circuit according to a third embodiment of the present invention.

In FIG. 3, reference numeral 91 denotes an output circuit of a recording waveform generating integrated circuit, 92 denotes an input circuit of a laser control integrated circuit including a laser drive circuit, and 93 and 94 connect between the two integrated circuits. These are a first signal wiring and a second signal wiring.

The current output interface circuit of FIG.
The variable current sources 98 to 109 of the output circuit 91 are different from those of the current output interface circuit described with reference to FIG.
Others are the same.

That is, in the output circuit 91, 98 to 109 are DA
A variable current source that can control the current value created by using C, etc., and includes variable current sources 98, 99, 104, 105 and a variable current source.
100, 101, 106, 107 and variable current sources 102, 103
, 108 and 109 are controlled so as to have the same current value.

The variable current sources 98, 100, and 102 are connected to switch circuits 95, 96, and 97, respectively. The switch circuits 95, 96, and 97 are connected to the first current output node OUT1 / second current output node OUT2 in accordance with the on / off state.
Select The first current output node OUT1 is connected to a first signal line 93 via an output terminal (not shown) of the integrated circuit, and the second current output node OUT2 is connected to an output terminal of the integrated circuit (not shown). ) Is connected to the second signal wiring 94.

Variable current sources 99, 101, 103 for DC component correction
Are respectively connected between the first current output node OUT1 and the ground node, and the variable current sources 104,
106 and 108 are respectively connected between the VCC node and the second current output node OUT2, and are connected to the variable current source 10 for DC component correction.
5, 107 and 109 are respectively connected between the VCC node and the first current output node OUT1.

Here, the variable current sources 98 to 103 are connected to the output circuit 91.
The variable current sources 104 to 109 supply an output current in a direction in which current flows from the output circuit 91. The variable current sources 98 to 103 and the variable current source 104 The polarity is opposite to that of ~ 109.

In the output circuit 91 having the above configuration, the switch circuits 95, 96, and 97 are turned on when the variable current sources 98, 100, and 102 are turned on.
To the first signal line 93 via the first current output node OUT1.
The variable current sources 98, 100, and 102 are connected to the second signal wiring 94 via the second current output node OUT2 when turned off. The variable current sources 99, 101, and 103 connected to the first current output node OUT1 always draw the output current from the first signal line 93, and are connected to the first current output node OUT1. Variable current sources 105, 107, 109
Always output the output current to the first signal wiring 93, and the variable current sources 104, 106, and 108 connected to the second current output node OUT2 always output the output current to the second signal wiring 93, respectively.
Out to the signal wiring 94.

Here, the current values of the variable current sources 98, 99, 104 and 105 are (I1 / 2), the current values of the variable current sources 100, 101, 106 and 107 are (I2 / 2), , 103, 108, and 109 are represented by (I3 / 2). The current of the variable current source connected to the switch circuit that is on at the time t when the switch circuits 95, 96, and 97 are alternatively selected to be in the on state is
(It / 2).

When the switch circuits 95, 96, and 97 are all off, the value of the current flowing through the first signal wiring 93 is
It becomes 0, and the value of the current flowing through the second signal wiring 94 becomes 0, so that the value of the difference current signal is 0.

On the other hand, at time t, the value of the current flowing through the first signal wiring 93 is (I1 + I2 + I3 + It-I1-I2-I3) /
2 = It / 2, and the value of the current flowing through the second signal wiring 94 is (I
Since 1 + I2 + I3-It-I1-I2-I3) / 2 = -It / 2, the value of the difference current signal is It.

This value corresponds to the output circuit 31 shown in FIG.
3 is equal to the current signal value of the output circuit 61, and it can be seen that the output circuit 91 of FIG.

The variable current sources 98, 99, 100, 101, 10
The sum of the current values of 2 and 103 is I1 + I2 + I3.
The variable current sources 7, 8, 9 of the conventional output circuit 1 shown in FIG.
Equal to the sum of the current values of

Therefore, the current consumption of the output circuit 91 shown in FIG. 3 is substantially equal to the current consumption of the conventional output circuit 1 shown in FIG. 7, similarly to the output circuit 31 shown in FIG.

On the other hand, the input circuit 92 in FIG. 3 has the same circuit configuration as the input circuit 32 in FIG. 1, but is assigned a different reference numeral from that in FIG. That is, 116 is a constant voltage source, 112 and 11
3 is the common base transistor, 114 and 115 respectively
Is a constant current source, and 110 and 111 are load resistors. Here, the current values of the constant current sources 114 and 115 are equal, the resistance values of the load resistors 110 and 111 are equal,
And 113 are equally shaped. And load resistance
Signal lines 117 and 118 use the voltage difference between 110 and 111 as an output signal.
Have taken out through.

As described above, when the switch circuits 95, 96, and 97 are selectively turned on, the current output interface circuit of FIG.
The value of the output current of the signal wiring 94 is (It / 2) and (-It / 2). Similar to the input circuit 62 in FIG. 2, a current larger than the amplitude of the difference current does not flow. There is no problem that the amplitude of the differential voltage output signal cannot be increased.

However, the output current of the second signal wiring 94 is (-It
/ 2). That is, the second signal wiring 94
The output current flows in the direction in which the current flows from the output circuit 91 to the input circuit 92. For this reason, the current value of the current source 114 of the input circuit 92 needs to be set to a value sufficiently larger than It / 2.

Further, the output circuit 91 of FIG.
Even if the current values of 98 and 104 and 99 and 105 are not exactly equal, they do not appear as errors in the difference current signal. Hereinafter, this will be described.

The variable current sources 98 and 99 and the variable current source 104
And 105 can be composed of current sources of exactly the same structure,
The current values can be substantially the same. Now, there is an error current ΔI1 in each of the currents of the variable current sources 104 and 105, and the current values of the variable current sources 98 and 99 are (I1 / 2),
Assuming that the current values of 104 and 105 are − (I1 / 2) + ΔI1, the output current values of the first signal wiring 93 and the second signal wiring 94 are (It / 2−ΔI1), respectively. (-It / 2-ΔI1), and the value of the difference current is It. That is, the variable current source 104 and
Since the error current ΔI1 of 105 cancels each other, it does not become an error of the difference current. Therefore, the output circuit 91 of FIG.
Does not cause the problem of current error as in the output circuit 61 of FIG.

<Specific Example of Third Embodiment> FIG. 4 shows a specific example in the case where the current output interface circuit shown in FIG. 3 is configured using bipolar transistors.

That is, in FIG. 4, reference numeral 121 denotes an output circuit;
2 is an input circuit, 123 is a first signal wiring, and 124 is a second signal wiring. For simplification of description, the output circuit 121 has two sets of a combination circuit of a variable current source and a switch circuit (FIG. 3 is different).

First, one set of the combination circuit of the variable current source and the switch circuit in the output circuit 121 will be described.

A circuit comprising NPN transistors 126, 127, 134, 137, 139 and resistors 128, 135, 138, 140 forms a first current mirror circuit. The current value of the first current mirror circuit is determined by the variable current source 125.
The NPN transistor 127 is a transistor for correcting the base current of the first current mirror circuit.

The circuit composed of the PNP transistors 141, 142, 144, 146 and the resistors 143, 145, 147 forms a second current mirror circuit, and the current value of the second current mirror circuit is determined by the collector current of the NPN transistor 139. The PNP transistor 142 is a transistor for correcting the base current of the second current mirror circuit.

As described above, the variable current source for current output and the DC
A variable current source for minute correction is formed by a current mirror circuit, and two current mirror circuits for passing currents of opposite polarities (positive and negative) are used.

The emitters of the NPN transistors 131 and 132 constituting the comparator circuit for the switch circuit are connected to the NPN transistors 131 and 132, respectively.
The collector of the transistor 134 is connected to each of the second signal wiring 124 and the first
Connected to the signal wiring 123. The bases of the transistors 131 and 132 are connected to differential signal sources (input signal sources) 129 and 130, respectively.
133 provides the input bias.

When the voltage V1 of the differential signal source 129 is
When the voltage is larger than the voltage V2 of the differential signal source 130, the collector current of the NPN transistor 134 flows through the NPN transistor 131, and the voltage V1 of the differential signal source 129 becomes the voltage V2 of the differential signal source 130.
If less, the collector current of the NPN transistor flows through the NPN transistor 132.

The collector of the transistor 137 is connected to the emitter of an NPN transistor 136, and the base of the transistor 136 is connected to the voltage source 133. The collector of the transistor 136 is connected to the first signal line 123.

The collectors of the transistors 144 and 146 of the second current mirror circuit are connected to the first signal line 123 and the second signal line 124, respectively. Here, the current value of the variable current source 125 is defined as I1.

The transistors 126, 134, 137, 139 of the first current mirror circuit have exactly the same shape, and the resistors 128,
When the resistance values of 135, 138, 140 are all equal, the collector currents of the transistors 126, 134, 137, 139 are all equal, and the current value is (I1-Ib1). Here, Ib1 is the base current of the transistor 127 for correcting the base current.

The transistors 141, 144, 146 of the second current mirror circuit have exactly the same shape, and the resistors 143, 14
If all 5,147 resistances are equal, the transistor
The collector currents of the transistors 141, 144, and 146 are all equal, and the current value is calculated from the collector current of the transistor 139 to the base current Ib2 of the transistor 142 for correcting the base current.
Becomes-(I1-Ib1-Ib2). Here, the reason why the current value is negative is that the current flows in the first current mirror and the second current mirror in opposite directions.

First, when the voltage V1 of the differential signal source 129 is higher than the voltage V2 of the differential signal source 130, the current flowing through the first signal wiring 123, the current flowing through the second signal wiring 124, and the first A differential output current flowing between the signal wiring 123 and the second signal wiring 124 will be considered.

The voltage V1 of the differential signal source 129 is
Is higher than the voltage V2, the collector current (current value I1-Ib1) of the transistor 134 flows through the transistor 131. The collector current of transistor 131 is
Since the base current Ib3 of 131 decreases, its current value becomes (I1-Ib1-Ib3). The value of the collector current of the transistor 146 is-(I1-Ib1-Ib2). Where Ib
2 is a base current for correcting the base current. As a result,
The value of the current flowing through the second signal wiring 124 is determined by the transistor
It is the sum of the collector current of 131 and the collector current of the transistor 146, and (I1-Ib1-Ib3)-(I1-Ib1-Ib2) = (-Ib3 + Ib2).

On the other hand, the current flowing through the first signal wiring 123 is determined by the collector current of the transistor 132 and the transistor
It is the sum of the collector current of 136 and the collector current of transistor 144. The voltage V1 of the differential signal source 129 is
When the voltage is larger than the voltage V2 of 0, no current flows through the transistor 132, so that the collector current of the transistor 132 is 0. If the transistor 136 whose base is connected to the bias power supply 133 has the same shape as the transistors 131 and 132, the base current of the transistor 136 becomes equal to the base current Ib3 of the transistor 131, and the value of the collector current of the transistor 136 becomes ( I1-Ib1-Ib3).
The collector current of the transistor 144 is equal to the collector current of the transistor 146, and the current value is-(I1-Ib1
-Ib2). As a result, the value of the current flowing through the first signal wiring 123 is (I1-Ib1-Ib3)-(I1-Ib1-Ib2) = (-Ib3 + ib2). Therefore, the value of the differential output current flowing between the signal lines 123 and 124 is (-Ib3 + Ib2)-(-Ib3 + Ib2) = 0.

Next, consider the case where the voltage V1 of the differential signal source 129 is smaller than the voltage V2 of the differential signal source 130.

At this time, the collector current (current value I1-Ib1) of the transistor 134 flows through the transistor 132. The value of the collector current of the transistor 132 is
This is the amount obtained by subtracting the base current of the transistor 132 from the collector current of No. 4, and this base current is equal to the base current Ib3 of the transistor 131 described above. Therefore, the value of the collector current of the transistor 132 is (I1-Ib1-Ib3). Further, the collector current of the transistor 136 becomes a constant amount (I1-Ib1-Ib3) irrespective of the voltage V1 of the differential signal source 129 and the voltage V2 of the differential signal source. In addition, transistor 144
The collector current of the differential signal source 129 and the voltage V2 of the differential signal source 130 are also constant, regardless of the voltage V1 of the differential signal source 130.
Becomes As a result, the value of the current flowing through the first signal wiring 123 is (I1-Ib1-Ib3) + (I1-Ib1-Ib3)-(I1-Ib1-IB2) = I1-Ib
1-2 × Ib3 + Ib2.

On the other hand, the collector current of the transistor 131 is
0, and the collector current of the transistor 144 becomes a constant amount-(I1-Ib1-Ib2) irrespective of the voltage V1 of the differential signal source 129 and the voltage V2 of the differential signal source. As a result, the value of the current flowing through the second signal wiring 124 is-(I1-Ib1-Ib2). Therefore, the value of the differential output current flowing between the signal wirings 123 and 124 is (I1-Ib1-2 × Ib3 + Ib2) + (I1-Ib1-Ib2) = 2 ×
(I1-Ib3).

The remaining one set (two sets) of the combination circuit (two sets) of the variable current source and the switch circuit in the output circuit 121 includes a current mirror circuit composed of NPN transistors 149, 150, 157, 160, 162 and resistors 151, 158, 161, 164.
PNP transistors 164,165,167,169 and resistors 166,168,
170, a current mirror circuit, NPN transistors 154 and 155 constituting a comparator circuit, a variable current source 148,
Differential signal sources 152,153, NPN transistor 159, current source 15
6) has the same configuration as the above-mentioned one set, and performs the same operation independently.

Here, the current value of the variable current source 148 is I2, the signal voltages of the differential signal sources 152 and 153 are V3 and V4, respectively, the base current of the transistor 150 is Ib4, the base current of the transistor 165 is Ib5, and the transistor 154 Is expressed by Ib6, the output current value under each input condition is as shown in the following table.

(1) Input condition V1> V2 and V3> V4 Current of first signal wiring 123 -Ib3 + Ib2-Ib6 + Ib5 Current of second signal wiring 124 -Ib3 + Ib2-Ib6 + Ib5 Difference current 0 (2) Input condition V1 <V2 and V3> V4 Current of the first signal wiring 123 I1-Ib1-2Ib3 + Ib2-Ib6 + Ib
5 Current of the second signal wiring 124 -I1 + Ib1 + Ib2-Ib6 + Ib5 Difference current 2 × (I1-Ib3) (3) Input condition V1> V2 and V3 <V4 Current of the first signal wiring 123 -Ib3 + Ib2 + I2-Ib4-2Ib6-I
b5 Current of second signal wiring 124 -Ib3 + Ib2-I2 + Ib4 + Ib5 Difference current 2 × (I2-Ib6) Next, the input circuit 122 in FIG. 4 will be described.

The first input node IN1 to which the first signal line 123 is connected is connected to the emitter of the base-grounded NPN transistor 174, and the second input node IN2 to which the second signal line 124 is connected is the base. Grounded NPN transistor 17
3 connected to the emitter.

The bases of the transistors 174 and 173 are commonly connected to a bias voltage source 179. The collectors of the transistors 174 and 173 are connected to the VCC node via load resistors 172 and 171 respectively. The emitters of the transistors 174 and 173 are connected to the collectors of NPN transistors 177 and 175, respectively.

A circuit including NPN transistors 181, 182, 177, 175 and resistors 183, 178, 176 forms a third current mirror circuit.
Is determined by In this case, the values of the collector currents of the transistors 177 and 175 are set to be sufficiently larger than the maximum of the current value of the first signal wiring 123 and the current value of the second signal wiring 124, respectively. I have.

Here, consider the case of the input condition (1) described above.

The transistor of the third current mirror circuit
The values of each collector current of 177,175 are equal. The current value of the first signal wiring 123 and the current value of the second signal wiring 124 are -Ib3 + Ib2-Ib6 + Ib5, respectively, which are equal. Therefore, the collector current of transistor 174 and the collector current of transistor 173 have the same current value. As a result, the voltage drop of the load resistor 172 and the voltage drop of the load resistor 171 become equal, and the differential voltage output becomes zero.

On the other hand, in the case of the input conditions (2) and (3) described above, the first signal line 123 and the second signal line
A difference occurs between the collector current of the transistor 173 and the collector current of the transistor 174 by the current difference of 124, and a value obtained by multiplying this current difference by the resistance value of the load resistor 171 or 172 appears as a differential voltage output. .

<Fourth Embodiment ... Laser Emission Control Circuit of Optical Disk Apparatus> FIG. 5 is a block diagram schematically showing a part of an optical disk apparatus according to a fourth embodiment of the present invention.

In FIG. 5, reference numeral 201 denotes an integrated recording waveform generation circuit (light emission power control device) for outputting a multi-valued control current Ic intensity-modulated to represent digital information, and 202 denotes a control current Ic. An integrated semiconductor laser control circuit (laser driving device) 203, a semiconductor laser connected to the semiconductor laser control circuit 202, and a photodetector 204 for detecting the output light of the semiconductor laser 203.

As the output circuit 205 of the recording waveform generating circuit 201, a differential output type output circuit as shown in the first to third embodiments and its specific example is used to output a quinary differential current signal. What is constituted so that it may be used.
Also, as the input circuit of the semiconductor laser control circuit 202, the differential input type input circuit 206 as shown in the first to third embodiments and its specific examples is used.

In the semiconductor laser control circuit 202, a differential current signal (intensity modulated control current signal) input from the recording waveform generation circuit 201 to the input terminal is input to the input circuit 20.
6 converts it to a differential voltage signal. This differential voltage signal becomes a drive control signal for a laser drive circuit 208 via a control amplifier circuit 207 and a level shift (not shown).
The laser drive circuit 208 supplies a drive current to the semiconductor laser 203.

The control amplifier circuit 207 is composed of a differential variable amplifier comprising a gain controllable operational amplifier circuit (Gain Control Amplifier; GCA) 209 and a control amplifier 210 having desired frequency characteristics connected in series. Also, the control amplifier circuit
The laser drive control signal circuit output from 207 is input to, for example, the base of an NPN transistor 208. The collector of the drive transistor 208 is connected to the semiconductor laser 203 via an external terminal LDC, and the emitter is connected to the external. Grounded via terminal RE and resistor 211.

The semiconductor laser control circuit 202 has a wide band front automatic power control (APC).
Control) method is adopted. In this method, when irradiating the optical disc 212 with the output light of the semiconductor laser 203,
The light actually irradiated onto the optical disk 212 (the semiconductor laser 20)
(A part of the front light 3) is guided to the photodetector 204 and detected, and the output signal of the semiconductor laser 203 is controlled using the detection signal. Can be suppressed. At this time, an error signal corresponding to the difference between the detection signal of the photodetector 204 and the laser drive control signal is generated by the control amplifier (error detection circuit) 207, and based on the error signal, the inverted input node (−) of the GCA 209 is generated. ) Is equal to the voltage level of the non-inverting input node (+).
3 constitutes a feedback control system that performs negative feedback control on the drive current.

On the other hand, the semiconductor laser 203, the monitor photodetector 204, the collimator lens 213, the compound prism 214, the collective prism 215, the galvanomirror 216, the reproduction hologram element 217, the reproduction light detector 218, etc. are fixed. The optical unit 219 is provided.

When data is written to the optical disk 212, the semiconductor laser 203 emits a laser beam according to the control current Ic. This output beam is applied to the collimator lens 21
3. The light is guided to the moving optical head 220 through the compound prism 214 and the galvanometer mirror 216. The moving optical head 220 is mounted on an optical pickup, and can move linearly in the radial direction of an optical disk 212 which is set in an optical disk device and rotates.

A part of the output light from the semiconductor laser 203 is separated by the compound prism 214 and input to the photodetector 204 via the collective prism 215. Photodetector 204
Is connected to a PDA terminal, and the monitor current of the photodetector 204 is fed back to the GCA 209 through the PDA terminal, so that the output light of the semiconductor laser 203 corresponds to a control current signal (modulation signal current). The light intensity is modulated in proportion to the differential voltage signal. Note that the temperature sensor
221 detects the temperature of the optical disk 212 irradiated with the laser beam and supplies a detection signal to the recording waveform generation circuit 201.

When reproducing information recorded on the optical disk 212, the semiconductor laser 203 outputs a laser beam having a light intensity lower than that at the time of recording as a reading beam. Also in this case, the read beam is transmitted to the optical unit 21.
The light is guided to the optical disk 212 by the moving optical head 9 and the moving optical head 220. At this time, the reflected light from the optical disk 212 returns from the moving optical head 220 to the optical unit 219, is separated by the composite prism 214, and is condensed on the reproducing photodetector 218 by the reproducing hologram element 217.

The light detecting power of the reproducing light detector 218 is guided to an arithmetic processing circuit 222 comprising a preamplifier and an arithmetic circuit, and a reproduced information signal and a servo signal are separated and generated. The servo signal is guided to a servo circuit 223, and the moving optical head 220
Control.

The reproduction information signal is converted into a binary signal which can be digitally processed and a binarization / PLL circuit 224 for generating a reproduction clock.
After being processed here, the disk controller
225.

The disk controller 225 includes a modulation / demodulation circuit and an error correction circuit, and further includes a controller for controlling the servo circuit 223 and the recording waveform generation circuit 201, a SCSI interface and the like. The disk controller 225 determines the abnormality detection state of the semiconductor laser control circuit 202 and achieves a stable operation of the optical disk device.

The recording waveform generation circuit 201 receives data from the controller 225 through the data bus, and
The control current Ic corresponding to the recording waveform as shown in FIG.
And a register / control circuit (not shown), an overwrite pulse generation circuit (not shown), an output circuit 205, and the like.

The above register / control circuit is shown in FIG.
D corresponding to the powers of Pp, Pw, Pe, Pb, and Pr corresponding to the five levels of the recording waveform shown in FIG.
The / A converter value is set as five register values.
The overwrite pulse generation circuit generates gate signals G1 to G5 corresponding to each of the five levels of the recording waveform based on the read / write signal and the write data from the controller 225.

The output circuit 205 converts, for example, the five register values from the register / control circuit into analog currents, for example, an 8-bit DAC (variable current source).
And a switch circuit for selectively switching the quinary analog current by the gate signals G1 to G5 from the overwrite pulse generation circuit and outputting it as the control current signal IC, the details of which are described above.

Further, the recording waveform generating circuit 201 switches various monitor signals from the semiconductor laser control circuit 202 by a multiplexer (not shown) and supplies them to an A / D converter (not shown) to convert the converted digital signals. To the controller 225 via the data bus.

According to the optical disk device, the current output interface circuit having the characteristics as described in each of the above embodiments is applied to the laser emission control circuit to increase the capacity and speed up data transfer. It is possible to achieve more accurate light intensity modulation and lower noise required for the above.

[0137]

As described above, according to the current output interface circuit of the present invention, the inductance component of the wiring of the transmission path between the input and output circuits is reduced by making the AC output current signal a differential signal. In addition, it is possible to reduce the influence of the impedance of the transmission path and improve the high frequency characteristics. In addition, it is possible to reduce the influence of noise mixed in from the transmission path and remove noise mixed in from the transmission path, thereby improving S / N.

At this time, a DC current source for DC correction is connected to the output current path, and DC offset (DC offset) when the current value of the differential signal is 0 is almost eliminated. Thus, the level of the differential signal can be set in the range of 0 to the maximum value.

Further, by using a current source for correcting a DC component having a polarity opposite to that of the current source of the output current, the value of the output current can be reduced to a current smaller than the amplitude of the difference current, and the input dynamic range is degraded. It can be made differential without doing so.

Further, by connecting a DC current source for correction to each of a pair of output current paths having opposite polarities, a DC error of the difference current can be substantially eliminated.

Further, by applying the current output interface circuit of the present invention to a laser emission control circuit of an optical disk device, it is possible to achieve more accurate light intensity modulation and lower noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a case where a current output interface circuit according to a first embodiment of the present invention is used in a laser emission control circuit of an optical disk device.

FIG. 2 is a circuit diagram showing a current output interface circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a current output interface circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a specific example of the current output interface circuit shown in FIG. 3;

FIG. 5 is a block diagram schematically showing a part of an optical disk device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a waveform of a laser drive control signal during recording on an optical disc and an example of a shape of a recording mark formed on the optical disc by the laser drive control signal.

FIG. 7 is a circuit diagram showing a current output interface circuit used in a laser emission control circuit of a conventional optical disc device.

8 is a diagram illustrating an example of a waveform of an output current signal of the output circuit in FIG. 7;

9 is an equivalent circuit diagram showing a model of a signal transmission line in the current output interface circuit of FIG. 7;

FIG. 10 is a diagram showing an example of an output current signal waveform and an input current signal waveform in the current output interface circuit of FIG. 7;

11 is a circuit diagram showing a circuit plan when the current output interface circuit shown in FIG. 7 is simply made differential.

[Explanation of symbols]

 31 output circuit, 32 input circuit, 33 first signal wiring, 34 second signal wiring, 35, 36, 37 switch circuit, 38, 40, 42 variable current source, 39, 41, 43 ... Variable current source for DC component correction, 44,45 ... Load resistance, 46,47 ... Common base transistor, 48,49 ... Bias current source, 50 ... Bias voltage source, 51,52 ... Difference voltage signal output signal line.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Norio Nakamura, Inventor No. 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Junichi Koike Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa 7F-1 Toshiba Information Systems Corporation F term (reference) 5D119 AA23 BA01 DA01 FA05 HA36 HA68 5F073 EA12 EA29 GA04 GA12 GA24 5H420 NA17 NA34 NB03 NB22 NB36

Claims (9)

[Claims] 1. A plurality of first current sources, and a plurality of first current sources are provided corresponding to the plurality of first current sources, on / off states of which are controlled to be switched, and the corresponding first current sources are turned on / off. A plurality of switch circuits connected to a first node / a second node corresponding to a state; and a plurality of switch circuits connected to at least one of the first node and the second node, wherein each of the switch circuits is in an off state. A current output interface circuit, comprising: a correction current source that supplies a DC correction current so that a difference current signal between the first output node and the second output node becomes substantially zero. . 2. The method according to claim 1, wherein the first integrated circuit is formed as a semiconductor integrated circuit.
Are connected to the first output terminal / second output terminal correspondingly, and the first output terminal / second node
2. The current output interface circuit according to claim 1, wherein a difference current signal between the output terminals is output. 3. The correction current source is provided corresponding to the plurality of first current sources, respectively connected to the first output node, and has the same current as the corresponding first current source. 3. The current output interface circuit according to claim 1, wherein the current output interface circuit includes a plurality of second current sources that supply currents having substantially equal values in directions. 4. The correction current source is provided corresponding to the plurality of first current sources, is connected to the second output node, respectively, and has a current opposite to that of the corresponding first current source. 3. The current output interface circuit according to claim 1, wherein the current output interface circuit comprises a plurality of second current sources through which a current having a value substantially equal to the direction of the current flows. 5. The correction current source is provided corresponding to the plurality of first current sources, respectively connected to the first output node, and has the same current as the corresponding first current source. A plurality of second current sources for passing currents of substantially equal values in directions; provided in correspondence with the plurality of first current sources; respectively connected to the second output node; A plurality of third current sources that allow a current having a value substantially equal to the direction of the current source to flow in the opposite direction; and a plurality of third current sources provided corresponding to the plurality of third current sources, each of which is connected to the first output node. 3. The current output interface circuit according to claim 1, further comprising a plurality of fourth current sources that supply currents of substantially the same value in the same direction as the current of the corresponding third current source. 6. The variable current source according to claim 1, wherein the plurality of first current sources are variable current sources having different current values from each other and capable of controlling each current value. The current output interface circuit according to the paragraph. 7. An emission power control device for controlling emission power of a semiconductor laser, and a laser driving device for emitting a semiconductor laser based on a signal of the emission power control device, wherein the emission power control device is an output circuit. And a current output interface circuit according to any one of claims 1 to 6, wherein the laser driver receives a difference current signal between the first output node and the second output node as an input. An optical disk device having an input circuit of a differential power input type. 8. The optical disk device according to claim 7, wherein the light emission power control device and the laser driving device are formed as separate semiconductor integrated circuits. 9. The switch circuit of the current output interface circuit is selectively controlled in accordance with a recording waveform for temporally controlling the level of light emission power of a semiconductor laser at the time of writing to an optical disk. 9. The optical disk device according to claim 7, wherein: