JP2001188705A - Tag update control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit for reducing a dead cycle at the time of controlling the update of a TAG(tag) memory, and for improving access through-put at the time of updating the TAG memory. SOLUTION: This circuit for controlling the indexing and update of information for a tag memory 100 at the time of controlling a cache is provided with a tag update buffer 2 for buffering the update transaction of the tag memory 100, a tag index buffer 1 for buffering the indexing transaction of the tag memory 100, and an arbitration control circuit 3 having an address comparator for comparing the address of an update transaction in the tag update buffer 2 with the address of an indexing transaction in the tag index buffer 1 for controlling the arbitration of the update transaction in the tag update buffer 2 and the indexing transaction in the tag index buffer 1. When the coincidence of the addresses is detected by the comparator, the update transaction in the tag update buffer 2 is preferentially executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tag update control circuit for controlling a TAG (Tag) memory holding address information and status information of a cache memory to update each information. In a multiprocessor system in which a plurality of processors are provided for each of a plurality of nodes, when accessing a cache memory and a main memory between the nodes, reference to information to a TAG memory in cache control of each node is performed. (Index) relates to a tag update control circuit suitable for use in controlling update.

[0002]

2. Description of the Related Art Referring to FIG.
The operation of indexing and updating information in the memory will be described. FIG. 7 is a timing chart showing a sequence from a TAG (tag) index operation to a TAG update operation. In FIG. 7, "R" indicates a TAG index (REA
D: read) operation cycle, “D” is dead cycle,
“W” indicates a TAG update (WRITE) operation cycle. TAG index transaction (TX)
Means that the update data of the preceding transaction is always TAG
Must be reflected in memory. Therefore, a subsequent TAG index transaction cannot be executed unless the TAG is updated (after writing to the TAG) for the result of the index operation. Therefore, a dead cycle always occurs between the Read → Write sequence for one transaction, thereby lowering the throughput of the TAG index operation.

[0003]

As described above, the conventional T
In the update control of the AG memory, since a dead cycle occurs between the read and write operation cycles in each transaction, a decrease in access throughput due to the dead cycle has been a problem.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a tag update control circuit that can reduce the occurrence of dead cycles in the update control of a TAG memory and improve the access throughput when updating the TAG memory.

[0005]

According to a first aspect of the present invention, there is provided a circuit for controlling indexing and updating of information in a tag memory in cache control. A tag update buffer for buffering a processing request, a tag index buffer for buffering an index processing request for information in the tag memory, an update processing request stored in the tag update buffer, and an index processing stored in the tag index buffer And an arbitration control circuit that performs arbitration control with the request.

According to a second aspect of the present invention, there is provided a circuit for controlling indexing and updating of information in a tag memory in cache control, wherein a tag updating buffer for buffering a request for updating the information in the tag memory; The tag index buffer for buffering the index processing request of the information of the above, the address information related to the update processing request stored in the tag update buffer is compared with the address information related to the index processing request stored in the tag index buffer. And performs arbitration control between the update processing request stored in the tag update buffer and the index processing request stored in the tag index buffer. The comparison circuit determines whether the address information matches. An arbitration control circuit that preferentially executes the update processing request stored in the tag update buffer when detected. It is characterized in Rukoto.

According to a third aspect of the present invention, the arbitration control circuit includes a buffer busy detection circuit for detecting that the tag update buffer is in a busy state where the update processing request cannot be further stored. Is detected, the update processing request stored in the tag update buffer is preferentially executed. According to a fourth aspect of the present invention, the arbitration control circuit has an index processing detecting circuit for detecting that the index processing request is not stored in the tag index buffer, and detecting that the index processing request is not stored. In this case, the update processing request stored in the tag update buffer is preferentially executed. The invention according to claim 5 is the invention according to claims 1-4.
In a multiprocessor system in which a plurality of processors are respectively provided in a plurality of nodes connected by a shared bus, the tag update control circuit according to any one of the above items has a function of each node when performing memory access between the nodes. The present invention is characterized in that it is provided in a tag control unit that controls updating of each information for a tag memory that holds address information and status information of a cache memory.

With the above-described configuration, the tag (TAG) update control circuit according to the present invention provides an SSRAM (Sync)
Hronous Static Random Acc
ESS memory), the dead cycle of the bidirectional bus is reduced by switching the index (Read) → update (Write) of the TAG memory.
Access to the G memory can be performed efficiently, and the throughput of the TAG index operation can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a tag update control circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a multiprocessor system to which a tag update control circuit according to the present invention is applied. In the multiprocessor system shown in FIG. 1, a plurality of processors (111 to 11) are connected to a plurality of nodes (nodes 1 to n) by the internode connection shared bus 300, respectively.
,..., n11 to n1m) are provided.

The TAG memories 100-1 to 100-n are:
In the multiprocessor system shown in FIG. 1, a copy of address information and status information of a cache memory (not shown) of processors 111 to 11m and n11 to n1m connected to each node is held. Is used to realize coherency control between the cache and the main memory.
The TAG control units 103 to n03 of each node index the TAG memories 100-1 to 100-n in order to realize coherency control for memory access between nodes,
Processors 111 to 11m connected to the node, n1
1 to n1m, and detects the status of the cache status held by the processors 111 to 11m and n11 to n1m.
The TAG memories 100-1 to 100-n are updated so that the cache status of the TAG matches the status of the TAG, and coherency control is performed.

In FIG. 1, the cache coherency control units 102 to n02 include processors 111 to 11
m, coherency control between n11 and n1m (MESI (Modified E
xclosed Shared) protocol, and to maintain coherency between nodes based on the TAG index result.
Transactions are issued to n11 to n1m, and transactions issued by the processors 111 to 11m and n11 to n1m are transferred to the inter-node bus control units 104 to n.
04. Main memory access control units 101 to n01
Controls access to the main memories 200-1 to 200-n connected to the nodes, and controls the inter-node bus control units 104 to n0.
4 from the main memory 200-1
~ 200-n read / write control. The inter-node bus controllers 104 to n04 control the shared bus 300 connecting the nodes, receive the transactions issued by the processors connected to the nodes, perform arbitration control of the shared bus, and perform the main memory access controllers 101 to n01. In order to transfer a transaction that accesses the main memory of the node to the node, and to realize coherency control between nodes,
Control is performed to transfer the transaction to the AG control units 103 to n03.

It is an object of the present invention to improve the TAG snooping process for the memory access between nodes, thereby improving the TAG snooping process, and increasing the memory access latency between nodes. Therefore, the tag control circuit according to the present invention has a TAG
In order to improve the throughput of the index operation, it is provided in the TAG control units 103 to n03 in FIG.

An embodiment of a tag control circuit according to the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration of a tag control circuit according to the present invention,
The memory 100 (the TAG memories 100-1 to 100 in FIG. 1)
Except for (−n), the configuration of the tag control circuit in the present embodiment is provided in the TAG control units 103 to n03 in FIG.

In FIG. 2, a tag control circuit for controlling the TAG memory 100 stores a TAG index instruction,
A TAG index buffer 1 for waiting (pending) a TAG index transaction during an update operation;
A TAG update buffer 2 that stores a G update transaction and waits (pending) the TAG update transaction by priority arbitration of the TAG index transaction, and selects (arbitrates) the two buffers 1 or 2 to index / update the TAG TAG to control operation
And an arbitration control circuit 3.

Also, if the TAG index transaction is TA
Until it is stored in the G update buffer 2, the address and command information of the TAG index transaction
To wait for the index data in the G memory 100, 1
One TAG index transaction is divided into four stages R1 to R4 in time series, and each stage R1
R7 to R4 are prepared and information on a maximum of four TAG index transactions is stored in each register 7 for each stage by sequentially shifting the stages.
-10. When storing a TAG index transaction in the TAG update buffer 2,
From the value of the index data storage register 11 for storing the index data of the TAG, the TAG
TAG update data is generated, and when TAG update is necessary, TAG update data is generated and the TAG update buffer 2 is updated.
Store the update data in. Here, the respective stages of R1 to R4 will be described. R1 is an external T (not shown).
The stage in which the AG index control unit issues a command to the TAG memory 100, the stage R2 is a stage in which the TAG memory 100 receives address information and commands, and the TAG memory 100 is activated, and the stage R3 is a stage in which output data is transmitted from the TAG memory 100. , R4 are the TAG control unit 103
To n03 are stages for receiving output data from the TAG memory 100.

Note that the TAG update data is
At the R2 stage in which the bus is switched by the G update, the TAG update data is transmitted to the TAG memory 100 so that the TAG update data is stored in the update data storage register 1.
(5) It is held in 2 (6).

The TAG arbitration control circuit 3 performs arbitration control of the TAG index (read) buffer 1 and the TAG update (write) buffer 2, and controls read and write processing for the TAG memory 100. The TAG arbitration control circuit 3
In order to increase the throughput of the G index operation, control is performed such that the TAG index operation is executed with priority, but the TAG update buffer 2 becomes busy due to the index operation priority arbitration,
When the address match between the transaction in the TAG index buffer 1 and the transaction in the TAG update buffer 2 is detected, the TAG update operation is processed with priority. Also, T
When data is stored in the AG update buffer 2, TA
When it is detected that no transaction exists in the G index buffer 1, the TAG updating operation is executed to effectively utilize the updating operation for the TAG memory 100. As a result, the frequency at which the TAG update buffer 2 becomes busy can be reduced, and at the same time, the frequency with which a subsequent transaction (transaction stored in the TAG index buffer 1) has an address match with the TAG update buffer 2 is also reduced. The frequency of the update operation interrupting the TAG index operation can be reduced, and the throughput of the TAG index operation can be increased.

Next, a detailed configuration of the TAG arbitration control circuit 3 will be described with reference to FIG. FIG. 3 is a block diagram of the TAG arbitration control circuit 3. The TAG arbitration control circuit 3 uses the TAG update buffer 2 indicating that the above-described TAG update condition has been satisfied,
The arbitration control of the AG index buffer 1 is performed. The TAG arbitration control circuit 3 prepares TAG update flags 13, 14, and 15 that become valid when the TAG update condition is satisfied. When any of the TAG update flags is set, the TAG arbitration control circuit 3 uses the OR circuit 19 and the selector 20. Control is performed to switch the TAG memory 100 from the index operation to the update operation.

The TAG update flag 13 is set when the TAG update buffer 2 exceeds a busy threshold, and is stored in the buffer by the buffer busy detection circuit 16 with the write pointer and the read pointer of the TAG update buffer 2. Manages the number of transactions and detects buffer busy. When the TAG update flag 13 is set, the TAG index process is inhibited (the TAG index transaction is suspended in the TAG index buffer 1), and the TAG update process is started.
Is written in the TAG memory 100. When the TAG update buffer 2 is released from the busy state, the TAG arbitration control circuit 3 resets the TAG update flag 13 and executes the TAG index processing.

The TAG update flag 14 is set when an address match between the transaction in the TAG update buffer 2 and the transaction in the TAG index buffer 1 is detected. The TAG update flag 14 is set until the transaction whose address matches the address of the TAG update buffer 2 is written to the TAG memory 100. While the TAG update flag 14 is set, the TAG index transaction is pending in the TAG index buffer 1 and the TAG update processing is performed. After completion, the TAG update flag 14 is reset,
Execute G index processing. Thus, the TAG index transaction can always reflect the latest value of the TAG memory 100.

The TAG update flag 15 is set when there is no transaction in the TAG update buffer 2 when no TAG index instruction is stored in the TAG index buffer 1. This is TAG update buffer 2
This is to reduce the frequency of occurrence of the buffer busy and the address match as described above. Since the TAG update buffer 2 does not execute a TAG update operation unless it detects a buffer busy or an address match with a TAG index transaction, a case where a transaction is stored in the TAG update buffer 2 is high, and a buffer busy or an address match occurs. The frequency increases. If the frequency of buffer busy or address matching increases, the throughput of the TAG index operation decreases.
Switching from “head” to “Write” is likely to occur. Therefore, if a transaction exists in the TAG update buffer 2 and no transaction exists in the TAG index buffer 1, the TAG update flag 15 is set and T
The AG update process is executed to control as much as possible the buffer busy and the address match of the TAG update buffer 2 and control the throughput of the TAG index operation.

Next, the TAG updating operation will be described with reference to time charts FIGS. The TAG update operation has three cases as described above. The first is a case in which the TAG update buffer 2 is busy, and the second is a TAG update buffer 2.
The case where the address match of the transaction between the update buffer 2 and the TAG index buffer 1 is detected,
In this case, a TAG update operation is performed when there is no G index transaction. The first busy is assumed to be busy when one transaction is stored in the TAG update buffer 2 for simplification of the description.
In the examples of FIGS. 4 to 6, transaction 0 is the TA
It is assumed that an update operation of the G memory 100 is required.

FIG. 4 shows a TAG update operation when the TAG update buffer 2 is busy. First, transactions 0 to 6 are sequentially performed in the TAG index buffer 1 in the periods T1 to T7.
And executes a TAG index process. When the TAG index transaction 0 receives the TAG index result at the R4 stage in FIG. 2 (T5), it generates TAG update data from the transaction information and the TAG index data,
In order to update the TAG, the update data is stored in the TAG update buffer 2 at a period T6. At the same time, the write pointer of the TAG update buffer 2 is incremented, and a difference is generated between the write pointer and the read pointer. The TAG arbitration control circuit 3 detects busy from the write pointer and the read pointer with the buffer busy detection circuit 16, and sets the TAG update flag 13 at a cycle T7. When the TAG arbitration control circuit 3 sets the TAG update flag 13, the TAG arbitration control circuit 3 suppresses the TAG index process of the transaction 6 (waits for the transaction in the TAG index buffer 1) and switches the TAG to the update operation. Transaction 0 stored in the TAG update buffer 2 updates (writes) the TAG
Then, the read pointer of the TAG update buffer 2 is incremented. When the buffer busy detection circuit 16 detects that there is no difference between the write pointer and the read pointer, the TAG arbitration control circuit 3
Is reset to release the buffer busy. When the TAG update flag 13 is reset, the TAG arbitration control circuit 3 sends the transaction 6
To execute the TAG index processing.

FIG. 5 shows that the TAG index transaction is T
This is an example of a case where the address is the same as the transaction stored in the AG update buffer 2. Transactions having the same address are assumed to be transactions 0 and 6. FIG.
When a TAG index transaction is continuously received from T1 to T7 in the same manner as in, the transaction 0 is stored in the TAG update buffer 2 at T6. At this time, since the transaction 6 in which the TAG index operation is to be performed has the same address as the transaction 0, the TAG arbitration control circuit 3 detects that the transactions 0 and 6 have the same address in the address comparator 17 of FIG. , TA
Set the G update flag 14 and set transaction 6 to T
Pending in AG index buffer 1 When the TAG update flag 14 is set, the TAG arbitration control circuit 3
Execute the TAG update operation of transaction 0. TA
The G update flag 14 is reset when the transaction 0 of the TAG update buffer 2 is completed (when the TAG memory 100 is updated), and the TAG arbitration control circuit 3
Since the update flag 14 is reset, the transaction 0 of the TAG index buffer 1 is executed to perform the TAG index processing.

FIG. 6 is a time chart showing a TAG updating operation when there is no TAG index transaction. FIG.
TAG index transactions 0-3 are:
It is executed continuously from T1 to T4, but after that, 2
Transaction 4 is being executed at intervals of a cycle.
Transaction 0 is stored in the TAG update buffer 2 at T6, but when stored, there is no transaction in the TAG index buffer 1 and the TAG index operation has not been executed one cycle before, so transaction 0 immediately executes the TAG update operation. You can do it. This is T
Since there is no TAG index transaction at T5 before being stored in the AG update buffer 2, a cycle (dead cycle) in which no access is made to the TAG occurs, and the transaction 0 is stored in the TAG update buffer 2 at T5.
6 also has no transaction in the TAG index buffer 1, so that the TAG can be updated.

FIG. 8 is a diagram showing the TAG indexing operation according to the present invention for preparing a TAG update buffer in comparison with the conventional sequence without preparing the TAG update buffer of FIG.
6 is a timing chart showing a sequence until a G update operation is started. As described above, in the conventional example shown in FIG. 7, the subsequent TAG index transaction must always reflect the update data of the preceding transaction in the TAG memory.
Must be updated (after writing to the TAG), subsequent TAG index transactions cannot be performed. Therefore, Read → W is always required for one transaction.
A dead cycle occurs during the write sequence,
The throughput of the TAG index operation is reduced. For this reason, in the example shown in FIG. 7, the TAG index operation can execute only three transactions in nine cycles. on the other hand,
In the case of the present embodiment shown in FIG. 8, since the TAG update buffer has the TAG update buffer, the TAG update buffer can detect an address match with the subsequent TAG index transaction, and the update data stored in the TAG update buffer is transmitted to the subsequent transaction. Since it can be reflected, continuous TA
G index processing can be performed. As a result, the sequence of updating from the TAG index having the TAG update buffer becomes 4 transactions in 9 cycles, and it can be seen that the throughput of the TAG index is improved by reducing the dead cycle according to the present invention.

As described above, in the tag control circuit of the present embodiment described with reference to FIG. 2, the TAG update buffer 2 is prepared, and the TAG update operation is suppressed as much as possible by buffering the TAG update data. , Unless the TAG update buffer 2 becomes busy, the TAG index operation is performed to improve the TAG snoop processing throughput. However, if the subsequent TAG index transaction is TA
When indexing the G memory 100, the TAG memory 100
May have been stored in the TAG update buffer 2 and the subsequent transaction may not reflect the latest value in the TAG memory 100. Thus, in the present embodiment, the TAG arbitration control circuit 3 is provided, and the TAG arbitration control circuit 3 performs the transaction stored in the TAG update buffer 2 and the subsequent TAG arbitration control circuit 3.
By providing a function to detect an address match with an index transaction, if an address match is detected, TA
The transaction of the G update buffer 2 is forcibly executed.

The subsequent TAG index transaction is T
The TAG index operation is executed after waiting until the update transaction of the same address is reflected in the TAG memory 100 in the AG index buffer 1. Thereby, TAG
The index operation determines whether the TAG update buffer 2 is busy or
Unless an address match is detected, TAG memory 1
00 can be indexed, and a dead cycle due to switching from Read to Write that reduces the throughput of the TAG index operation is reduced.

Further, in this embodiment, when the TAG index transaction does not exist in the TAG index buffer 1 so that the frequency of the TAG update operation due to the busyness of the TAG update buffer 2 or the address match can be reduced, Is provided, a function of executing a transaction in the TAG update buffer 2 is also provided.

[0030]

According to the present invention, the TAG access Re
Since the TAG index processing is executed efficiently by reducing the dead cycle generated in ad → Write,
The throughput of the access (index processing) to the TAG memory can be improved. When the processor executes the memory access between the nodes, the snoop processing (index processing) of the TAG becomes faster, so that the latency of the memory access is reduced. You can get the effect that you can give

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a multiprocessor system to which a tag update control circuit according to the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a tag update control circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a tag arbitration control circuit 3 shown in FIG. 2;

FIG. 4 is a timing chart showing an operation example of the tag update control circuit shown in FIG. 2;

FIG. 5 is a timing chart showing another operation example of the tag update control circuit shown in FIG. 2;

FIG. 6 is a timing chart showing another operation example of the tag update control circuit shown in FIG. 2;

FIG. 7 is a timing chart for explaining the throughput of tag memory access according to the related art.

FIG. 8 is a timing chart for explaining the throughput of tag memory access according to the present invention.

[Explanation of symbols]

 1 Tag (TAG) index buffer 2 Tag (TAG) update buffer 3 Tag (TAG) arbitration control circuit 16 Buffer busy detection circuit 17 Address comparator 18 Index transaction detector

Claims (5)

[Claims] 1. A circuit for controlling indexing and updating of information in a tag memory in cache control, comprising: a tag update buffer for buffering an update processing request for information in a tag memory; And a arbitration control circuit that performs arbitration control between the update processing request stored in the tag update buffer and the index processing request stored in the tag index buffer. Tag update control circuit. 2. A circuit for controlling indexing and updating of information in a tag memory in cache control, comprising: a tag updating buffer for buffering an updating request for information in a tag memory; And an address comparison circuit that compares the address information related to the update processing request stored in the tag update buffer with the address information related to the index processing request stored in the tag index buffer. And performs arbitration control between the update processing request stored in the tag update buffer and the index processing request stored in the tag index buffer. When the comparison circuit detects that the address information matches, the tag is determined. An arbitration control circuit that preferentially executes the update processing request stored in the update buffer. Tag update control circuit. 3. The arbitration control circuit further includes a buffer busy detection circuit for detecting that the tag update buffer is in a busy state in which an update processing request cannot be further stored. 3. The tag update control circuit according to claim 2, wherein the update processing request stored in the tag update buffer is preferentially executed. 4. An arbitration control circuit having an index processing detection circuit for detecting that an index processing request is not stored in the tag index buffer, and when detecting that an index processing request is not stored. 4. The tag update control circuit according to claim 2, wherein the control section executes the update processing request stored in the tag update buffer preferentially. 5. A multiprocessor system in which the tag update control circuit according to claim 1 is provided with a plurality of processors at a plurality of nodes connected by a shared bus, respectively. A tag update control circuit, which is provided in a tag control unit that performs update control of each information with respect to a tag memory that holds address information and status information of a cache memory of each node when performing access. .