JP2001196928A - A / D conversion processing device - Google Patents

Abstract

(57) Abstract: Provided is an A / D conversion processing device capable of easily increasing the number of polyphase conversion clocks and obtaining a highly accurate delay amount. An input amplifier receives a pulse from a pulse shaping circuit in which the amplitude and pulse width of a clock having a constant period are shaped, and a pulse from the input amplifier is delayed to generate an A / D conversion clock. A clock control circuit 107 including a delay circuit 110 for generating a signal, an output amplifier 111 for outputting a delayed pulse from the delay circuit 110, and a converted signal supplied from a distribution circuit supplied from the delay circuit. And a plurality of A / D conversion circuits 108 for performing A / D conversion using the clock for A / D conversion, and a plurality of A / D conversion circuits 108 connected in series so that the clock control circuits 106 are connected in series. Become.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion processing device suitable for converting an input signal waveform into digital data corresponding to the voltage value.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a conventional configuration. FIG.
FIG. 6 is a diagram showing an operation time chart of FIG. 5. Original vibration 501
And an oscillation signal from the source 501, and a plurality of A
A plurality of conversion clocks 552-1 are formed into pulse widths and amplitudes suitable as conversion clocks used when the / D conversion circuits 503-1 to 503-1-n perform A / D conversion, each having a desired delay time difference. To n output polyphase pulse shaping circuit 502
And a signal 556-0 to be A / D-converted,
/ D conversion circuits 503-1 to 503-1-n with the same delay time and output 55
It comprises an input distribution circuit 506 for performing 6-1 to n, and a result processing circuit 504 for storing or performing arithmetic processing on the outputs 557-1 to n of the A / D converted results.

As shown in FIG. 6, an A / D conversion circuit 503-1
N, the input signal 556-1 to be A / D converted
n is the time difference generated by the polyphase pulse shaping circuit 502.
Sampling is performed by the conversion clocks 552-1 to n having K1 to Kn and A / D conversion is performed. Further, the result of the A / D conversion is output to the result processing circuit 504 as digital data 577-1 to n. Incidentally, as related to the prior art, Japanese Unexamined Patent Application Publication
An example described in JP-A-6-273452 is given.

[0004]

As described above, in the conventional apparatus, when a conversion clock to be supplied to a plurality of A / D conversion circuits is created, the input original signal is multi-phased.
A multi-phase pulse shaping circuit, which is a circuit for generating a plurality of clocks having a desired time difference, is separately prepared and supplied to the clock.

However, these multi-phase pulse shaping circuits require the A / D converter from the multi-phase pulse shaping circuit when the speed of the apparatus is increased and the frequency of the conversion clock is increased or when the number of generated clocks is increased. It is expected that it will be difficult to control the amount of delay including the wiring path leading to the conversion circuit with high precision and create a conversion clock having a desired time difference.

In particular, when the number of A / D conversion circuits needs to be increased in the future and the number of conversion clocks is increased, such a multi-phase pulse shaping circuit manufactured separately has a problem. When it was manufactured and made into an apparatus, it was necessary to make it again so as to have the optimal time difference and the number of phases.

An object of the present invention is to provide an A / D conversion processing device capable of easily increasing the number of polyphase conversion clocks and obtaining a highly accurate delay amount.

[0008]

According to the present invention, there is provided an input amplifier which receives a pulse from a pulse shaping circuit in which the amplitude and pulse width of a clock having a constant period are input, and delays the pulse from the input amplifier to A. A clock control circuit including a delay circuit for generating a clock for / D conversion and an output amplifier for outputting a delayed pulse from the delay circuit; A / D conversion by the A / D conversion clock supplied from the circuit
An A / D conversion processing device characterized in that a data conversion circuit composed of a plurality of A / D conversion circuits for performing conversion is connected in a plurality of stages so that the clock control circuits are connected in series.

According to the present invention, an original oscillator for generating a clock having a fixed period, a pulse shaping circuit for receiving the clock and shaping the amplitude and the pulse width thereof, and inputting a pulse from the pulse shaping circuit. Comprising: an input amplifier for delaying a pulse from the input amplifier to generate a clock for A / D conversion; and an output amplifier for outputting a delayed pulse from the delay circuit A plurality of clock control circuits in which a plurality of control circuits are serially connected in series, and an A / D converter for individually converting a converted signal supplied through the distribution circuit by an A / D conversion clock supplied from the plurality of delay circuits. An A / D conversion processing device, comprising: a plurality of A / D conversion circuits for performing A / D conversion.

Further, according to the present invention, a source for generating a clock having a fixed period, a pulse shaping circuit into which the clock is input and shaping the amplitude and pulse width thereof, and a pulse from the pulse shaping circuit being one of A transmission line connected to an end point and connected to a terminal circuit for preventing reflection at an opposite end point, and a plurality of conversion clock inputs at a constant interval on the transmission line for receiving a signal to be converted supplied through a distribution circuit. A / D conversion processing device comprising a plurality of A / D conversion circuits for performing A / D conversion individually.

[0011]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention. The A / D converter according to the first embodiment of the present invention can vary its oscillation cycle,
A variable source 101 whose cycle can be freely set, and an oscillation signal from the variable source 101 are input, and an A / D conversion circuit 108 at the subsequent stage inputs an A / D signal.
A pulse shaping circuit 102 which shapes and outputs a pulse width and amplitude suitable as a conversion clock used when performing D conversion.
, A data conversion circuit 106-1 to n, and a signal 156-0 to be A / D-converted are input, distributed to the data conversion circuits 106-1 to n with the same delay time, and output 156-1 to n. Input distribution circuit 10
3, and a result processing circuit 104 for storing or processing the output 157 of the result of the A / D conversion.

Here, each of the data conversion circuits 106-1 to 106-n includes a clock control circuit 107-1 to n and an A / D conversion circuit 108-1.
, And each of the clock control circuits 107-1 to 107-1.
Each of the input buffer amplifiers 109-1 to 109-n, each of the delay circuits 110 and each of the output buffer amplifiers 111-1 to 111-n are configured. Here, a desired delay amount is set in advance for the delay circuits 110-1 to 110-n, and the input buffer amplifiers 109-1 to n and the output buffer amplifiers 111-1 to 111-n are connected to the data conversion circuits 106-1 to n.
In other words, this is an amplifier that enables input and driving of a clock with predetermined characteristics (amplitude, pulse width, etc.) when a plurality of delay circuits 110-1 to 110-n are connected in series. The conversion clock 152 passes through a clock control circuit 107-1 composed of an input buffer amplifier 109-1, a delay circuit 110-1, and an output buffer amplifier 111-1, and sequentially controls clocks connected in series having the same configuration. Delays are made sequentially in circuits 107-2 to 107-n.

FIG. 2 is a diagram showing an operation time chart of FIG. A source signal 151 output from the variable source 101 of FIG.
Is input to the pulse shaping circuit 102, and is shaped into a pulse width and amplitude suitable as a conversion clock 152 used when the subsequent A / D conversion circuits 108-1 to 108-n perform A / D conversion, and output. In the first-stage data conversion circuit 106-1, the input conversion clock 152 is delayed, and the A / D conversion circuit 10
8-1 and output to the next-stage data conversion circuit 106-2.
The delay is set in the delay circuit 110-2 in which the desired amount of delay is set, then sequentially delayed, delayed in the final-stage delay circuit 110-n, and used in each of the A / D conversion circuits 108-1 to 108-n. The conversion clocks 153-1 to 153-1 are generated and supplied.

In FIG. 2, the delay time differences T1 to Tn of the converted clocks 153-1 to 15-n are created by the delay circuits 110-1 to 110-n. On the other hand, the signal 156 to be A / D converted
−0 is input to the distribution circuit 103, and each of the A / D conversion circuits 108-1 to
Distribution and supply are performed so that there is no difference in the delay time to reach n, that is, at the same timing. Each A / D conversion circuit
At 108-1 to 108-n, the signals 156-1 to n to be subjected to A / D conversion input in this way are sampled by the conversion clocks 153-1 to 15-n, and A / D conversion is performed. The corresponding digital data 157-1 to 157-1-n are output to the result processing circuit 104, and are stored or processed.

Therefore, according to the first embodiment, there is provided an A / D conversion processing device capable of easily increasing the number of phases of a polyphase conversion clock and obtaining a highly accurate delay amount. Obtainable. Further, in the first embodiment, the data conversion circuit described above is once converted to an A /
If the conversion clock is formed in the same chip as the D conversion circuit and connected in series, a conversion clock having a desired delay time difference can be easily obtained, and the number of phases of the conversion clock can be easily increased. .

FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention. The same parts as those in the first embodiment of FIG. 1 are denoted by the same reference numerals. An A / D converter according to a second embodiment of the present invention is configured such that a variable original 101 and an oscillation signal from the variable original 101 are input, and an A / D converter 1
08-1 to n form a pulse width and amplitude suitable as a conversion clock used when performing A / D conversion and output a pulse shaping circuit 102, and a transmission line 301 to which the conversion clock is input and propagated. A termination circuit 302 for preventing the propagated converted clock from being reflected at the end of the transmission line 301.
And an A / D connected to the transmission line 301 at a fixed position interval
It is composed of a conversion circuit 108 and a result processing circuit 104.

Here, the transmission line 301 is constituted by, for example, a line having a microstrip structure formed on a printed circuit board or a coaxial line. Similar to the first embodiment, the source 151 output from the variable source 101 is a pulse generation circuit.
The signal is supplied to the transmission line as a conversion clock 152 via 102. The conversion clock is added with a delay amount corresponding to the position of each of the A / D conversion circuits 108-1 to 108-n arranged and connected on the transmission line. 1
Will be supplied as

In the operation time chart of this embodiment shown in FIG. 4, the delay time differences caused by the difference in the positions on the transmission line are represented by t1 to tn. A / D
The conversion circuits 108-1 to n convert these conversion clocks 153-1 to n.
A / D-convert the signals 156-1 to n to be A / D-converted at the same timing, output the results as digital data 157-1 to n to the result processing circuit 104, and store or calculate Perform processing.

Therefore, according to the second embodiment, there is provided an A / D conversion processing apparatus which can easily increase the number of phases of a polyphase conversion clock and obtain a highly accurate delay amount. Obtainable. In the second embodiment, the transmission line is configured to be long in advance and the A / D
By connecting the conversion circuit, a conversion clock having a desired time difference can be easily obtained.

[0020]

According to the present invention, it is possible to obtain an A / D conversion processing device capable of easily increasing the number of polyphase conversion clocks and obtaining a highly accurate delay amount.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an operation time chart of FIG. 1;

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing an operation time chart of FIG. 3;

FIG. 5 is a diagram showing a conventional configuration.

FIG. 6 is a diagram showing an operation time chart of FIG. 5;

[Explanation of symbols]

101: variable original vibration, 102: pulse shaping circuit, 103:
Input distribution circuit, 104 result processing circuit, 106 data conversion circuit, 107 clock control circuit, 108 A / D conversion circuit, 109 input buffer amplifier, 110 delay circuit, 111 output buffer amplifier, 301 transmission Line, 302 ... Terminal circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tokuo Chujo 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Institute (72) Inventor Masami Makuuchi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Masayoshi Takahashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Production Co., Ltd. (72) Inventor Shinji Homma 3--16 Higashi 3-chome, Shibuya-ku, Tokyo No. 3 Hitachi Electronics Engineering Co., Ltd. F-term (reference) 5J022 AA01 BA01 BA10 CE01 CE03 CE04 CF02

Claims (3)

[Claims] 1. An input amplifier for receiving a pulse from a pulse shaping circuit in which the amplitude and pulse width of a clock having a constant period are shaped, and an A / D converter for delaying a pulse from the input amplifier.
A clock control circuit including a delay circuit for generating a clock for conversion and an output amplifier for outputting a delayed pulse from the delay circuit, and a converted signal supplied through the distribution circuit is output from the delay circuit. A plurality of data conversion circuits each including a plurality of A / D conversion circuits for performing A / D conversion with a supplied A / D conversion clock are connected so that the clock control circuits are connected in series. A / D conversion processing device characterized by the above-mentioned. 2. A source for generating a clock having a fixed period, a pulse shaping circuit for receiving the clock and shaping its amplitude and pulse width, and an input amplifier for inputting a pulse from the pulse shaping circuit. And a delay circuit for delaying a pulse from the input amplifier to generate a clock for A / D conversion and an output amplifier for outputting a delayed pulse from the delay circuit. A plurality of clock control circuits connected in series and a plurality of A's for individually performing A / D conversion of a converted signal supplied through the distribution circuit by A / D conversion clocks supplied from the plurality of delay circuits. An A / D conversion processing device comprising: an A / D conversion circuit. 3. A source for generating a clock having a fixed period, a pulse shaping circuit for receiving the clock and shaping the amplitude and pulse width thereof, and a pulse from the pulse shaping circuit being input to one end point. At the opposite end point, a transmission line to which a terminating circuit for preventing reflection is connected, and the converted signal supplied through the distribution circuit are individually input to the transmission line by a plurality of conversion clock inputs at regular intervals on the transmission line. An A / D conversion processing device comprising: a plurality of A / D conversion circuits for performing / D conversion.