JP2001102483A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to reduce thermal resistance by connecting a semiconductor device and a thermal via in a wiring board with good electrical and thermal efficiency. SOLUTION: A semiconductor device comprises a semiconductor element to be mounted on a wiring board, a conductive pillar-shaped member mounted on the wiring board and passed through the semiconductor in the thickness direction, and a thermally conductive member for connecting the semiconductor element and the conductive pillar-shaped member thermally and electrically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a high-frequency power amplifier for a portable communication terminal.

[0002]

2. Description of the Related Art In recent years, miniaturization and weight reduction of portable communication terminals, for example, portable telephones, are progressing at a rapid pace, and at the same time, cost reduction is an important issue. This small, lightweight,
In order to realize the three low-cost conditions, it is essential to improve the efficiency (ratio of output power to power consumption) of the high-frequency power amplifier. Since the efficiency of a high-frequency power amplifier is almost proportional to the power consumption during a call, considering the same continuous talk time as a reference, the use of a high-efficiency, high-frequency power amplifier with low power consumption results in a corresponding increase in the battery capacity. Can be reduced, and the weight can be reduced.

[0003] On the other hand, from the viewpoint of reducing the cost of the power amplifier itself, in addition to the above-described efficiency improvement, it is essential that the power amplifier itself be densely mounted and miniaturized. This high-density mounting and miniaturization are not necessarily technical issues limited to power amplifiers, but due to the consolidation of heat spots, even if the amount of heat generated can be reduced, the local temperature inside the device will be higher than conventional products. In some cases, it is necessary to develop a technology for lowering the thermal resistance in accordance with the higher density.

In a communication device having an antenna, such as a mobile phone, a semiconductor element in a high-frequency power amplifier generates heat when radio waves are transmitted through the antenna. Since the efficiency of a high-frequency power amplifier is not 100% and most of the difference between the power consumption and the output power is released as heat, generally, the heat released from the semiconductor element in the power amplifier is transmitted from the semiconductor substrate. Designed to be transmitted to the motherboard via the wiring board and form the outer shape of the mobile phone, radiated, heat transferred to the air, or transmitted to the outside through the hand of the person holding the mobile phone Have been. This semiconductor device includes a semiconductor element and a wiring board on which the semiconductor element is mounted, and heat generated from the semiconductor element passes through the wiring board. Therefore, it can be said that the higher the thermal conductivity of the wiring board, the more suitable it is to lower the temperature of the semiconductor element to a certain reference value or less.

This semiconductor device used for a power amplifier or the like will be described with reference to FIG. The multilayer wiring board 2 is mounted on the motherboard 8. The semiconductor element 1 is mounted on the multilayer wiring board 2 via a brazing material 9. The semiconductor element 1 includes a semiconductor substrate 1a and a circuit such as a transistor formed on a surface of the semiconductor substrate 1a. A heat generating portion 1b (for example, a region between an emitter and a base of a transistor) exists in a part of this circuit.
Reference numeral 3 denotes a columnar member (hereinafter referred to as a thermal via) penetrating the multilayer wiring board 2 in the thickness direction, and includes a semiconductor substrate 1a.
And the motherboard 8 are electrically and thermally connected. Reference numeral 5 denotes a wiring element of the multilayer wiring board 2, which is connected to the motherboard 8. A plurality of components 12 such as a chip capacitor and a resistor are mounted on the multilayer wiring board 2 in addition to the semiconductor element 1.

In general, a ceramic-based material such as glass-ceramic, glass-epoxy, or alumina having high electrical insulation is used as the material of the multilayer wiring board 2. The materials of the wiring board as described above have characteristics of high electrical insulation, but low thermal conductivity. Therefore, when these materials are used as they are as the material of the multilayer wiring board 2, the thermal resistance of the entire semiconductor device is reduced. Therefore, there is a problem that the temperature of the heat generating portion 1b of the semiconductor element 1 rises above a target upper limit.

As one means for solving such a problem,
As shown in the semiconductor device of FIG. 5, there is a device in which a plurality of thermal vias 3 are arranged on a multilayer wiring board 2 and a semiconductor element 1 is mounted thereon using a conductive brazing material 9 such as solder. By providing the thermal vias 3, the semiconductor element 1 is electrically connected to the common ground electrode on the motherboard 8 via the back surface of the multilayer wiring board 2, and at the same time, the semiconductor substrate 1 a and the motherboard 8 are thermally connected. Since the connection can be made, the thermal resistance between the heat generating portion 1b of the semiconductor element 1 and the rear surface of the multilayer wiring board 2 is reduced, and the temperature of the heat generating portion 1b can be set to a certain reference value or less.

On the other hand, in the semiconductor device, for example, a Si single crystal substrate is conventionally used as a material of the semiconductor substrate 1a, and a high frequency power amplifier has been formed by forming a MOSFET circuit on the single crystal substrate. . This S
Since the i-type material has a relatively high thermal conductivity, the thermal resistance between the heat generating portion 1b on the element surface and the back surface of the multilayer wiring board 2 does not increase as much as when a GaAs-based compound semiconductor substrate described later is used. . However, in order to improve the efficiency of the high-frequency power amplifier, there is a problem that a Si-based MOSFET is not sufficient. For this reason, there is a semiconductor substrate formed of a GaAs-based compound semiconductor substrate for the purpose of improving the output and improving the efficiency of the high-frequency power amplifier.

Since the GaAs-based material has a characteristic of low thermal conductivity and high electrical insulation, the semiconductor substrate 1a
A through hole called a via hole is formed in a part of the substrate, a plating layer such as gold plating is provided on the back surface of the semiconductor element, a specific wiring on the front surface side of the semiconductor substrate 1a and the back surface of the semiconductor substrate via the via hole. May be electrically connected. Thereby, the wiring inductance can be reduced. In this case, the plating layer functions as a heat diffusion plate, and the thermal resistance between the heat-generating portion 1b on the element surface and the back surface of the multilayer wiring board 2 becomes small.
Even with an aAs-based material, it is possible to reduce the thermal resistance of the entire power amplifier.

The plating layer used as the above-mentioned heat diffusion plate is generally a plated heat sink (hereinafter, PHS).
An example of a semiconductor device in which the PHS and the via hole are combined is disclosed in, for example, JP-A-5-152.
No. 340, for example.

FIG. 6 shows a semiconductor device in which a heat diffusion plate 13 is interposed between a semiconductor substrate 1a constituting a semiconductor element 1 and a wiring substrate 2. According to FIG. 6, not only the power amplifier of the portable communication device but also a structure in which a thermal via is not provided in the wiring board 2 when a semiconductor element is mounted on the wiring board can be considered. Examples of the semiconductor device to which the heat diffusion plate is attached as described above include, for example, JP-A-11-191603 and JP-A-10-247704.

FIG. 7 shows a semiconductor device in which the thermal via 3 penetrating through the wiring board 2 is substantially equal to or larger than the semiconductor substrate 1a and has a single shape. In the figure, 7 indicates PHS. As described above, the PHS 7 is made of a gold plating layer or the like, and transfers heat from the semiconductor element 1 to the thermal via 3.

[0013]

SUMMARY OF THE INVENTION GaAs having low thermal conductivity
When a PHS is provided on the back surface of a semiconductor substrate made of an s-based material, and the PHS is directly fixed to a multilayer wiring substrate using a brazing material such as solder, the element is not as thick as a Si-based semiconductor device unless the PHS is extremely thick. The thermal resistance from the heat generating portion on the surface to the multilayer wiring board cannot be reduced. However, when such a thick PHS is formed by gold plating,
It becomes extremely expensive in terms of cost.

If the thickness of the PHS due to the gold plating layer is too large, a difference in linear expansion coefficient between GaAs and gold may cause a thermal stress generated in a reflow process in a manufacturing process, or a heat cycle during device operation. Cracks may occur in the semiconductor substrate 1a due to thermal stress generated at the interface between the gold plating layer and the semiconductor substrate,
There is a possibility that peeling may occur between S and S.

Further, as disclosed in Japanese Patent Application Laid-Open No. 10-247704, a wiring board, a first brazing material, a heat diffusion plate, a second brazing material, and a semiconductor element are mounted in this order from the bottom to form a semiconductor substrate. In order to reduce the thermal resistance by reducing the thickness of the thermal via, the spread of heat to the thermal vias becomes narrow because the three-dimensional heat spread in the semiconductor substrate is insufficient.
Thermal vias that do not contribute to heat transfer occur, making it impossible to use thermal vias effectively. For this reason, the thermal resistance in the multilayer wiring board cannot be sufficiently reduced, and the thermal resistance of the entire device may not always be reduced.

Conversely, if the thickness of the semiconductor substrate is increased, the heat is diffused over a wider range as the substrate is thicker, and the thermal vias can be effectively used without waste. Processing becomes difficult,
There is a problem that costs cannot be met. Further, since the thermal resistance in the semiconductor substrate increases as the thickness increases, the thermal resistance of the entire device does not always decrease.

As a result, considering the total thermal resistance from the heat-generating portion on the front surface of the semiconductor substrate to the rear surface of the multilayer wiring substrate, it is not very effective to reduce the thermal resistance even if the semiconductor substrate is thin or thick. No.

Incidentally, the fact that the base material of the multilayer wiring board is made of a glass ceramic or glass epoxy material having high insulating properties means that the multilayer wiring board becomes a heat insulating layer substantially.
Except for the thermal via, there is no portion that allows heat to escape to the rear surface of the multilayer wiring board.

As shown in FIG. 7, by forming a single thermal via 3 having a sectional area equal to or larger than the sectional area of the semiconductor substrate 1a, the thermal resistance can be sufficiently reduced. However, when a single huge thermal via is formed, a nest is formed inside the thermal via, and as a result, there is a high possibility that the thermal resistance is increased.

On the other hand, when a device is formed by press-fitting a thermal via 3 made of a plate-like member by providing a through hole in the multilayer wiring board 2, even if a material having no problem in terms of thermal resistance is selected,
If the coefficient of linear expansion of the thermal via 3 and the coefficient of linear expansion of the multilayer wiring board 2 are not matched within a certain error range, there is a possibility that the element will be broken by thermal stress at the time of heat generation. If the size of the thermal via 3 is made considerably smaller than the through hole of the multilayer wiring board 2 in order to avoid this problem, it is necessary to separately consider a method of fixing the thermal via 3, which causes an increase in cost. I will.

An object of the present invention is to provide a semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring substrate without increasing the thickness of a semiconductor substrate, at a low cost.

[0022]

A first object of the present invention is to provide a semiconductor device mounted on a wiring board and a first element disposed in the wiring board and penetrating the wiring board in a thickness direction.
And a second heat conductive member for thermally connecting the semiconductor element and the first heat conductive member.

A semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction;
A heat diffusion plate provided between the heat diffusion member and the semiconductor element, and a second heat conduction member for thermally connecting the heat diffusion plate and the first heat conduction member. Achieved.

A semiconductor element mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the wiring board in a thickness direction;
A heat diffusion plate provided between the heat conduction member and the semiconductor element and having an area equal to or larger than the area of the semiconductor element; and thermally connecting the heat diffusion plate and the first heat conduction member to each other. And a second heat conducting member having an area equal to or larger than the area of the semiconductor element is provided.

In the semiconductor device according to the first aspect, a multi-finger element including a plurality of transistors or diodes is formed on a single-crystal semiconductor substrate such as Si or a compound semiconductor substrate such as GaAs. This is achieved by:

Further, the second heat conductive member disposed between the semiconductor element and the wiring board is achieved by using a material having a higher thermal conductivity than the semiconductor element.

A second heat conductive member disposed between the semiconductor element and the wiring board;
This is attained by the fact that all of the heat diffusion plates disposed between the heat conducting members are made of a material having higher heat conductivity than the semiconductor element.

The thickness of the semiconductor element, the second heat conducting member and the heat diffusion plate is achieved by the thinnest heat diffusion plate and the thickest second heat conduction member.

[0029]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a sectional view of a semiconductor device provided with the present invention, and FIG. 2 is a sectional view of a semiconductor device provided with a thermal via which does not penetrate a multilayer wiring board of the present invention.

In FIG. 1, a semiconductor substrate 1 a constituting a semiconductor element 1 is mounted on a wiring board 2. A plurality of thermal vias 3 having conductivity and high thermal conductivity are provided inside the wiring board 2 so as to penetrate the wiring board 2. A heat conductive member 4 is interposed between each thermal via 3 and the semiconductor substrate 1a, and is electrically and thermally connected.

Since the wiring board 2 is made of a glass-ceramic or glass-epoxy material having a high insulation property and a low thermal conductivity, portions other than the thermal vias 3 are close to heat insulation and are electrically connected within the wiring board 2. Almost only the thermal via 3 has good thermal conductivity. Therefore, as many thermal vias 3 as possible are thermally connected to the semiconductor substrate 1 by using the heat conductive member 4 so that the semiconductor substrate 1
It is possible to reduce the thermal resistance between the heat generating portion 1b on the surface layer a of FIG. The semiconductor substrate 1a is as thin as possible (100 μm) in order to reduce the thermal resistance of this portion.
m or less, typically about 30 to 50 μm).

Even if the heat diffusion in the semiconductor substrate 1a becomes insufficient due to the thinning, the region where the temperature is locally high and the thermal via 3 on the back surface of the semiconductor substrate 1a is thermally By effectively and effectively connecting, it is possible to reduce the thermal resistance between the rear surface of the wiring board 2 and the heat generating portion 1b.

The semiconductor substrate 1 on which the heat conducting member 4 is located
The space between a and the wiring board 2 may be sealed using an insulating member without any problem, and may be mounted in a form floating above the space as shown in FIG. The wiring element 5 on the back surface of the wiring board 2 is electrically connected to the thermal via 3,
The wiring element 5 is connected to a common ground wiring on the motherboard 8. Incidentally, the wiring element 5 does not need to cover the entire back surface of the wiring board 2. This point is common to all embodiments of the present invention described below.

FIG. 1 shows an example in which the thermal vias 3 are evenly arranged. However, the number of thermal vias 3 and their intervals are not limited to the example shown in FIG.

In FIG. 2, when the wiring board 2 is a multilayer wiring board, if the wiring element 5 having high conductivity and high thermal conductivity is interposed between the respective layers, the wiring board 2 penetrates in the thickness direction. There is no problem even if there is no thermal via 6 that does not directly contact the heat conductive member 4. It is desirable that the thermal vias 3 or 6 and the semiconductor substrate 1a be thermally connected as much as possible. The thermal vias 6 that cannot be directly connected to the semiconductor substrate 1a by the heat conductive member 4 are formed by the wiring elements 5 existing between the layers. The heat can be effectively utilized, and the thermal resistance can be further reduced.

Circuit elements 12 other than the semiconductor element 1 are mounted on the multilayer wiring board 2. These circuit elements 1
2 and the independent wiring provided on the rear surface of the multilayer wiring board 2 may be electrically connected using a through hole independent of the thermal via 3.

It is important that the cross-sectional area of each of the heat conducting members 4 is such that a temperature difference generated when heat is transferred to the thermal via 3 connected to each heat conducting member 4 is constant. The thermal resistance can be adjusted by increasing the cross-sectional area of the heat conductive member 4 having the longest distance from the substrate 1a to the thermal via 3.

Another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a semiconductor device having another embodiment of the present invention.

In FIG. 3, a PHS 7 made of a plating layer such as gold is provided between a semiconductor substrate 1a and a heat conducting member 4. When the semiconductor substrate 1a is not thick, the heat generated from the plurality of heat generating portions 1b located on the surface layer of the semiconductor substrate 1a does not sufficiently diffuse inside the semiconductor element 1, and the temperature distribution on the back surface of the semiconductor element 1 is uniform. do not become. For example,
In some cases, the temperature immediately below each of the heat generating portions 1b is high, and the temperature between the portions is low. Variations in the temperature distribution of a material that has no spatial distribution of thermal conductivity are equivalent to having a distribution in the heat flux passing through the material. For this reason, the amount of heat transmitted to the thermal vias 3 through the individual heat conducting members 4 is not uniform, and some thermal vias 3 may not function effectively. Therefore, it is desirable that the temperature distribution on the back surface of the semiconductor substrate 1a be as uniform as possible.

FIG. 3 is a graph showing the relationship between the amount of heat transmitted to the individual thermal vias 3 through the heat conducting member 4.
The PHS 7 is provided between the semiconductor substrate 1a and the heat conducting member 4. Even when the semiconductor substrate 1a is made thinner, the temperature distribution on the rear surface of the PHS 7 becomes a concentric temperature distribution in which the outer peripheral edge has the lowest temperature and the central portion has the highest temperature. Can be offset by the distribution of the plurality of heat generating regions 1b. This is P
The thermal resistance can be reduced because the positive effect of uniformly diffusing the heat by the PHS 7 is greater than the negative effect of increasing the thermal resistance by the thickness of the HS 7.
Also, it is possible to almost eliminate the need to adjust the arrangement of the portion of the heat conductive member 4 that contacts the semiconductor substrate 1a according to the arrangement of the heat generating portion 1b.

Another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a sectional view of a semiconductor device having another embodiment of the present invention.

In FIG. 4, on the back surface of the semiconductor substrate 1a,
A PHS 7 having a sectional area substantially equal to or larger than that of the semiconductor substrate 1a is provided. on the other hand,
A heat conductive member 10 is provided between the PHS 7 and the multilayer wiring board 2.
Is interposed. A brazing material is provided on both upper and lower surfaces of the heat conductive member 10, a first brazing material 9 is provided on the multilayer wiring board 2 side, and a second brazing material 11 is provided on the PHS side. The multilayer wiring board 2 is provided with a thermal via 3 having high conductivity and high thermal conductivity so as to penetrate the multilayer wiring board 2. These brazing materials 9 and 11 electrically and thermally connect the semiconductor substrate 1 a and the thermal via 3.

When the area of the thermal via 3 arranged in the multilayer wiring board 2 is larger than the area of the semiconductor element 1, the area of the heat conducting member 10 needs to be larger than the area of the semiconductor substrate 1a. If so, it is desirable to have an area that extends over all the thermal vias 3.

By using the PHS 7, the temperature distribution on the back surface of the PHS 7, ie, the surface facing the heat conducting member 10, can be made uniform, and the thermal resistance from the semiconductor element 1 to the heat conducting member 10 can be reduced. Can be. Further, since the heat conducting member 10 is a single plate-like member, the heat generating member 10 is generated at the heat generating portion 1b of the semiconductor element 1 at a lower cost than in the other embodiments of the present invention shown in FIG. The heat generated can be efficiently transmitted to the thermal via 3 having high conductivity and high heat conductivity disposed on the multilayer wiring board 2. For this reason, the thermal resistance between the heat conductive member 10 and the back surface of the wiring board 2 can be reduced, and the combination of the PHS 7, the heat conductive member 10, and the thermal via 3 can realize a low heat resistance structure at low cost.

It is desirable that the thickness of the heat conducting member 10 is larger than the thickness of the semiconductor substrate 1a and smaller than or equal to the thickness of the portion of the wiring substrate 2 through which the thermal via penetrates. As for the thicknesses of the semiconductor substrate 1a and the PHS7, it is desirable that the PHS7 be thinner. That is, the thicknesses of the portions of the semiconductor substrate 1a, the PHS 7, the heat conduction member 10, and the thermal via 3 of the wiring board 2 through which the thermal vias 3 pass are t1 and t, respectively.
Assuming that t2, t3, and t4, the relationship of t2 <t1 <t3 ≦ t4 holds in the semiconductor device according to the present embodiment. As an example, t2 = about 5 to 20 μm t1 = 30 to 50, maximum about 100 μm t3 = about 150 to 300 μm t4 = about 300 to 450 μm, but if the above relational expression is satisfied, it is not necessarily limited to the above range Needless to say, it will not be done. Also,
Assuming that the thicknesses of the first and second brazing materials and the thermal vias are t5, t6, and t7, respectively, the following relationship is established.
Adjust the thickness.

T2 ≦ t5 ≒ t6 ≦ t1 t4 = t7 On the other hand, the semiconductor substrate 1a, the PHS7, the heat conductive member 10, the base material of the wiring board 2, the first brazing material 9, the second brazing material 11,
The thermal conductivity of the thermal via 3 is λ1, λ2, λ, respectively.
3, λ4, λ5, λ6, λ7, and the linear expansion coefficients are α1, α2, α3, α4, α5, α6, α7, respectively.
In the present embodiment, the materials are selected such that the following relationship is satisfied.

Λ4 <λ5 ≒ λ6 ≒ λ1 <λ2 ≒ λ3 ≒ λ7 α6 ≦ α1 <α2, α4 ≒ α7 <α3, α6 <α3 Here, the symbol 意味 means that the physical property values are almost in the same order. This means that we do not always care about magnitude relations. That is, the thermal resistance increases in the order of the base material of the wiring board 2, the various brazing materials, the semiconductor substrate 1a, and the various heat conducting / thermal diffusing members. When the semiconductor substrate 1a has a thermal conductivity equal to or higher than that of Si (λ1λ100 [W / (m at 373K (100 ° C.)).
.K)] or more), and the relationship between the thermal conductivity of the semiconductor substrate 1a and the thermal conductivity of the brazing materials 9, 11 is λ5 ≒ λ6 <λ1.
It does not matter.

Regarding the coefficient of linear expansion, the coefficient of linear expansion of the second brazing material is the lowest, that of the semiconductor substrate 1a is equal to or higher, and that of the PHS 7 is very high. With respect to the members below the second brazing material, the base material of the wiring board 2 and the thermal vias 3 are substantially equal, and the coefficient of thermal expansion of the heat conductive member 10 is high.

In the embodiment shown in FIG. 4, it is conceivable that the material of the semiconductor substrate 1a is a semiconductor substrate made of a Si-based single crystal or a GaAs-based compound.
In addition, as a material of the heat conductive member 10, a metal such as copper, aluminum, and molybdenum, or an alloy containing them as a main component can be considered. However, as long as the heat resistance can be set to a target value or less, the above materials are not necessarily used. You don't have to. On the other hand, the first brazing material 9 is preferably made of a material such as solder, and the second brazing material 11 is made of a conductive silver paste or the like, has conductivity, and has a thermal conductivity substantially equal to that of the semiconductor substrate 1a. A thermosetting material is desirable.

In the present embodiment, the melting point of the first brazing material 9 is higher than the curing temperature in the manufacturing process of the second brazing material 11, and the semiconductor element 1 is fixed on the second brazing material 11 via the PHS 7. In this case, a material having physical properties such that the first brazing material 9 is not melted is selected. One of the reasons for using the conductive silver paste material is that the base material of the paste material is a thermosetting resin. The thermal stress generated at the interface between the heat conductive member 10 and the second brazing material 11 or at the interface between the PHS 7 and the second brazing material can be reduced. Further, the thermal stress at the interface between the PHS 7 and the semiconductor substrate 1 a generated by the heat generation operation after the second brazing material is cured can be reduced by making the PHS 7 sufficiently thin.
It can be alleviated by the yield and deformation of the gold plating layer.

FIG. 5 shows the semiconductor substrate 1a and the thermal via 3
Are connected via the brazing material 9.

FIG. 6 shows an embodiment in which the semiconductor substrate 1a and the wiring board 2 are connected via a heat diffusion plate 13.

FIG. 7 shows that the thermal via 3 is a semiconductor substrate 1a.
An embodiment of the present invention, which has a size equal to or larger than the size and is formed of an integrally molded product, is shown.

Another embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a sectional view of a semiconductor device provided with the present invention. 9 is a perspective view in which a part thereof is cut out, and FIG. 10 is a top view (FIG. 10a) and a bottom view (FIG. 10b) of the wiring board 2 and a cross-sectional view including the semiconductor element 1 (FIG. 19).
c).

A semiconductor device to which the present invention is applied as shown in FIG. 8 has a plurality of types of semiconductor elements 16 on a single wiring board 2.
17 is implemented. The semiconductor element 16 is made of GaAs
A heat generating portion 16b is formed on a semiconductor substrate 16a having a relatively low thermal conductivity such as a system, and the semiconductor substrate 16 having a relatively small thickness is formed.
The PHS 7 is formed on the back surface of a by plating or the like.
On the other hand, in the semiconductor element 17, a heat generating portion 17b is formed on a semiconductor substrate 17a having a relatively high thermal conductivity such as a Si type.
When the thermal conductivity of the semiconductor substrate 17a is substantially equal to or higher than the thermal conductivity of the Si-based material, the temperature distribution on the back surface of the semiconductor substrate 17a can be made substantially uniform by setting the thickness of the semiconductor element 17a to about several hundred μm. Therefore, the target value of the thermal resistance can sometimes be achieved without using the PHS 7 or the above-described heat conducting member 10. In such a case, as shown in FIG.
Since the semiconductor substrate 17 can be directly mounted on the wiring board 2 via the second brazing material 11 on the wiring board 2, the cost can be reduced.

In FIG. 8A, the surface layer 2a of the multilayer wiring board is shown.
Includes a wiring element 101 in addition to the semiconductor devices 16 and 17;
Circuit components 12 such as resistors and chip capacitors are mounted. The wiring element 101 or the circuit component 12 and the semiconductor elements 16 and 17 are electrically connected by, for example, bonding wires 18.

Although not shown in the cross-sectional view of FIG. 8A, the combination of the wiring elements, the through holes, and the semiconductor elements 16 and 17 in each layer of the multilayer wiring board 2 operates as, for example, a high-frequency power amplifier for a portable communication terminal. One semiconductor device (hereinafter, module) is configured. FIG.
In the case of a, the GNDs of the semiconductor elements 16 and 17 are PHS7,
It is electrically and thermally connected to the GND wiring layer 102 on the motherboard 8 via the heat conductive member 10, the thermal via 3, and the GND wiring layer 5 formed on the back surface 2b of the multilayer wiring board.

Further, electrodes 103 for input / output signals are also formed on the back surface 2b of the multilayer wiring board, and between the electrode 103 and the wiring elements 101 and circuit elements 12 on the surface layer 2a of the multilayer wiring board or between the layers, the wiring board 2 is provided. It is electrically connected by a wiring 104 formed as a through hole on the side surface or inside. Wiring layers 105 corresponding to the electrodes 103 are respectively formed on the motherboard 8, and the electrodes 103 and the wiring layers 105 are electrically connected. These wiring layers 5
For the connection between the electrode 103 and the wiring layers 102 and 105, a third brazing material 106 such as low-melting solder is used.

In the above structure, the first brazing material 9 is a solder, the second brazing material is a thermosetting conductive paste material, and the third brazing material is a solder. , T2, and T3. First, the heat conductive member 10 and the semiconductor device 17 are mounted on the surface layer 2a of the multilayer wiring board, then the semiconductor device 16 is mounted on the heat conductive member 10, and the rear surface 2 of the multilayer wiring board in the completed module is mounted on the mother board 8. Considering the process, materials are selected so that T1>T2> T3.

In the case where the heat generation amount of the heat generating portion 17b formed on the semiconductor substrate 17a is sufficiently small and the semiconductor substrate 17a is made of a material having a high thermal conductivity such as Si, the PHS 7 In some cases, even without the conductive member 10, the thermal resistance can be reduced to the target upper limit or less, and in such a case, there is no need to use the PHS 7 or the thermal conductive member 10. Therefore, when a plurality of chips are mounted on one multilayer wiring board 2, it is necessary to select an optimal configuration in terms of heat and cost from the physical property values and heat generation values of the semiconductor substrate constituting the chip. Can be. Assuming that the thickness of the semiconductor element 16 is t1 as it is, the thickness of 17 is t9, and the thickness of the circuit component 12 excluding a chip resistor formed by a microstrip line is t8, t1 <t8 and The relationship t1 <t9 holds. The relationship between t8 and t9 does not need to be particularly limited.

Regarding the wiring element 5 on the rear surface 2b of the wiring board, the semiconductor element 16, 17 may be configured to form a common circuit, or may be configured not to short-circuit each other. There is no particular problem as long as the functions of the entire apparatus can be secured.

FIG. 8B shows a case where the semiconductor element 17 is mounted face down (flip chip mounting). In this case, input / output signals and the like to / from the semiconductor element 17 are transmitted through the through hole 110 inside the multilayer wiring board 2 and the wiring layer 11.
1 to the semiconductor element 17 or output from the semiconductor element 17. A CCB is provided between the circuit network on the surface layer of the semiconductor element and the multilayer wiring board 2 via solder bumps 112 and the like.
Connected. In the sectional view shown in FIG.
7b is directly connected to the thermal via 3 via the solder bump 112. That is, the solder bumps 112 play the role of the heat conducting member 4 in the embodiment of the present invention in FIG. Therefore, the heat released from the heat generating element 17b is effectively transmitted to the thermal via 3, and the heat resistance from the heat generating element 17b to the rear surface 2b of the multilayer wiring board can be reduced.

In the embodiment of the present invention shown in FIGS. 8A and 8B, the wiring layers 5 and the electrodes 103 formed on the back surface 2 of the multilayer wiring board are solid wirings, respectively, and are formed on the motherboard 8 together with these. Wiring layers 102 and 105
Is joined by a third brazing material 106,
One embodiment of the present invention includes a case where the brazing material 113 such as solder is arranged under the multilayer wiring board back surface 2b in a grid pattern and joined to the motherboard 8 by so-called BGA joining. FIG. 8C is a cross-sectional view showing the case where the semiconductor device 17 is mounted as described above. However, the semiconductor element 17 may or may not be flip-chip mounted.

FIG. 9 is a perspective view in which a part of a semiconductor device to which the present invention is applied is cut out. When the whole semiconductor device is sealed with a cap 107 or the like and a circuit portion is protected, an electrical connection to the motherboard 8 is made. Since the connection portion is only the side surface and the back surface of the portion where the cap 107 does not cover, for example, the electrodes 103 on the back surface are independent electrodes,
Numerals 8 only need to be assigned different roles, such as electrodes of the GND wiring layer 5 that short-circuit with the thermal via 3.

FIG. 10 is a top view (FIG. 10a) of the semiconductor device used in the embodiment of the present invention shown in FIG. 4 or 8a and 9 with the cap 107 removed, and a cross-sectional view through the semiconductor element 16 (FIG. 10a). 10B) is a bottom view (FIG. 10C) of the back surface 2 of the multilayer wiring board viewed from below. FIG.
In the case of 0, the circuit is formed only on a part of the surface layer 2a of the multilayer wiring board. However, even if the circuit is formed by effectively using the entire surface, the essence of the present invention is not spoiled.

As shown in FIG. 10A, when the circuit element 12 is isolated on the surface layer or when the wiring layer 101 is interrupted on the way, actually, the wiring A circuit network is formed and electrically interconnected via through holes and the like to constitute one product as a whole module.

FIG. 10B shows an example of a wiring pattern on the back surface 2b of the multilayer wiring board. Even if the GND wiring layer 5 directly connected to the thermal via 3 is a solid wiring, or a solder ball grid array, (BG
A) Of course, it does not matter. Independent electrode 10
Numerals 3 each constitute a signal input / output electrode or the like.

From the viewpoint of protection of the element, the cap 1
The space inside 07 may be filled with a protective member 109 such as a resin.

FIG. 11 shows an example of a module manufacturing process of the semiconductor device according to the embodiment of the present invention shown in FIG. 4 or FIG.

In FIG. 11, high melting point solder is printed or applied as a first brazing material 9 at a predetermined position on the wiring board 2. Next, parts 1 such as chip capacitors and resistors
2 and the heat conductive member 10 are first mounted on the position where the first brazing material 9 is printed or applied, and the component 12 and the heat conductive member 10 are mounted in a reflow and cleaning process. Next, a second brazing material 11 such as a conductive silver paste is applied to a predetermined position, and the semiconductor device 1 or 16 having the PHS 7 or the PH
The semiconductor element 1 or 17 not using the S structure 7 is mounted thereon, and is lower than the melting point of the first brazing material 9 and the second brazing material 1
1 at a temperature high enough to cure the second brazing material 11
Bake and wash. Further, the semiconductor element 1 or 16 or 17 is connected to a predetermined position of the wiring board 2 by wiring 18 by wire bonding or the like, and a member 109 for protecting the semiconductor element is applied and fixed, and then a cap 107 is attached. Further, the wiring board 2 is divided for each unit semiconductor device, and a semiconductor device that has passed the inspection process is completed. In this step, the first brazing material 9 and the second brazing material 1
1. The member 109 for protecting the semiconductor element is made of a material whose melting point or curing temperature gradually decreases in the order of the steps.

The mounting of the module on the motherboard 8 may be performed in the following manufacturing process, or the module may be shipped to the customer in the state of the module and mounted on the customer. In this case, the magnitude relationship between the melting point T3 of the third brazing material 106 in FIG. 8 and the melting points or curing temperatures of the other brazing materials and the protective members must be as described above. T
The value of 3 may be instructed in advance, or conversely, other appropriate values for T1 and T2 may be selected according to T3.

FIG. 12 shows that the semiconductor substrate 1 or 16 is made of GaAs.
FIG. 4 is a schematic cross-sectional view of the vicinity of the heat generating portion 1b when a hetero bipolar transistor (hereinafter, HBT) is formed on the s-based substrate 21.

In FIG. 12, semi-insulating GaAs is formed on the heat conductive member 10 via the second brazing material 11 and the PHS 7.
A system board 21 is mounted. On a GaAs substrate 21, a sub-collector layer 22, a collector layer 23, a base layer 2
4, emitter layer 25, base electrode 26, cap layer 2
7, an emitter electrode 28, a collector electrode 29, interlayer insulating films 30 and 31, an emitter wiring layer 32, and the like are formed. G
A through-hole called a via hole 33 is formed at a predetermined position of the aAs-based substrate 21, and the PHS structure 7 and the emitter wiring layer 32 on the back surface of the GaAs-based substrate 21 are connected via the PHS 7 flowing into the via-hole 33. It is electrically connected. Further, the emitter wiring layer 32 and the via hole 3
In some cases, a resistor 34 called a ballast resistor is arranged in a part of the wiring between the first and third wires.

The heat generating portion 1b or 16b, 17b shown in FIG. 4 or FIG. 8 is a region through which current flows intensively between the individual base 24 and emitter 25 layers in FIG. Here, for simplification of the drawing, a structure in which there is only one heat-generating region is shown, but there may actually be a plurality of heat-generating regions. Further, the number of heat generating regions and the number of via holes 33 do not need to match. Generally, the number of via holes 33 is smaller than the number of heat generating regions.

In the structure shown in FIG. 12, the PHS 7 is electrically connected from the emitter wiring 32 via the via hole 33 to the back surface of the thermal via 3 in the wiring board 2. The wiring board 2 is further mounted on the motherboard. At this time, a wiring electrically connected to the emitter wiring in the wiring board 2, for example, the back wiring 5 in FIG. 10 is grounded to a common GND of the motherboard. The potential can be kept constant.

FIG. 13 shows GaAs as shown in FIG.
In the system-HBT element 1 or 16, there is shown an example of a layout diagram of the heat-generating region (finger) when the size of the heat-generating region (finger) 19 is 2 μm in width, 20 μm in length, and 16 × 8 = 128.

In FIG. 13, the semiconductor substrate 1 or 1
6, and the dimensions of the PHS7 are 0.9 mm or 1.0 mm square on one side, and the dimensions of the heat conducting member 10 are 1.4 mm or 1.3 mm squares on the side, or 2.4 mm long. The thermal vias 3 in the wiring board 2 each have a diameter of 0.15 mm.
Here, it is assumed that they are arranged at an equal pitch of 0.35 mm vertically and horizontally. The thickness, material, dimensions, and the like of the heat conducting member 10 which will be discussed in FIG.
13 and the results when optimization is performed based on the above criteria. The size and number of the fingers 19 strongly influence the absolute value of the thermal resistance between the heat generating region 1b and the rear surface 2b of the wiring board. It is clear from heat conduction analysis that the influence is not so strong.
For the qualitative evaluation of the effect of reducing the thermal resistance by the combination of the wiring board 2 having the thermal vias 3 and the PHS structure 7, it is almost sufficient to consider the dimensions and arrangement of the heat generating region in one case. Unless otherwise specified, it is assumed that the material of the heat conducting member 10 is copper and the PHS structure 7 is a gold plating layer. The thickness of the PHS structure 7 was 15 μm unless otherwise specified, and the thermal conductivity of the first brazing material 9 and that of the second brazing material 11 were equal, and the thickness was 30 μm. Is shown.

FIG. 14 shows a GaAs substrate 21 or Ga.
The relationship between the thickness of the heat conducting member 10 and the thermal resistance of the entire device (module) obtained by using the steady-state heat conduction analysis when the Si system is used instead of the As system is shown.

In FIG. 14, the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance. According to FIG. 14, regardless of the thickness of the substrate 21, the heat conducting member 10 is
By installing the module between the structure 7 and the wiring board 2, the module thermal resistance can be reduced.
The optimum value of the thickness is approximately 300 μm within the study range.
It can be seen that it is before and after. The reason that the module thermal resistance is smaller when the Si substrate is used is that the thermal conductivity of Si is higher than the thermal conductivity of GaAs. In addition, GaAs-HBT
In the case of the above-described power amplifier for a high-frequency device, the reason for adopting is to improve the output and to improve the high rate, which is a problem different from the problem of the thermal resistance.

FIG. 15 shows how the module thermal resistance changes depending on the combination of the dimensions of the GaAs substrate 21 or the semiconductor element 1 or 16 and the PHS structure 7 with the dimensions of the heat conducting member by a steady-state heat conduction analysis. The results are shown.

In FIG. 15, as in FIG. 14, the abscissa represents the thickness of the heat conducting member 10 and the ordinate represents the module thermal resistance. From this figure, it can be seen that the size of the semiconductor element 16 has little effect on the thermal resistance and the size of the heat conducting member 10 is large and affects the module thermal resistance. This is because the thermal via 3 in the wiring board 2 is
When the heat conductive member 10 is arranged in a wider area than the area of the semiconductor element 16, the area of the heat conductive member 10 is made larger than that of the semiconductor element 16 so that the heat generated in the heat generating region 8 can be released to the thermal via 3 not directly below the semiconductor element 16. This shows that a structure that can be used can reduce the thermal resistance of the entire module.

From FIG. 14 and FIG. 15, the thickness of the heat conducting member 10 is at least about 100 μm or more and about 300 μm, and its area is larger than that of the semiconductor element 16 so as to extend over as many thermal vias 3 as possible. By adopting the proper dimensions, the module thermal resistance can be reduced. Also in the present invention, it is desirable that the heat conducting member 10 has the above-described structure.

FIG. 16 shows the relationship between the thickness of the PHS structure 7 and the module thermal resistance when the semiconductor element 1 or 16 is directly mounted on the wiring board 2 using the second brazing material 11 without the heat conductive member 10. The result of examining the relationship by steady-state heat conduction analysis is shown.

In FIG. 16, the horizontal axis represents the thickness of the PHS structure 7, and the vertical axis represents the module thermal resistance. From FIG. 16, in order to realize substantially the same reduction in thermal resistance without using the heat conducting member 10, the thickness of the PHS structure 7 must be 50 to 60 μm.
Or more. Although it is difficult to form a thick gold plating film as described above in terms of process and cost, the above structure may be employed if conditions permit.

FIG. 17 shows the result of examining the result when trying to reduce the thermal resistance by the effect of the heat conducting member 10 alone without the PHS structure 7.

In FIG. 17, the horizontal axis represents the thickness of the heat conducting member 10 and the vertical axis represents the module thermal resistance. From the figure, the optimum value of the thickness of the heat conducting member 10 is 300 μm as in FIGS.
m, but when the GaAs substrate 21 is used, PH
It can be seen that without the S structure 7, the thermal resistance is not sufficiently reduced. Therefore, PHS is applied to the GaAs substrate 21.
Structure 7 is essential. On the other hand, in the case of a Si-based substrate, if the thickness of the heat conducting member 10 is optimized, the module thermal resistance hardly changes even with or without the PHS structure 7. Therefore, there is no particular problem even if the PHS structure 7 is not provided for the Si-based control IC as in the embodiment of the present invention shown in FIGS. In the present invention, a PHS structure 7 is provided when a substrate 21 having a thermal conductivity of about 50 W / (m · K) or less, such as a GaAs substrate, is used. When a substrate of about 148 W / (m · K) or more is used, the configuration may be such that the PHS structure 7 is not provided. When the thermal conductivity of the substrate 21 is from about 50 to about 148, whether or not to use the PHS 7 and the thermal conductive member 10 can be selected according to the thickness and the calorific value.

FIG. 18 shows the results of a study on the relationship between the module thermal resistance and the thickness of the heat conducting member 10 when the material of the heat conducting member 10 is changed from copper to aluminum or molybdenum.

In FIG. 18, since aluminum or molybdenum has a lower thermal conductivity than copper, the effect of reducing thermal resistance cannot be obtained as much as copper. However, the thickness is also about 200 to 300 μm. , There is an optimum value of the thickness, and a slight thermal resistance reduction effect can be obtained. From this, as a material of the heat conductive member 10, whether the heat conductivity is the same as that of the semiconductor substrate 21,
Alternatively, it is necessary to select a higher material. If possible, it is desirable to select a material having a thermal conductivity equal to or higher than that of copper.

[0089]

According to the present invention, a semiconductor device capable of efficiently transmitting heat from a semiconductor element to the outside from a multilayer wiring board without increasing the thickness of a semiconductor substrate can be provided at low cost. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device having a basic embodiment according to the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device having a thermal via that does not penetrate a wiring board according to the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device having a PHS according to the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device having a heat conducting member between a PHS and a thermal via according to the present invention.

FIG. 5 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 8 is a cross-sectional view of a semiconductor device according to the present invention in which a plurality of types of semiconductor elements are mixedly mounted on one wiring board.

FIG. 9 is a perspective view of a part of a semiconductor device to which the present invention is applied;

FIG. 10 is a diagram showing a top surface and a bottom surface of a semiconductor device in which a plurality of types of semiconductor elements according to the present invention are mounted together on one wiring board.

FIG. 11 is a view showing an example of a process step in which a semiconductor element according to the present invention is mounted on a wiring board;

FIG. 12 is a cross-sectional view of a semiconductor device showing a periphery of a typical emitter electrode when a semiconductor element according to the present invention is an HBT element;

FIG. 13 is a schematic top view showing an example of the arrangement of heat generating regions according to the present invention.

FIG. 14 is a graph showing the effect of the thickness of the heat conducting member on the module thermal resistance in the present invention.

FIG. 15 is a graph showing the effect of the area of the heat conduction member on the module thermal resistance in the present invention.

FIG. 16 is a graph showing the effect of the PHS thickness on the module thermal resistance in the case where a heat conducting member is not used in the present invention.

FIG. 17 is a graph showing the effect of the thickness of a heat conducting member on module thermal resistance in the absence of PHS in the present invention.

FIG. 18 is a graph showing the effect of the type of heat conducting member on module thermal resistance in the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 1a ... Semiconductor substrate, 1b ... Heating area,
2 Wiring board, 2a Wiring board surface layer, 2b Backside of wiring board, 3 Thermal via, 4 Thermal conduction member, 5 Wiring element, 6 Thermal via not penetrating inside wiring board, 7 P
HS, 8: mother board, 9: first brazing material, 10: heat conductive member, 11: second brazing material, 12: circuit component, 13
... heat diffusion plate, 15 ... brazing material, 16 ... semiconductor element composed of a material having low thermal conductivity, 16a ... semiconductor substrate, 16b
... Heating region, 17: Semiconductor element composed of a material having high thermal conductivity, 17a: Semiconductor substrate, 17b: Heating region, 1
8: wire wiring, 19: finger, 21: semiconductor substrate, 22: subcollector, 23: collector, 24: base, 25: emitter, 26: base electrode, 27: cap layer, 28: emitter electrode, 29: collector electrode , 30
... insulating layer, 31 ... insulating layer, 32 ... emitter wiring, 33 ...
Via hole, 34: Ballast resistance, 35: Cap,
36 ... electrode, 37 ... electrode, 101 ... wiring layer, 102 ... wiring layer, 103 ... electrode, 104 ... wiring layer, 105 ... electrode,
106: third brazing material, 107: cap, 108: electrode, 109: protective member, 110: through hole, 111
... wiring layer, 112 ... solder bump, 113 ... solder bump.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasunari Umemoto 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Chushiro Kusano Gojomisho, Kosumi-shi, Tokyo No. 20-1, Hitachi Ltd. Semiconductor Group (72) Inventor Kiyoshi Yamashita 1-280, Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shizuo Kondo Waterworks, Kodaira-shi, Tokyo 5-2-1, Honcho, Hitachi, Ltd., Semiconductor Group, Ltd. (72) Inventor Sakae Kikuchi 5--20-1, Josuihonmachi, Kodaira-shi, Tokyo In-house, Hitachi, Ltd. Semiconductor Group (72) Inventor, Satoshi Sasaki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Hibi Komei 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Masaki Nakanishi 190 Kashiwagi, Komoro-shi, Nagano F-term in Hitachi Eastern Semiconductor Co., Ltd. 5F036 AA01 BB08 BB21

Claims (7)

[Claims] A semiconductor device mounted on the wiring board; a first heat conductive member disposed in the wiring board and provided through the semiconductor substrate in a thickness direction; A semiconductor device comprising: a second heat conductive member for thermally connecting the first heat conductive member to the first heat conductive member. 2. A semiconductor device mounted on a wiring board, a first heat conductive member disposed in the wiring board and provided through the semiconductor substrate in a thickness direction, A semiconductor device comprising a heat diffusion plate provided between a heat conduction member and the semiconductor element, and a second heat conduction member for thermally connecting the heat diffusion plate and the first heat conduction member. . 3. A semiconductor device mounted on a wiring board, a first heat conductive member disposed in the wiring board, and provided through the semiconductor substrate in a thickness direction, A heat diffusion plate provided between the heat conduction member and the semiconductor element and having an area equal to or larger than the area of the semiconductor element; and thermally connecting the heat diffusion plate and the first heat conduction member to each other. And a second heat conductive member having an area equal to or larger than the area of the semiconductor element. 4. The semiconductor device according to claim 1, wherein said semiconductor element is a single crystal semiconductor substrate such as Si or GaAs.
A semiconductor device in which a multi-finger element including a plurality of transistors or diodes is formed on a compound semiconductor substrate such as 5. The semiconductor device according to claim 1, wherein said second heat conductive member disposed between said semiconductor element and said wiring board is made of a material having a higher thermal conductivity than said semiconductor element. . 6. The semiconductor device according to claim 2, wherein said second element is disposed between said semiconductor element and a wiring board.
A semiconductor device, wherein both the heat conductive member and the heat diffusion plate disposed between the semiconductor element and the second heat conductive member are made of a material having higher heat conductivity than the semiconductor element. 7. The semiconductor device according to claim 3, wherein the thickness of the semiconductor element, the second heat conducting member, and the heat diffusing plate is thinnest for the heat diffusing plate and thickest for the second heat conducting member. Semiconductor device.