JP2001102520A - Pressure contact type semiconductor device - Google Patents

Abstract

(57) [Summary] The present invention can reduce the inductance component of wiring and improve the stability of switching operation. SOLUTION: An emitter electrode plate 30 having a plurality of protrusions 31, a printed circuit board 40 fixed to the emitter electrode plate between the respective protrusions, and an insulating film formed only on one surface of the printed circuit board and near a fixed portion. An emitter detection wiring layer 43 exposed from the substrate and in contact with the emitter electrode plate; a gate wiring layer formed on the other surface of the printed circuit board and having substantially the same shape as the emitter detection wiring layer; A plurality of pressure contact pins 32 erected near each convex portion while insulated from the plate, and a collector electrode plate 60 disposed opposite to the emitter electrode plate and a pressure contact with each convex portion of the emitter electrode plate. And a plurality of semiconductor chips each having a gate electrode pressed into contact with each of the press contact pins.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type semiconductor device in which a plurality of insulated gate type semiconductor chips such as IGBTs are incorporated in the same package, and more particularly to a pressure contact type semiconductor device capable of improving the stability of switching operation. Related to the device.

[0002]

2. Description of the Related Art Conventionally, when operating an insulated gate semiconductor element such as an IGBT with a large current, a press-contact type semiconductor device in which a plurality of semiconductor chips are connected in parallel and incorporated in a package has been widely used. .

FIG. 12 is a plan view of an emitter electrode of this type of press contact type semiconductor device as viewed from the inside of a package. The emitter electrode 1 is surrounded by an insulating envelope 3 holding a gate terminal 2, and a plurality of press-contacts arranged on the inner peripheral portion thereof so as to be in pressure contact with gate pads of respective semiconductor chips (not shown). A pin (= spring pin) 4 is provided. Each pressure contact pin 4 and the gate terminal 2 are connected in parallel by a plurality of lead wires 6 having a gate resistor 5.

On the other hand, as shown in FIG. 13, another insulating substrate 7 made of resin or ceramic having an opening in the inner peripheral portion of the envelope or the semiconductor chip array portion is provided on the collector electrode plate 8. There is also a structure in which a gate wiring network 7a thinly formed on the insulating substrate 7 and a gate pad 9g of each semiconductor chip 9 are bonded and connected via a wire 10.

[0005]

However, the above-described press-contact type semiconductor device has the following problems.
That is, in a structure in which each lead wire 6 is connected in parallel to the gate terminal 2, a gate resistor 5 or a thermistor for preventing oscillation is generally connected to each lead wire 6. However, the inductance component of the long lead wire 6 may cause the main current to vibrate or oscillate for each chip, thereby making the switching operation of each chip unstable.

On the other hand, in the structure in which the gate wiring network 7a and each semiconductor chip 9 are bonded and connected, the gate wiring network 7a
In a press-fit type package in which the inductance components of both a and the bonding wire 10 cannot be neglected and current oscillation is liable to occur, the switching operation of each chip may be similarly unstable.

[0007] These unstable switching operations cause current non-uniformity between chips, and in the worst case, 1
The entire current of the package is concentrated on one semiconductor chip, which causes element destruction. In addition, the unstable switching operation tends to appear significantly as the gate resistance decreases.

The present invention has been made in view of the above circumstances, and has as its object to provide a press-contact type semiconductor device capable of reducing the inductance component of wiring and improving the stability of switching operation.

[0009]

According to a first aspect of the present invention, there is provided an emitter electrode plate having a plurality of projections arranged in a grid, and an emitter electrode plate provided in the vicinity of each of the projections while being insulated from the emitter electrode plate. A plurality of pressure contact pins erected, a printed circuit board fixed to the emitter electrode plate between each of the projections and each pressure contact pin; and an insulating film selectively formed on one surface of the printed circuit board. An emitter detection wiring layer that is exposed from the insulating film only in the vicinity of each of the pressure contact pins and contacts the emitter electrode plate; and the emitter detection wiring layer selectively formed on the other surface of the printed circuit board. A gate wiring layer having substantially the same shape as the layer and electrically connected to each of the press-contact pins, a collector electrode plate disposed opposite to the emitter electrode plate, and a respective one of the collector electrode plate and the emitter electrode plate. With convex Are arranged in the same plane as the contact pressure, the is a pressure-contact type semiconductor device including a plurality of semiconductor chips having a gate electrode to be individually pressure contact with the respective press pins.

According to a second aspect of the present invention, in the press contact type semiconductor device according to the first aspect, the gate wiring layer has a length of a current path between a control signal input portion and each of the press contact pins. Are pressure-contact type semiconductor devices having the same size.

Here, the gate wiring layer can be formed as a symmetrical planar shape as a whole. Specifically, for example, a tree extending from a control signal input portion to each press contact pin through a plurality of branch portions is provided. It can be created as a planar shape. In this case, it is preferable that the number of branch portions is three or more from the viewpoint of increasing the capacity. Note that a linear planar shape having no branch portion may be symmetrically arranged as a whole.

Further, according to a third aspect of the present invention, in the press-contact type semiconductor device according to the first or second aspect, the gate wiring layer includes a press-contact type in which a resistor is inserted at least for each of the semiconductor chips. Semiconductor device.

Here, the term "at least" means that a resistor can be appropriately inserted in the middle of a current path other than in the vicinity of each semiconductor chip. In this case, as approaching the control signal input portion from each press contact pin side through the branch portion, a resistor having a small value is inserted, contrary to the increase in the current value.

According to a fourth aspect of the present invention, in the press-contact type semiconductor device according to any one of the first to third aspects, the emitter detection wiring layer is in contact with the emitter electrode plate. A press-contact type semiconductor device in which a resistance value in a current path from a portion to an end of the printed circuit board is higher than a resistance value in a thickness direction excluding a projection of the emitter electrode plate.

Here, the resistance value of the emitter detection wiring layer is:
Although it is defined regardless of the presence or absence of the resistor, it is preferable to insert a resistor of the same degree at the same position as the gate wiring layer, for example, from the viewpoint of ease of design (however, excluding the resistance of each semiconductor chip). .

(Operation) Therefore, in the invention corresponding to claim 1, by taking the above means, the emitter detection wiring layer for detecting the emitter potential is directly connected to the emitter electrode plate in the immediate vicinity of the chip. In addition, the inductance component of the wiring can be reduced, and the stability of the switching operation can be improved.

In addition, since the emitter detection wiring layer and the gate wiring layer are arranged in parallel with each other, the influence of inductance on currents flowing in opposite directions can be reduced, and the above-described operation can be further improved. .

According to a second aspect of the present invention, the length of the current path between the control signal input portion and each of the press-contact pins is equal to each other as the gate wiring layer. In addition, each semiconductor chip can be controlled more uniformly and easily.

Further, in the invention according to claim 3, since a resistor is inserted at least for each semiconductor chip as a gate wiring layer, in addition to the action according to claim 1 or 2, it is easy and reliable. In addition, control stability for each semiconductor chip can be improved.

According to a fourth aspect of the present invention, in the emitter detection wiring layer, the resistance value in a current path from a portion in contact with the emitter electrode plate to an end of the printed circuit board is a convexity of the emitter electrode plate. Since the resistance value is higher than the resistance value in the thickness direction excluding the portion, in addition to the action corresponding to any one of claims 1 to 3, the main current can be prevented from flowing into the emitter detection wiring layer, and the detection operation can be performed safely. Nature can be secured.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Before that, a gate drive system to which a press-contact type semiconductor device according to the present invention is applied will be described. This gate drive method has recently been considered by the present inventors. In addition to reducing the inductance component Lg of the gate wiring, which has conventionally been a problem, the gate resistance is reduced to reduce the switching loss. ing.
The common side is directly connected to the emitter of each semiconductor chip from the viewpoint of reducing the influence of the parasitic inductance LE caused by the wiring (including the emitter electrode plate) after the emitter electrode of the semiconductor chip. Also,
Gate resistance per 4 chips or chip effective area 1cm
It is less than 10Ω per ² .

FIG. 11 is a circuit diagram showing a gate drive circuit applied to this gate drive system and a driven semiconductor device. The gate drive circuit GD includes an inductance L that insulates the positive and negative DC power supplies 21 and 22 from the subsequent amplification units 23 and 24 and the like, a negative DC power supply 24 of the photocoupler 23, and a power supply (not shown). A photocoupler 23 that transmits a current signal received from a photocoupler drive circuit to a subsequent voltage amplifier 25 as a drive signal while electrically insulating the current signal from the photocoupler drive circuit
A voltage amplifying unit 25 for amplifying the voltage of the drive signal and supplying the amplified signal to a current amplifying (emitter follower) unit 26; a current amplifying unit 26 for amplifying the voltage-amplified drive signal and providing the same to an output unit 27; MOS based on the drive signal
An output unit 27 is provided that drives the FETs 1 and 2 to output a gate signal to the gate of the IGBT and that has a common Co point directly connected to the emitter of the IGBT.

In the above configuration, the Co point on the common side is set to IG
By reducing the parasitic inductance LE of the emitter wiring by directly connecting to the emitter of the BT, the effective gate potential between the emitter and the gate is not changed, and
A predetermined gate potential can be applied between the gates.
The present invention is a press-contact type semiconductor device (the IGBT portion in FIG. 11) suitable for such a gate drive system, and aims to further reduce the inductance component. Hereinafter, description will be made sequentially. FIG. 1 is a perspective view showing an assembly configuration of a press-contact type semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a plan view showing an internal configuration of the press-contact type semiconductor device. FIG. 3 is a plan view showing the configuration of both sides of a printed circuit board used in this press-contact type semiconductor device, and FIG. 4 is a sectional view taken along line 4-4 in FIG. FIG. 5 is a perspective view showing a connection structure between the printed circuit board and the press contact pins.
FIG. 6 is a sectional view taken along line 6-6 of FIG. 2 (including the collector electrode plate and the like).

As shown in FIGS. 1 and 2, this press-contact type semiconductor device is configured such that each of the protrusions 31 and 16 press-contact pins 32 arranged in a lattice form The printed circuit board 40 in which 16 openings 41 are arranged in a lattice so as to pass through the portions 31 and the press-contact pins 32 is fixed so as to be located between the convex portions 31. In addition, each convex part 31 and each press contact pin 32 are divided into four blocks from the viewpoint of ensuring the symmetry of the current path, and in each block, each press contact pin 32 is arranged so as to concentrate on the middle side. I have.

Here, the printed circuit board 40 is 0.5 mm
A double-sided substrate having a wiring pattern of copper foil on both sides of glass epoxy or the like having a thickness of, in the gate drive method described above, the wiring layer for gate drive and the wiring layer for emitter potential detection as parallel conductors Is formed.

Specifically, as shown in FIG. 3A, a gate wiring layer 42 indicated by a hatched pattern including resistors r1 to r4 is formed on a surface facing the collector electrode plate 60. The gate wiring layer 42 is formed in a symmetrical planar shape such as an H-type so as to make the wiring length (current path length) from the external gate electrode terminal side 42t to the four blocks equal. Further, in the gate wiring layer 42, a resistance r can be inserted into, for example, a branch portion of the wiring from the viewpoint of reducing the influence of inductance.

Each of the resistors r1 to r4 is provided at least for each press contact pin (= for each semiconductor chip), and has a smaller resistance value as it approaches the external gate electrode terminal side 42t on the current path (r1). <R2 <r3 <r4). This becomes closer to the external gate electrode terminal side 42t,
This is because it is necessary to reduce the voltage drop due to the current before the branch that flows more than after the branch.

For example, the resistance r1 of each press contact pin 32 is 1
Ω, and the resistance r3 after branching from the gate electrode terminal side 42t into two lines is set to a value smaller than 1Ω, such as about 0.5 to 0.1Ω, and The resistance r4 is set to a smaller value. However, when the resistance r4 of each press contact pin 32 is provided with an appropriate value, the other resistances r1 to r3 in the wiring layer 32 may be omitted as appropriate.

As shown in FIG. 3B, the printed circuit board 40 has an emitter, which is insulated from the gate wiring layer 42 and has substantially the same shape as the gate wiring layer 42, on the surface in contact with the emitter electrode plate 30. The detection wiring layer 43 is formed. In the emitter detection wiring layer 43, the resistors re2 to re4 are inserted similarly to the gate wiring layer 42 from the viewpoint of mitigating the influence of the fluctuation of the potential due to the large current flowing in the emitter electrode plate 30 (however, the pressure welding is performed). Excluding the resistance of each pin). The resistances re2 to re4 have the same resistance values as the resistances r2 to r4 in the gate wiring layer 42 disposed facing each other. Also, the emitter detection wiring layer 43 is
Except for the contact portion 43a made of solder or the like located in the vicinity (and in the vicinity of the screw hole 44), the entire region including the resistors re2 to re4 is covered with the protective insulating film 45.

That is, the printed circuit board 40 is
As shown in a section taken along line -4, when the emitter detection wiring layer 43 is fixed to the emitter electrode plate 30 by the screws 46,
Is in contact with the emitter electrode plate 30. The contact portion 43a may be formed so as to surround the screw hole 44. In this case, when a washer or the like is inserted between the contact portion 43a and the emitter electrode plate 30 and screwed, a contact between the contact portion 43a and the emitter electrode plate can be obtained more reliably.

After the printed circuit board 40 is fixed with the screws 46, as shown in FIG. 5, the wiring region 42a located at the end of the gate wiring layer 42 beyond the resistor r2 and each pressure contact pin 32 are connected to each other. They are electrically connected via the wiring 47.
Each press contact pin 32 is insulated from each protrusion 31 and the emitter electrode plate 30 by each insulator 32a.

In this state, as shown in FIG. 6, a rectangular cylindrical envelope 50 is fixed to the outer peripheral side of the emitter electrode plate 30.
Each of the emitter-side thermal buffer plates 4 made of Mo or the like on each of the convex portions 31
The semiconductor chip 70 is mounted on each emitter-side thermal buffer plate 48 in a direction in which the gate pad is brought into contact with the press-contact pin 32. Further, a collector-side thermal buffer plate 61 made of Mo or the like is mounted on all the semiconductor chips 70, and the collector electrode plate 60 is fixed on the envelope 50 so as to press the collector-side thermal buffer plate 61.

According to the above structure, as shown in FIG. 7A, the gate wiring layer 42 and the emitter detection wiring layer 4
3 is formed. As shown in the figure, since the emitter detection wiring layer 43 for detecting the emitter potential is directly connected to the emitter electrode plate 30 at the contact portion 43a, the emitter potentials of all the semiconductor chips 70 can be accurately taken out. 7B, the influence of the parasitic inductances Lg and LE due to the gate wiring 6 and the emitter wiring and the like can be reduced to reduce vibration and oscillation, and a stable gate drive voltage can be reduced.
0 can be applied.

As a result, the semiconductor chips 70 arranged in the same package perform a uniform and stable switching operation, so that abnormal operation, failure, and destruction of the semiconductor element can be prevented, and reliability can be improved.

In addition, the emitter detection wiring layer 43 and the gate wiring layer 42 are arranged in parallel with each other,
The influence of the (mutual) inductance on the current flowing in different directions can be reduced, and the reliability can be further improved.

Further, since no closed loop exists in both the emitter detection wiring layer 43 and the gate wiring layer 42, currents having the same magnitude and opposite directions can flow through both wiring layers 43 and 42. As a result, even if the gate current is large,
The gate-emitter voltage of each semiconductor chip 70 can be made uniform.

Further, since the resistor r1 is inserted into the gate wiring layer 42 at least for each semiconductor chip 70, the control stability of each semiconductor chip 70 can be improved easily and reliably.

Further, as the emitter detection wiring layer 43,
Since the resistance value in the current path from the contact portion 43a with the emitter electrode plate 30 to the end of the printed circuit board 40 is higher than the resistance value in the plate thickness direction excluding the protrusion 31 of the emitter electrode plate 30, the emitter The main current can be prevented from flowing into the detection wiring layer 43, and the safety and accuracy of the detection operation can be ensured.

Further, since the gate wiring is formed on the printed circuit board 40, the wiring is easy, the possibility of disconnection or short circuit is reduced, and the reliability on the wiring surface can be improved. In addition, it is possible to prevent a wiring position shift or the like during transportation, and to perform stable gate driving.

Further, since the printed circuit board 40 is disposed on the side of the emitter electrode plate 30, it is sufficient that insulation against a low voltage is obtained, and it can be easily realized.

Further, the wiring pattern can have an arbitrary planar shape by observing a simple design standard that the current paths from the gate electrode terminal side 42t to the respective press contact pins 32 are almost equal in length. It is possible to easily cope with an increase in the number of 70s.

In the case of this embodiment, for example, a pattern may be used in which the center of a new H-type (or I-type) is connected to the four corners (or two corners) of the H-type. This type of deformation pattern may be created (or added) while being aware of the symmetrical shape from the beginning as illustrated, and an arbitrary wiring pattern may be formed with point symmetry (rotation) or mirror symmetry (bending). It may be created while expanding based on. Since the design standard is simple, it can be easily transformed into a large number of wiring patterns. However, it goes without saying that any wiring pattern may be included in the scope of the present invention as long as the wiring pattern satisfies the aforementioned design criteria.

(Second Embodiment) Next, a press-contact type semiconductor device according to a second embodiment of the present invention will be described.
The same elements as those in the above-described drawings are denoted by the same reference numerals, and detailed description thereof will be omitted. Here, different parts will be mainly described.

That is, the present embodiment is a modification of the first embodiment, in which the wiring pattern of the printed circuit board 40 is changed.

Here, the printed circuit board 40 is formed as shown in FIG.
8 shows the gate wiring layer 42, and FIG. 8B shows the emitter detection wiring layer 43. The position of the screw hole 44 has been changed to a substantially central portion of the printed circuit board 40. The position of the contact portion 43a of the layer 43 is also the screw hole 4.
4 has been changed.

With the above configuration, the same operation and effect as in the first embodiment can be obtained. In the present embodiment, the wiring pattern of the printed circuit board 40 may be modified as shown in FIGS. That is, FIG.
As shown in (a) and (b), the gate wiring layer 42 and the emitter detection wiring layer 43 may be each divided into two to form a T-shaped equal-length wiring. In this case, each semiconductor chip 70 can be driven every eight chips by using two gate drive circuits GD. Also, the terminal side 42t of each gate drive circuit GD
The current paths from to the respective semiconductor chips 70 have the same length. The values of the resistors r1, r3, r4 are
It has been reset as appropriate.

As shown in FIGS. 10A and 10B, the wiring pattern shown in FIG. 9 is further dispersed, and each semiconductor chip 70 is divided into four chips by using four gate drive circuits GD. It may be configured to be drivable.

Even with such a modification, the same operation and effect as in the first embodiment can be obtained.

The above embodiments and modifications have been described by taking an IGBT chip as an example of an insulated gate semiconductor element. However, the present invention is not limited to this. For example, another insulated gate type device such as a MOSFET chip or an IEGT chip may be used. Even when the present embodiment is applied to a semiconductor element, the same effects can be obtained by implementing the present embodiment in the same manner.

Further, in each of the above-described embodiments and modifications, a case has been described in which all of the plurality of semiconductor chips 70 are switching elements. However, the present invention is not limited to this. Also, even in the case of using a diode chip in an anti-parallel manner, the present invention can be implemented in the same manner to realize an inverter circuit having the same effect.

In this case, each diode chip may be arranged on the surplus convex portion 31 after the groups of the switching element chips are arranged symmetrically in the current path (however,
The press contact pins 32 have been removed). Further, from the viewpoint of shortening the length of the gate wiring layer 42 serving as the inductance Lg, it is preferable that the groups of the switching element chips are arranged on the outer peripheral side and the diode chips are arranged on the center side. Further, the configuration can be modified to include a diode chip in one group (for example, a group including four switching elements and three diode elements and one diode chip).

In each of the above-described embodiments and modifications, the case where the number of semiconductor chips 70 is 16 has been described. However, the present invention is not limited to this. The same effect can be obtained by implementing the same.

Further, each of the above embodiments and modifications is
The relationship between the contact portion 43a and the screw hole 44 is, for example, a relationship that is separated from each other in FIG. 3 and is shown as an integral relationship in the central portion of FIG. Alternatively, the relationship may be separated from each other at the center of FIG.

That is, if the contact portion 43a of the emitter detection wiring layer 43 is in contact with the emitter electrode plate 30 when the printed board 40 is fixed to the emitter electrode plate 30, what is the configuration around the contact portion 43a? , Is included in the scope of the present invention. This is the contact portion 43a
Even if the screw hole 44 is largely separated from the screw hole 44, it means that the screw hole 44 is included in the scope of the present invention. Because the contact part 43
If the contact hole 43a is formed in a protruding shape, even if the screw hole 44 is provided apart from the contact part 43a, the contact part 43a
This is because it comes into contact with.

In the above embodiments and modifications, the case where the printed circuit board 40 is fixed to the emitter electrode plate by screwing is described. However, the present invention is not limited to this, and fixing means other than screwing (fitting, etc.) is used. Even if fixed, the present invention can be implemented in the same manner and the same effect can be obtained.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0057]

As described above, according to the present invention, it is possible to provide a press-contact type semiconductor device capable of reducing the inductance component of the wiring and improving the stability of the switching operation.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an assembly configuration of a press contact type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the internal configuration of the press-contact type semiconductor device according to the embodiment;

FIG. 3 is a plan view showing the configuration of both sides of the printed circuit board in the embodiment.

FIG. 4 is a sectional view taken along line 4-4 of FIG. 2 in the same embodiment;

FIG. 5 is an exemplary perspective view showing a connection configuration between a printed circuit board and a press contact pin according to the embodiment;

FIG. 6 is a sectional view of the same embodiment taken along line 6-6 of FIG. 2;

FIG. 7 is an equivalent circuit diagram for explaining the effect of the embodiment in comparison with the related art.

FIG. 8 is a plan view showing the configuration of both sides of a printed circuit board applied to a press-contact type semiconductor device according to a second embodiment of the present invention.

FIG. 9 is an exemplary plan view showing a modified configuration of the printed circuit board according to the embodiment;

FIG. 10 is an exemplary plan view showing a modified configuration of the printed circuit board according to the embodiment;

FIG. 11 is a circuit diagram showing a gate drive circuit and a driven semiconductor device applied to the embodiment;

FIG. 12 is a plan view of an emitter electrode of a conventional pressure contact type semiconductor device as viewed from the inside of a package.

FIG. 13 is a plan view showing the internal configuration of a conventional pressure contact type semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 30 ... Emitter electrode plate 31 ... Convex part 32 ... Press-contact pin 32a ... Insulator 40 ... Printed circuit board 41 ... Opening part 42 ... Gate wiring layer 42a ... Wiring area 42t ... Gate electrode terminal side r1-r4, re 2-re 4. Resistance 43 ... Emitter detection wiring layer 43a ... Contact portion 44 ... Screw hole 45 ... Protective insulating film 46 ... Screw 47 ... Wiring 48 ... Emitter side heat buffer plate 50 ... Envelope 60 ... Collector electrode plate 61 ... Collector side heat buffer plate 70 ... Semiconductor chip

Claims (4)

[Claims] 1. An emitter electrode plate having a plurality of protrusions arranged in a lattice, a plurality of press-contact pins erected near each of the protrusions while insulating the emitter electrode plate, and each of the protrusions And a printed board fixed to the emitter electrode plate between the press contact pins, and selectively formed on one surface of the printed board, having an insulating film on the surface, and only the area near the press contact pins. An emitter detection wiring layer exposed from an insulating film and in contact with the emitter electrode plate; and selectively formed on the other surface of the printed circuit board and having substantially the same shape as the emitter detection wiring layer; A gate wiring layer electrically connected to the collector electrode plate, a collector electrode plate disposed opposite to the emitter electrode plate, and a same plane so as to be in pressure contact with each of the convex portions of the collector electrode plate and the emitter electrode plate. Arranged in And a plurality of semiconductor chips each having a gate electrode that is individually press-contacted with each of said press-contact pins. 2. The pressure contact type semiconductor device according to claim 1, wherein the gate wiring layer has a current path length between a control signal input portion and each of the pressure contact pins equal to each other. Type semiconductor device. 3. The pressure-contact type semiconductor device according to claim 1, wherein a resistor is inserted into at least each of the semiconductor chips in the gate wiring layer. 4. The pressure contact type semiconductor device according to claim 1, wherein the emitter detection wiring layer extends from a portion in contact with the emitter electrode plate to an end of the printed circuit board. Wherein the resistance value in the current path up to the current path is higher than the resistance value in the thickness direction excluding the projections of the emitter electrode plate.