JP2001103104A - Digital radio equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To achieve distortion compensation in a PA (power amplifier) 36, miniaturization and power saving. SOLUTION: Baseband modulated signals I1 and Q1 are distortion-compensated by a distortion compensation processing section 26, converted into analog signals by D / A conversion sections 30 and 32 (frequency fs1), amplified by a PA 36, and transmitted. Part is fed back and demodulated, PA3
In the digital radio apparatus for detecting the distortion component generated in step 6 and calculating a distortion compensation coefficient for canceling the distortion component, the frequency converter 40 converts the feedback signal into the first IF of the frequency FI1.
The signal is converted to a signal, undersampled (frequency fs2) by the first A / D converter 76, and I4 and Q4 are demodulated by the digital quadrature demodulation processing of the demodulation unit 70, and LPFs 72 and 74 detect distortion components from I4 and Q4. A signal generation unit that obtains I5 and Q5 and generates a sampling clock of frequencies fs1 and fs2, a carrier wave to the analog quadrature modulation unit 34, and an oscillation frequency signal to the first frequency conversion unit 40 from a common reference oscillation source 90. 80 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to four-phase modulation of transmission data to generate baseband modulation signals I and Q, which are converted to analog signals by a D / A (digital / analog) converter. Then, after being modulated by the analog quadrature modulator, the signal is amplified by the power amplifier to create a transmission signal, a part of the transmission signal is fed back and demodulated, and a distortion component generated by the power amplifier is detected from the demodulated signal. The present invention relates to a digital radio apparatus in which a distortion compensation coefficient for canceling a distortion component is calculated and multiplied by baseband modulation signals I and Q to suppress adjacent channel leakage power of a transmission signal.

[0002]

2. Description of the Related Art In recent years, in the field of digital mobile radio communication, the band of a transmission signal has been narrowed in order to increase the channel capacity by reducing the frequency interval between adjacent channels. In order to realize such an improvement in frequency use efficiency, a modulation scheme with a small modulation spectrum bandwidth is desired, and a PSK (Phase Shift Keying) scheme, a QAM (Quad
A linear modulation scheme such as an r-ature Amplitude Modulation (r-ature Amplitude Modulation) scheme has been adopted. When this linear modulation scheme is applied to wireless communication, the linearity of the amplitude and phase characteristics of the power amplifier of the transmission unit is required, and it is important to suppress adjacent channel leakage power. On the other hand, when using a power amplifier, it is important to operate at an operating point that is as high as possible in power efficiency (a region close to a saturation point).
An increase in adjacent channel leakage power due to nonlinear distortion can be considered. In addition, when power efficiency is improved by using a power amplifier having poor linearity (for example, when power efficiency is improved in a small wireless device), adjacent channel leakage power due to nonlinear distortion increases. I will. Therefore, a technique for correcting distortion generated by the non-linear characteristics of the power amplifier becomes essential. That is, a technique for correcting distortion of a transmission signal caused by distortion of input power amplitude-output power amplitude characteristics and input power amplitude-phase rotation amount (or group delay amount) characteristics of a power amplifier becomes essential. As the distortion correction technology, a number of distortion correction methods such as Cartesian and feed forward have been proposed in the analog method.
There is a problem that power saving cannot be achieved, and there is a problem that it is difficult to adjust the phase to stabilize the circuit because the feedback gain must be very large.

Recently, with the advancement of digital signal processors (hereinafter simply referred to as DSPs), a system for correcting distortion by digital signal processing technology has become possible, and various nonlinear distortion correction systems based on digital signal processing have been proposed. Above all, a part of the transmission signal is fed back, demodulated and taken into the DSP, the distortion amount of the power amplifier is detected from the demodulated signal, and an LMS (Least Mean Square) algorithm which is a digital adaptive filter technique is used. Research and development for distortion compensation processing are active.
A conventional circuit based on such a distortion correction method using the LMS algorithm has been configured as shown in FIG.

The conventional circuit shown in FIG. 2 includes a DSP 10 and an RF (Radio Frequency) unit 12 on the transmission side.
0 has a transmission system 14 and a demodulation system 16. Transmission system 1
4, π / 4 shift QPSK (Quadrature Phase S
hift Keying) mapping unit (hereinafter simply π / 4-QP)
An SK mapping unit) 18, a root Nyquist filter 20, a power calculation unit 22, a distortion compensation coefficient calculation unit 24, a distortion compensation processing unit 26, and a clock generation unit 28.
D / A converters 30 and 32, an analog quadrature modulator 34, a power amplifier (hereinafter, referred to as PA) 36, a directional coupler 38, a frequency converter 40, and an analog quadrature demodulator 42 A / D (analog / digital) converters 44 and 46 for feedback, LNA (low noise amplifier) 48, frequency converter 50, analog quadrature demodulator 52, A / D converters 54 and 56 for reception, and RF signal A generation unit 58 is provided. The demodulation system 16 includes a BPF
(Band pass filters) 60 and 62 and a base band demodulation unit 64 are provided.

A clock generator 28 divides a clock oscillation source (not shown) and a reference oscillation frequency of a clock generated by the clock oscillator into integers corresponding to the respective clocks, and generates frequencies fs1, fs2a, and fs3a. A signal is generated, and a D / A converter 30 is used as a sampling clock.
32, A / D converters 44 and 46 for feedback, and a frequency divider (not shown) for outputting to A / D converters 54 and 56 for reception. Further, the RF signal generation unit 58
Generates a reference oscillation source (not shown) that generates a reference oscillation signal (RF signal) having a reference oscillation frequency fref, generates a signal synchronized in phase with the reference oscillation signal generated by the reference oscillation source, and generates an analog quadrature signal as a carrier signal. Modulation units 34, 42,
And a PLL (phase locked loop) circuit that outputs the signal to the frequency converters 52 and 50 as a signal for frequency conversion.

When the transmission data is taken into the DSP 10, baseband modulated signals I1 and Q1 are generated by the π / 4-QPSK mapping unit 18 and the root Nyquist filter 20, and the complex product sum is output by the distortion compensation processing unit 26. The distortion is compensated by the arithmetic processing and output to the transmission side RF unit 12. In the transmission-side RF unit 12, the baseband modulated signals I2 and Q2, which have been distortion-compensated by the distortion compensation processing unit 26, are converted into analog signals by D / A conversion units 30 and 32 (sampling clock frequency fs1), and analog quadrature modulation The signal is quadrature-modulated by the unit 34, amplified to a predetermined power by the PA 36, becomes a transmission signal, and is output from the antenna 66 after passing through the directional coupler 38. A part of the transmission signal output from the PA 36 is extracted by the directional coupler 38 and
0, the signal is frequency-converted (down-converted) to a predetermined frequency FI1, and the demodulated signal I is converted by the analog quadrature demodulator 42 and the A / D converters 44, 46 for feedback.
3, Q3 is demodulated and fed back to the DSP 10. In the DSP 10, according to the power value P obtained by the power calculator 22 by the distortion compensation coefficient calculator 24, first, the demodulated signal I3, which is fed back from the transmitter RF unit 12 using the baseband modulated signals I1 and Q1 as reference signals,
An error component (that is, a distortion component) for Q3 is detected,
Next, a distortion compensation coefficient for canceling the error component is calculated. This distortion compensation coefficient is multiplied by the baseband modulated signals I1 and Q1 (complex number product-sum operation) in the distortion compensation processing unit 26 according to the power value P, and the adjacent channel leakage power of the transmission signal is suppressed.

The received signal received by the antenna 68 is amplified by an LNA (low noise amplifier) 48, frequency-converted (down-converted) by a frequency converter 50 to a predetermined frequency FI 2, and analog-demodulated by an analog quadrature demodulator 52. The signal is demodulated, and the demodulated signal is converted into digital demodulated signals I and Q by A / D converters 54 and 56 for reception and input to DSP 10. In the DSP 10, the input demodulated signals I and Q are limited to the frequency bands corresponding to the BPFs 60 and 62, input to the baseband demodulation unit 64 and demodulated, and receive data is output from the baseband demodulation unit 64.

[0008]

However, the conventional circuit shown in FIG. 2 has a problem that the distortion compensation characteristics are significantly deteriorated by the analog quadrature demodulator 42 and the A / D converters 44 and 46 constituting the feedback system. was there. That is, since the analog quadrature demodulation unit 42 is composed of components having poor linearity such as a 90 ° phase shifter and a multiplier, the I / Q
A quadrature error and an I / Q gain error occur, deteriorating distortion compensation characteristics. For example, the phase of the carrier for reproduction (reference signal) output from the RF signal generator 58 is shifted by 90 °
The phase shifter normally has an error of about ± 2 °, an I / Q quadrature error occurs, and an amplitude error occurs in the demodulated I / Q signal. Also, the I / Q signals after the quadrature demodulation are converted into A / D converters 44 and 46.
A DC bias circuit is required to match the input range of
An offset has occurred.

The conventional circuit shown in FIG. 2 demodulates two types of demodulated signals I3 and Q3 using an analog quadrature demodulator 42 in a feedback system, and two types using an analog quadrature demodulator 52 in a reception system. Since the demodulated signals I and Q are demodulated, two A / D converters 44 and 46 are required in the transmission-side RF unit 12 for feedback and two A / D converters 54 for reception. , 56 are required, and there is a problem that the circuit scale becomes large and miniaturization is difficult. Further, the DSP 10 is provided with the clock generation unit 28, and the transmission-side RF unit 12 is provided with the RF signal generation unit 58,
The sampling clock generated by the clock generator 28 is converted into D / A converters 30, 32, A / D converters 44, 46, 5
4 and 56, and outputs the carrier signal generated by the RF signal generator 58 to the analog quadrature modulator 34 and the analog quadrature demodulators 42 and 52, and outputs a signal for frequency conversion to the frequency converters 40 and 50. Therefore, there is a problem that the transmission signal and the feedback signal cannot be synchronized, and accurate error detection cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to improve distortion compensation characteristics by eliminating quadrature errors and gain errors in quadrature demodulation processing, and to reduce the size and power consumption. It is an object of the present invention to provide a digital radio device that can be achieved.

[0011]

According to the present invention, transmission data is subjected to four-phase modulation to generate baseband modulated signals I and Q, and a D / A converter (sampling clock frequency f
In s1), the signal is converted into an analog signal, modulated by an analog quadrature modulator, and then amplified by a power amplifier to create a transmission signal.
A part of the transmission signal is demodulated by feedback, a distortion component generated in the power amplifier is detected from the demodulated signal, a distortion compensation coefficient for canceling the distortion component is calculated, and the baseband modulation signals I and Q are multiplied. In the digital radio apparatus which suppresses the adjacent channel leakage power of the transmission signal, the feedback transmission signal is converted to the first frequency FI1.
A first frequency conversion unit that converts the signal into an IF signal (intermediate frequency signal); and a frequency that satisfies the condition that the first IF signal satisfies a condition equal to FI1 × 4 / m, where fs2 is at least twice fs1 and m is 3 or more. 1A / A), which samples at the sampling clock and converts it into a digital signal.
A D conversion section, a first digital quadrature demodulation section for performing digital quadrature demodulation processing on the output signal of the first A / D conversion section and outputting demodulated signals orthogonal to each other, and a demodulation output from the first digital quadrature demodulation section A low-pass filter that extracts an envelope component from the signal and uses the envelope component as a demodulated signal for distortion component detection, and outputs a frequency fs1 to the D / A conversion unit.
, A sampling clock of frequency fs2 output to the first A / D conversion unit, a carrier signal output to the analog quadrature modulation unit, and a signal for frequency conversion output to the first frequency conversion unit. A signal generator for generating a signal from an oscillation source is provided, and the frequency fs1 is set to twice or more the transmission symbol rate of transmission data.

The feedback transmission signal is converted into a first IF signal having a frequency FI1 by a first frequency converter, and is converted into a digital signal by a first A / D converter. The sampling frequency fs2 of the first A / D converter is the sampling frequency fs1 of the D / A converter that creates the transmission signal.
And at least four times the frequency FI1 of the first IF signal.
m (m represents an odd number of 3 or more).
That is, the condition of fs2 = FI1 × 4 / m and fs2 ≧ f
The first sampling frequency fs2 satisfying the condition of s1
By sampling (i.e., undersampling) the IF signal, the signal down-converted to 1/4 of the sampling frequency fs2 is converted to a first A / D signal while the information data component of the first IF signal is held. It can be generated and output by the unit. For this reason, the processing speed of the digital quadrature demodulation unit and the low-pass filter can be suppressed low, and the digital quadrature demodulation unit and the low-pass filter can be used in digital signal processing of the DSP. Therefore, the distortion compensation characteristics can be improved by eliminating the orthogonal error and the gain error of the orthogonal demodulation unit, and the size and power consumption can be reduced by reducing the number of devices used. In addition, the sampling clock of frequency fs1 output to the D / A converter, the sampling clock of frequency fs2 output to the first A / D converter, the carrier signal output to the analog quadrature modulator, and the first
The signal for frequency conversion to be output to the frequency conversion unit is generated from the common reference oscillation source by the signal generation unit, so that the transmission signal and the feedback signal can be synchronized, and the non-linear characteristic of the power amplifier is generated. The error can be accurately detected.

In order to simplify the configuration of the signal generation section, the signal generation section includes a reference oscillation source for generating a reference oscillation signal having a reference oscillation frequency fref, and a reference oscillation frequency of the reference oscillation signal generated by the reference oscillation source. fref is multiplied by 1 / N1 (N1
Is an integer of 1 or more), generates a signal of frequency fs1, and outputs the signal as a sampling clock to the D / A converter, and a reference oscillation frequency fr of the reference oscillation signal.
f is divided by 1 / N2 times (N2 is an integer of 1 or more) to generate a signal of frequency fs2, and a second frequency divider that outputs the signal as a sampling clock to the first A / D conversion unit; A first PLL circuit that generates a phase-synchronized signal and outputs the signal as a carrier signal to the analog quadrature modulation unit, and a second PLL circuit that generates a signal that is phase-synchronized with the reference oscillation signal and outputs the signal as a frequency conversion signal to the first frequency conversion unit And

In order to reduce the size and power consumption of the receiving section of the digital radio apparatus, the received signal is transmitted at the second frequency FI2.
A second frequency conversion unit that converts the signal into an IF signal (intermediate frequency signal); and converts the second IF signal into a frequency fs3 (fs3 is 2 of fs1).
A frequency that satisfies the condition equal to or more than twice and equal to FI2 × 4 / n. n represents an odd number of 3 or more. 2) A / D in which sampling is performed by the sampling clock and converted into a digital signal
A conversion unit, a second digital quadrature demodulation unit for performing digital quadrature demodulation processing on the output signal of the second A / D conversion unit and outputting demodulated signals orthogonal to each other, and two types of signals output by the second digital quadrature demodulation unit And a baseband demodulator for demodulating received data based on an output signal of the channel selection filter. A signal for frequency conversion output to the frequency converter and a sampling clock of frequency fs3 output to the second A / D converter are generated from a common reference oscillation source.

In order to reduce the size and power consumption of the receiving section of the digital radio apparatus and simplify the configuration of the signal generating section, the signal generating section is provided with a reference oscillation circuit for generating a reference oscillation signal having a reference oscillation frequency fref. And the reference oscillation frequency fref of the reference oscillation signal generated by this reference oscillation source is 1 /
The frequency is divided by N1 times (N1 is an integer of 1 or more) and the frequency fs1
And a first frequency divider for generating a signal as a sampling clock and outputting it to the D / A converter, and dividing the reference oscillation frequency fref of the reference oscillation signal by 1 / N2 times (N2 is an integer of 1 or more). A second frequency divider for generating a signal of the frequency fs2 and outputting the signal as a sampling clock to the first A / D converter, and setting the reference oscillation frequency fref of the reference oscillation signal to 1 / N3
A third frequency divider that divides the frequency by a factor of 2 (N3 is an integer of 1 or more) to generate a signal of frequency fs3 and outputs the signal to the second A / D converter as a sampling clock, and a signal that is phase-synchronized with the reference oscillation signal A first PLL circuit that generates and outputs the carrier signal as a carrier signal to the analog quadrature modulation unit, a second PLL circuit that generates a signal synchronized in phase with the reference oscillation signal and outputs the signal as a frequency conversion signal to the first frequency conversion unit, To generate a signal that is phase-synchronized with the second
And a third PLL circuit for outputting to the frequency conversion unit.

In order to be able to use the digital radio equipment for business use, the reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source is set to k times (k is an integer of 1 or more) the channel interval, Frequency FI1 of first IF signal
Is set to q times the channel interval (q is an integer of 1 or more), or the reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source is set to k times the channel interval, and the first I
The frequency FI1 of the F signal is set to q times the channel interval,
The frequency FI2 of the second IF signal is set to r times (r
Is an integer of 1 or more).

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a digital radio apparatus according to the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and the description is omitted or simplified. In FIG. 1, 1
0a is a DSP, and 12a is a transmission side RF unit. The DS
P10a has a transmission system 14a and a demodulation system 16a. The transmission system 14a includes a π / 4-QPSK mapping unit 18, a root Nyquist filter 20, a power calculation unit 22, and a distortion compensation coefficient calculation unit 24, similarly to the DSP 10 of FIG.
And a distortion compensation processing unit 26, a digital quadrature demodulation unit 70 and an LPF (low-pass filter).
72 and 74 are provided. The transmitting side RF unit 12a
The D / A conversion unit 3 has the same configuration as the transmission-side RF unit 12 in FIG.
0, 32, analog quadrature modulator 34, PA 36, directional coupler 38, LNA 48, and first and second frequency converters 4
0 and 50 are provided, and first and second A / D converters 76 and 78 and a signal generator 80 are provided. The demodulation system 16a includes a digital quadrature demodulation unit 82, channel selection filters 84 and 86, and a baseband demodulation unit 8
8 are provided.

The signal generator 80 comprises a reference oscillation source 90, first, second and third frequency dividers 91, 92 and 93 and first, second and third PLL circuits 94, 95 and 96. . The reference oscillation source 90 supplies a reference oscillation signal (RF) having a reference oscillation frequency fref (for example, fref = 19.2 MHz).
Signal). The reference oscillation frequency fref is set to k times (k is an integer of 1 or more, for example, k = 3072) the channel interval (for example, 6.25 kHz). The first, second and third frequency dividers 91, 92 and 93 increase the reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source 90 by 1 / N1, 1 / N2 and 1 / N3 times (N1 , N
2, N3 represents a positive integer) and the frequency fs1
(For example, 48 kHz when N1 = 400), fs2
(For example, 240 kHz when N2 = 80), fs3
(For example, 200 kHz in the case of N3 = 96), and the D / A converter 3 is used as a sampling clock.
0, 32, first A / D converter 76, second A / D converter 7
8 is output. Here, the sampling clock frequency fs1 to the D / A conversion units 30 and 32 is set to p times the transmission symbol rate (p is an integer of 2 or more) because oversampling must be performed to satisfy the sampling theorem. Have been. The first PLL circuit 94 generates a signal that is phase-locked to the reference oscillation signal of the reference oscillation frequency fref and outputs the signal as a carrier signal to the analog quadrature modulation unit 34. The second and third PLLs 95 and 96 output the reference oscillation frequency fref. A signal that is phase-synchronized with the oscillation signal is generated, and is used as a signal for frequency conversion (for beat down).
The signals are output to the second frequency converters 40 and 50.

The first frequency converter 40 frequency-converts (down-converts) the frequency of the transmission signal fed back by the directional coupler 38 and outputs a first IF signal having a frequency FI1 (for example, 300 kHz). The frequency FI1 of the first IF signal is the channel interval (for example, 6.
Q times (25 kHz) (q is an integer of 1 or more, for example, q =
48 is set to 300 kHz).
The frequency (local oscillation frequency) of the frequency conversion signal output from the LL 95 to the first frequency conversion unit 40 is set. The first A / D converter 76 samples the first IF signal output from the first frequency converter 40 at a sampling frequency fs2, and performs feedback I
An F signal (hereinafter, simply referred to as an FBIF signal) is output.
The sampling frequency fs2 satisfies the following equation (1) and is set to an integer multiple of twice or more the sampling frequency fs1 of the D / A converters 30 and 32. fs2 = FI1 × 4 / m (1) In the equation (1), m is an odd number of 3, or more (3, 5, 7,...)
And the first IF signal is converted to the Nyquist frequency (2 of FI1).
This means that sampling (hereinafter simply referred to as undersampling) is performed at a sampling frequency equal to or less than twice the frequency. In addition, the reason why fs2 is set to be twice or more than fs1 is that the first A / D converter 76 on the feedback side is required to faithfully detect the transmission signal (including the distortion component) output from the transmission-side RF unit 12a. Is required to be set to be twice or more the sampling frequency fs1 of the transmitting side.

The digital quadrature demodulation unit 70 converts the FBIF signal output from the first A / D
It sequentially multiplies digital local signals on the I and Q sides (hereinafter simply referred to as Lo signals) having a phase difference of ° to output demodulated signals I4 and Q4 orthogonal to each other. The LPF
Numerals 72 and 74 remove the frequency components of fs2 / 2 and fs2 / 4 from the demodulated signals I4 and Q4 obtained by the quadrature demodulation processing of the digital quadrature demodulation unit 70 to extract the envelope components, and to reduce the influence of the DC offset. To reduce. That is, only the envelope component (information data signal component) is extracted by removing the fs2 / 2 frequency component from the demodulated signals I4 and Q4 in which the "0" amplitude component is alternately mixed at a cycle of 2 / fs2. The effect of the DC offset is reduced by removing the frequency component of fs2 / 4 generated in the orthogonal demodulation processing of the DC offset component. The distortion compensation coefficient calculator 24 detects the amount of distortion generated in the PA 36, calculates a distortion compensation coefficient for canceling the distortion, and outputs the calculated distortion compensation coefficient to the distortion compensation processor 26.

The second frequency converter 50 frequency-converts (down-converts) the frequency of the received signal received by the antenna 68 and amplified by the LNA 48, and outputs a second IF signal of frequency FI2. The frequency FI2 of the second IF signal is a channel interval (for example, 6.25 kHz).
(The r is an integer of 1 or more, for example, 450 kHz when r = 72).
The frequency (local oscillation frequency) of the signal for frequency conversion to be output to the second frequency conversion unit 50 from is set.
The second A / D converter 78 is configured to control the second frequency converter 5
The second IF signal output from 0 is converted to the sampling frequency fs
3 and outputs a reception IF signal (hereinafter simply referred to as a RIF signal). This sampling frequency fs3 is set so as to satisfy the following equation (2). fs3 = FI2 × 4 / n (2) In the equation (2), n is an odd number of 3 or more (3, 5, 7,...)
And the second IF signal is converted to the Nyquist frequency (2 of FI2).
This means that sampling (hereinafter simply referred to as undersampling) is performed at a sampling frequency equal to or less than twice the frequency.

The digital quadrature demodulation unit 82 is configured in the same manner as the digital quadrature demodulation unit 70,
The RIF signal output from the / D converter 78 is sequentially multiplied by the digital local signals on the I and Q sides having a phase difference of 90 ° to output demodulated signals Ia and Qa orthogonal to each other. The channel selection filters 84 and 86 select and output the corresponding frequency band components from the input demodulated signals Ia and Qa. The baseband demodulation unit 88 performs baseband demodulation processing on signals output from the channel selection filters 84 and 86 to demodulate received data.

Next, the operation of FIG. 1 will be described. For convenience of explanation, the frequency fref of the reference oscillation signal generated by the reference oscillation source 90 is 19.2 MH under the following condition (A).
z (= 6.25 kHz × 3072 (when k = 3072)), the frequency fs1 of the sampling clock set by the first, second, and third frequency dividers 91, 92, and 93 is 48 k
Hz, fs2 is 240kHz, fs3 is 200kHz
(When N1 = 400, N2 = 80, N3 = 96), the frequency FI1 of the first and second IF signals set by the first, second and third PLL circuits 94, 95 and 96 is 300 kHz,
The case where FI2 is 450 kHz (q = 48, r = 72) will be described as an example. Condition (A) (1) Transmission / reception symbol rate: 4.8 k symbol / se
c (2) Transmission / reception bit rate: 9.6 kbit / sec (3) Modulation / demodulation method: π / 4 shift QPSK (4) Channel interval: 6.25 kHz

(1) When the transmission data is taken into the DSP 10a, the baseband modulation signals I1 and Q1 are generated by the π / 4-QPSK mapping unit 18 and the root Nyquist filter 20, and the complex product by the distortion compensation processing unit 26 Baseband modulated signal I corrected for distortion by sum operation processing
2, Q2 is output to the transmitting side RF unit 12a. Transmission side RF
In the unit 12a, the baseband modulation signals I2 and Q2, which have been distortion-compensated by the distortion compensation processing unit 26, are converted into D / A conversion units 30 and 32.
(Sampling clock frequency fs1 = 48 kHz), is converted into an analog signal by the analog quadrature modulator 34, is quadrature-modulated, is amplified to predetermined power by the PA 36, becomes a transmission signal, passes through the directional coupler 38, and then passes through the antenna 66.
To the base station.

(2) A part of the transmission signal output from the PA 36 is taken out by the directional coupler 38, down-converted to the first IF signal of the frequency FI1 (= 300 kHz) by the first frequency converter 40, and / D converter 76
To enter. The first A / D converter 76 undersamples the first IF signal at a sampling frequency fs2 (= 240 kHz) to generate an FBIF signal, and the DSP 10
The signal is output to the digital quadrature demodulation unit 70 in a.

(3) The FBIF signal output from the first A / D converter 76 is subjected to the quadrature demodulation processing of the digital quadrature demodulator 70 so that the I-side Lo signal and the Q-side Lo signal having a phase difference of 90 ° are sequentially formed. The signals are multiplied and output as demodulated signals I4 and Q4 orthogonal to each other. The I-side Lo signal has a period 1 /
For each fs2 (corresponding to a phase difference of 90 °), “+1”, “0”,
The signals are in the states of "-1" and "0", and one state (4 / fs2) is constituted by the four states. The Q side Lo signal is the I side Lo signal.
90 ° phase lag (or advance) with respect to signal
One cycle is composed of four states of “0”, “+1”, “0”, and “−1”. Therefore, in the digital quadrature demodulation unit 70, the I-side Lo signal (Q
Quadrature demodulation processing is performed by sequentially and repeatedly multiplying the same Lo signal by the same frequency fs as the FBIF signal.
Baseband demodulated signals I4 and Q4 are generated as a result of multiplication with a 2/4 Lo signal (Q-side Lo signal is a signal whose phase is delayed (or advanced) by 90 ° with respect to I-side Lo signal). The baseband demodulated signals I4 and Q4 are on the I side Lo.
Both the signal and the Q-side Lo signal have a “0” signal every period 2 / fs2. As described above, since the baseband demodulated signals I4 and Q4 subjected to the quadrature demodulation processing by the digital quadrature demodulation unit 70 have a “0” signal every 2 / fs2, the transmission signal output from the transmission-side RF unit 12a is provided. In order to faithfully detect (including the distortion component), the undersampling frequency fs of the first A / D converter 76 in the above (2) is required.
2 must be set to at least twice the sampling frequency fs1 on the transmission side, fs1 = 48 kHz, fs1
2 = 240 kHz satisfies this.

(4) From the demodulated signals I4 and Q4 output from the digital quadrature demodulation unit 70, the frequency components of fs2 / 2 and fs2 / 4 are removed by the LPFs 72 and 74, so that the envelope component is extracted and the influence of the DC offset. Is reduced. That is, since the demodulated signals I4 and Q4 obtained by the quadrature demodulation process become "0" signals every period 2 / fs2, the frequency components of fs2 / 2 are removed by the LPFs 72 and 74 formed by digital FIR filters, for example. (The information data signal band passes), and the envelope component is extracted. Since the digital filter processing is a convolution operation, if the waveform in which the “0” signal is present is alternately filtered, the signal amplitude is reduced to 、. Therefore, the signal filtered by the LPFs 72 and 74 is not shown in an amplifier or the like. Must be doubled and output to the distortion compensation coefficient calculation unit 24.

(5) As described above, f
By removing the frequency component of s2 / 2, the information data
Data component can be demodulated, but by further removing the frequency component of fs2 / 4, it is possible to prevent the characteristic deterioration due to the DC offset component on the feedback side (bias voltage error of the input signal of the first A / D converter 76). .

(6) When the signal transmitted from the base station is received by the antenna 68, the received signal is amplified by the LNA 48, and is down-converted by the second frequency converter 50 to the second IF of the frequency FI2 (= 450 kHz). The signal is converted into a signal and input to the second A / D converter 78. 2A
The / D converter 78 converts the second IF signal to a frequency fs3 (=
Sampled with a sampling clock of 200 kHz) and R
An IF signal is generated and output to the digital quadrature demodulation unit 82 in the DSP 10a.

(7) When the RIF signal output from the second A / D converter 78 is input to the digital quadrature demodulator 82,
Demodulated signals Ia and Qa orthogonal to each other are obtained by the same quadrature demodulation processing as in the digital quadrature demodulation unit 70, and input to the channel selection filters 84 and 86. In the channel selection filters 84 and 86, the corresponding frequency band components of the demodulated signals Ia and Qa are selected and input to the baseband demodulation unit 88. Is demodulated.

In the above embodiment, under the following condition (A), when the frequency fref of the reference oscillation frequency signal is 19.2 MHz, and under the following condition (B), N
1 = 400, p = 10, N2 = 80, m = 5, N3 = 9
6, n = 9, q = 48, q = 72 (that is, fs1 = 48 kHz, fs2 = 240 kHz, fs
3 = 200 kHz, FI1 = 300 kHz, FI2 = 4
(In the case of 50 kHz), but the present invention is not limited to this. Condition (A) (1) Transmission / reception symbol rate: 4.8 k symbol / se
c (2) Transmission / reception bit rate: 9.6 kbit / sec (3) Modulation / demodulation method: π / 4 shift QPSK (4) In the case of channel spacing: 6.25 kHz, condition (B) (1) fs1 = fref / N1 : (N1 is an integer of 1 or more) fs1 = (transmission / reception symbol rate) × p: (p is an integer of 2 or more) (2) fs2 = fref / N2: (N2 is an integer of 1 or more) fs2 = FI1 × 4 / m: (m is an odd number of 3 or more) (3) fs3 = fref / N3: (N3 is an integer of 1 or more) fs3 = FI2 × 4 / n: (n is an odd number of 3 or more) (4) FI1 = (channel (Interval) × q: (q is an integer of 1 or more) (5) FI2 = (channel interval) × r: (r is an integer of 1 or more)

That is, in the condition (A), if the transmission / reception symbol rate is a value other than 4.8 k symbols / sec,
The transmission / reception bit rate is twice the transmission / reception symbol rate,
In the case where the modulation / demodulation method is a 4-phase phase modulation / demodulation method and the channel interval is a value other than 6.25 kHz, in condition (B), N1 is an integer of 1 or more except 400, p is an integer of 2 or more other than 10, and N2 is an integer of 2 or more other than 10. An integer other than 80, m is an odd number of 3 or more other than 5, N3 is an integer of 1 or more other than 96, n is an odd number of 3 or more other than 9, q is an integer of 1 or more other than 48, and q is 72
The present invention can also be applied to cases where the value is set to an integer other than 1 or more.

In the above-described embodiment, the case where the signal generating unit is formed in the transmitting RF unit has been described. However, the present invention is not limited to this, and the present invention is also used when the signal generating unit is formed in the DSP. be able to. For example, FIG.
Instead of forming the signal generation unit 80 in the transmission-side RF unit 12a, a signal generation unit 80a (not shown) is formed in the DSP 10a, and this signal generation unit 80a uses a clock oscillation source as a common reference oscillation source. A sampling clock having a frequency fs1 to be output to the D / A conversion unit;
A sampling clock of frequencies fs2 and fs3 to be output to the D conversion unit, a carrier signal output to the analog quadrature modulation unit, and a signal for frequency conversion output to the first and second frequency conversion units are generated. It can also be used in some cases.

In the above embodiment, in order to simplify the configuration of the signal generator, the signal generator is composed of a reference oscillation source, first, second, and third frequency dividers, and first, second, and third PLL circuits. And the reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source in the first, second, and third frequency dividers is 1 / N1, 1 / N.
The frequency is divided by N2, 1 / N3 times (that is, a fraction of an integer) to generate signals of frequencies fs1, fs2, and fs3, and a D / A converter, a first A / D converter,
The signal is output to the second A / D converter, the first PLL circuit generates a signal that is phase-locked to the reference oscillation signal, and the signal is output as a carrier signal to the analog quadrature modulation unit. A case has been described in which a signal is generated and output to the first and second frequency conversion units as a signal for frequency conversion. However, the present invention is not limited to this, and the signal generation unit outputs a signal to the D / A conversion unit. sampling clock of fs1, sampling clocks of frequencies fs2 and fs3 output to the first and second A / D converters, carrier signals output to the analog quadrature modulator, and frequencies output to the first and second frequency converters The present invention can be used for a signal that generates a signal for conversion from a common reference oscillation source.

In the above embodiment, the case where the present invention is applied to the transmitting section and the receiving section of the digital radio apparatus has been described. However, the present invention is not limited to this, and the present invention is applied only to the transmitting section of the digital radio apparatus. Holds for those that use At this time, when the signal generation unit is configured by the reference oscillation source, the first and second frequency dividers, and the first and second PLL circuits, the configuration of the signal generation unit can be simplified.

[0036]

According to the present invention, a first frequency converter for converting a feedback transmission signal into a first IF signal having a frequency FI1 and a first A / D converter for sampling the first IF signal at a frequency fs2 and converting the signal into a digital signal. Part and this 1A
A digital quadrature demodulation unit that performs digital quadrature demodulation processing on the output signal of the / D conversion unit and outputs demodulated signals orthogonal to each other, and extracts an envelope component from the demodulated signal output by the digital quadrature demodulation unit to detect distortion components. A low-pass filter as a demodulated signal, wherein the sampling frequency fs2 of the first A / D converter is at least twice the sampling frequency fs1 of the D / A converter for generating the transmission signal, and the frequency FI1 of the first IF signal. 4 / m (m is 3
(Odd number). Therefore, while the information data component of the first IF signal is held, a signal that is down-converted to a quarter of the sampling frequency fs2 can be generated and output by the first A / D converter. The processing speed of the digital quadrature demodulation unit and the low-pass filter can be kept low, and the digital quadrature demodulation processing and the low-pass filter can be realized by the DSP. Therefore, the distortion compensation characteristics can be improved by eliminating the orthogonal error and the gain error of the orthogonal demodulation unit, and the size and power consumption can be reduced by reducing the number of devices used. Moreover, a sampling clock of frequency fs1 output to the D / A converter, a sampling clock of frequency fs2 output to the first A / D converter, a carrier signal output to the analog quadrature modulator, and a frequency output to the first frequency converter All of the conversion signals are generated from a common reference oscillation source by the signal generation unit, so that the transmission signal and the feedback signal can be synchronized, and the error caused by the nonlinear characteristics of the power amplifier can be accurately detected. Can be done.

The signal generator comprises a reference oscillation source, first and second frequency dividers, and first and second PLL circuits. The reference oscillation source generates a reference oscillation signal having a frequency fref. The reference oscillation frequency fref of the reference oscillation signal is 1 / N
The frequency is divided by 1, 1 / N2 times (ie, 1 / integer) to generate signals of the frequencies fs1 and fs2, and output to the D / A conversion unit and the first A / D conversion unit as a sampling clock, and the first PLL circuit Generates a signal that is phase-locked to the reference oscillation signal and outputs the signal as a carrier signal to the analog quadrature modulation unit.
When the PLL circuit generates a signal that is phase-synchronized with the reference oscillation signal and outputs the signal to the first frequency conversion unit as a signal for frequency conversion, the transmission unit and the feedback unit may include a digital radio device using the present invention. The configuration of the signal generator can be simplified.

A second frequency converter for converting the received signal into a second IF signal having a frequency FI2, and a second IF signal having a frequency fs
A second A / D converter for sampling by a sampling clock of No. 3 and converting it into a digital signal, and a second digital for performing digital quadrature demodulation processing on an output signal of the second A / D converter and outputting demodulated signals orthogonal to each other. A quadrature demodulator,
A channel selection filter for selecting and outputting frequency bands corresponding to two types of demodulated signals output from the second digital quadrature demodulation unit, and a baseband demodulation unit for demodulating received data based on the output signal of the channel selection filter And a frequency conversion signal output to the second frequency conversion unit and a frequency fs output to the second A / D conversion unit.
3 is generated from a common reference oscillation source by the signal generation unit,
The configuration of the signal generation unit of the digital wireless device using the present invention for the transmission unit, the feedback unit, and the reception unit can be simplified.

The reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source is set to k times (k is an integer of 1 or more) the channel interval, and the frequency FI1 of the first IF signal is set to q times (q is the channel interval). Or an integer of 1 or more), or the reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source is set to k times the channel interval, and the frequency FI1 of the first IF signal is set to q times the channel interval. , 2nd I
When the frequency FI2 of the F signal is set to r times the channel interval (r is an integer of 1 or more), the present invention can be used for a digital radio device for business use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital wireless device according to the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

10, 10a: DSP, 12, 12a: RF on the transmitting side
, 14, 14a: transmission system, 16, 16a: demodulation system, 18: π / 4-QPSK mapping unit (an example of a digital quadrature modulation processing unit), 20: root Nyquist filter (an example of a root Nyquist processing unit), 22 …
Power calculation unit, 24: distortion compensation coefficient calculation unit, 26: distortion compensation processing unit, 30, 32: D / A conversion unit, 34: analog quadrature modulation unit, 36: PA (power amplifier), 38 ...
Directional coupler, 40 first frequency converter, 48 L
NA (low noise amplifier), 50 second frequency converter, 66, 68 antenna, 70, 82 digital quadrature demodulator, 72, 74 LPF (low pass filter), 76 first A / D converter, 78 2nd A / D
Conversion unit, 80 ... Signal generation unit, 84, 86 ... Channel selection filter, 88 ... Baseband demodulation unit, 90 ...
Reference oscillation source, 91: first frequency divider, 92: second frequency divider, 93: third frequency divider, 94: first PLL circuit,
95: second PLL circuit, 96: third PLL circuit, F
BIF: IF signal for feedback (intermediate frequency signal), FI1: frequency of first IF signal, FI2: frequency of second IF signal, fref: reference oscillation frequency,
fs1: the sampling clock frequency of the D / A converters 30 and 32; fs2: the sampling clock frequency (undersampling clock frequency) of the first A / D converter 76; fs3: the sampling clock frequency of the second A / D converter 78 (under) Sampling clock frequency), first IF, second IF ... intermediate frequency signal, RI
F: IF signal for reception (intermediate frequency signal).

Claims (6)

[Claims] 1. Four-phase modulation of transmission data to generate baseband modulated signals I and Q, which are converted to analog signals by a D / A converter (sampling clock frequency fs1), and analog quadrature modulation. The signal is modulated by the power amplifier and then amplified by a power amplifier to create a transmission signal. A part of the transmission signal is fed back and demodulated, and a distortion component generated in the power amplifier is detected from the demodulated signal to cancel the distortion component. , And multiplies the baseband modulated signals I and Q to suppress the adjacent channel leakage power of the transmission signal. In the digital radio apparatus, the feedback transmission signal is converted to a first IF signal ( A first frequency converter for converting the first IF signal into a frequency fs2 (where fs2 is at least twice the frequency fs1 and FI1 ×
Represents a frequency satisfying a condition equal to 4 / m. m represents an odd number of 3 or more. A) a first A / D converter for sampling by a sampling clock and converting the digital signal into a digital signal; and a first digital signal for performing a digital quadrature demodulation process on an output signal of the first A / D converter and outputting demodulated signals orthogonal to each other. A quadrature demodulation unit; and a low-pass filter that extracts an envelope component from the demodulation signal output from the first digital quadrature demodulation unit and uses the envelope component as a demodulation signal for distortion component detection, and outputs a frequency fs1 to the D / A conversion unit. And a frequency f output to the first A / D converter.
a signal generation unit that generates a sampling clock of s2, a carrier signal output to the analog quadrature modulation unit, and a signal for frequency conversion output to the first frequency conversion unit from a common reference oscillation source; A digital radio apparatus characterized in that fs1 is set to be at least twice the transmission symbol rate of the transmission data. 2. A signal generator comprising: a reference oscillation source for generating a reference oscillation signal having a reference oscillation frequency fref; and a reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source.
/ N1 times (N1 is an integer of 1 or more) and frequency fs
1 is generated and D / A is used as a sampling clock.
A first frequency divider to be output to the converter, and a frequency of fs2 generated by dividing the reference oscillation frequency fref of the reference oscillation signal by 1 / N2 times (N2 is an integer of 1 or more), as a sampling clock. A second frequency divider for outputting to the first A / D converter, and a first frequency divider for generating a signal synchronized in phase with the reference oscillation signal and outputting the signal as a carrier signal to the analog quadrature modulator.
2. The digital radio apparatus according to claim 1, comprising: an LL circuit; and a second PLL circuit that generates a signal synchronized in phase with the reference oscillation signal and outputs the signal to the first frequency conversion unit as a signal for frequency conversion. 3. A second frequency converter for converting a received signal into a second IF signal (intermediate frequency signal) having a frequency FI2, and a second frequency converter for converting said second IF signal to a frequency fs3 (fs3 is twice or more of fs1 and FI2 × 4 / n Represents a frequency that satisfies a condition equal to: n represents an odd number of 3 or more.) A second A / D converter for sampling by a sampling clock and converting it into a digital signal, and an output signal of the second A / D converter A second digital quadrature demodulation unit for performing digital quadrature demodulation processing and outputting demodulated signals orthogonal to each other, and a channel for selecting and outputting a frequency band corresponding to the two types of demodulated signals output by the second digital quadrature demodulation unit A selection filter,
A baseband demodulation unit for demodulating received data based on an output signal of the channel selection filter; a signal generation unit configured to output a signal for frequency conversion output to the second frequency conversion unit and the second A / D Frequency fs output to converter
2. The digital radio apparatus according to claim 1, wherein the three sampling clocks are generated from a common reference oscillation source. 4. A signal generator for generating a reference oscillation signal having a reference oscillation frequency fref, and a reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source being 1
/ N1 times (N1 is an integer of 1 or more) and frequency fs
1 is generated and D / A is used as a sampling clock.
A first frequency divider to be output to the converter, and a frequency of fs2 generated by dividing the reference oscillation frequency fref of the reference oscillation signal by 1 / N2 times (N2 is an integer of 1 or more), as a sampling clock. A second frequency divider for outputting to the first A / D converter; and dividing the reference oscillation frequency fref of the reference oscillation signal by 1 / N3 times (N3 is an integer of 1 or more) to obtain a frequency f
s3, and generates a second signal as a sampling clock.
A third frequency divider for outputting to the A / D converter, a first PLL circuit for generating a signal phase-synchronized with the reference oscillation signal and outputting the signal as a carrier signal to the analog quadrature modulation section, and a phase-locked signal for the reference oscillation signal A second PLL circuit that generates a signal and outputs the signal to the first frequency conversion unit as a signal for frequency conversion;
A third PL that generates a signal phase-synchronized with the reference oscillation signal and outputs the signal to the second frequency conversion unit as a signal for frequency conversion;
4. The digital radio apparatus according to claim 3, comprising an L circuit. 5. The reference oscillation frequency fref of a reference oscillation signal generated by a reference oscillation source is set to k times (k is an integer of 1 or more) the channel interval, and the frequency FI1 of the first IF signal is set to q times (channel interval). 3. The digital wireless apparatus according to claim 2, wherein q is an integer of 1 or more. 6. The reference oscillation frequency fref of the reference oscillation signal generated by the reference oscillation source is set to k times (k is an integer of 1 or more) the channel interval, and the frequency FI1 of the first IF signal is set to q times (channel interval). q is an integer of 1 or more), and the second I
5. The digital radio apparatus according to claim 4, wherein the frequency FI2 of the F signal is set to r times the channel interval (r is an integer of 1 or more).