JP2001119693A - MPEG image display control method and apparatus - Google Patents

Abstract

(57) [Summary] [Problem] To provide an MPEG image display control method for decoding an MPEG stream and performing image display control, when an error occurs in decoded image data in an MPEG decoder, a simple error concealment process is performed on the display image. Make the disturbance less noticeable. An MPEG stream is decoded in an MPEG decoder using four frame memories M0 to M3 so that one frame of encoded image data is decoded within one frame display period.
The decoding image data output from the MPEG decoder includes a step of writing the decoded image data to a frame memory storing invalid data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving
The present invention relates to an MPEG image display control method and apparatus for decoding a stream and controlling image display.

[0002]

FIG. 13 is a block circuit diagram showing a main part of an example of a conventional MPEG image display apparatus. In FIG. 13, 1
Is a conventional MPEG image display control device that decodes an MPEG stream and controls image display. In the MPEG image display control device 2, 3 denotes M
MPEG decoder for decoding PEG stream, 4
Reference numerals -0, 4-1 and 4-2 denote frame memories for storing decoded image data output from the MPEG decoder 3.

[0005] Further, 5 is controlled by a distribution control signal given from the MPEG decoder 3, and decodes decoded image data output from the MPEG decoder 3 into a frame memory 4.
0, 4-1 or 4-2;
Is a selector which is controlled by a select control signal given from the MPEG decoder 3 and selects one of the frame memories 4-0, 4-1 and 4-2, and outputs decoded image data output from the selected frame memory. When the decoded image data output from the selector 6 is display image data, a display controller 7 inputs the decoded image data and performs image display control on the display 1 by inputting it.

FIG. 14 is a timing chart showing an example of the operation of the conventional MPEG image display device shown in FIG. 13. FIG. 14A shows a decoded image output from the MPEG decoder 3, and FIG. ,
FIG. 14C shows a decoded image stored in the frame memories 4-0 to 4-2, and FIG. 14D shows a memory map of the frame memory 4-2 at time TA. In this operation example, the MPEG decoder 3 performs decoding in the order of I2 image → B0 image → B1 image → P6 image → B3 image → B4 image → B5 image → P10 image.
, B0 image → B1 image → I2 image → B3 image →
The images are displayed in the order of B4 image → B5 image.

[0005]

The conventional M shown in FIG.
In the PEG image display device, the decoding processing of the MPEG stream and the display processing of the decoded image are not synchronized in units of frames, and the decoded image data is not written in the frame memory from which the display image data is read. May occur. For example, FIG.
When the B4 image data is output from the MPEG decoder 3 in the operation example shown in (1), I2 image data as reference image data to be held as valid data is stored in the frame memories 4-0 and 4-1. Since the P6 image data is stored, the B4 image data cannot be written in the frame memories 4-0 and 4-1. The B3 image data is stored and the frame in which the B3 image data is currently read out is stored. The B4 image data must be overwritten on the memory 4-2.

Here, for example, as shown in FIG.
When an error occurs in the B4 image data being decoded in the PEG decoder 3, what is displayed next to the currently displayed B3 image is:
A method of displaying an image as it is, (2) a method of displaying a currently displayed B3 image, and (3) a method of displaying an I2 image or a P6 image held as a reference image can be considered. However, the method (1) uses the B4
This method is inconvenient in displaying an image.
This is inconvenient in displaying the B3 image overwritten by the image, and the method (3) is inconvenient in displaying an image inconsistent in the time relationship of the displayed images.

As described above, the conventional MPEG shown in FIG.
In a conventional MPEG image display device including the image display control device 2, when an error occurs in a decoded image,
There was a problem that a sufficient error concealment process could not be performed, and the disturbance of the displayed image on the display 1 could not be made noticeable.
In particular, in broadcast media, since an MPEG stream is transmitted by radio waves, an error in which a bit string becomes abnormal due to noise is likely to occur.
The error concealment process is regarded as a particularly important process.

The present invention has been made in view of the above circumstances, and when an error occurs in decoded image data in an MPEG decoder, disturbance of a display image can be made less noticeable by a simple error concealment process. It is an object of the present invention to provide an MPEG image display control method and apparatus.

[0009]

According to the MPEG image display control method of the present invention, an MPEG decoder decodes an MPEG stream so that one frame of encoded image data is decoded within one frame display period. And writing the decoded image data output from the MPEG decoder into a frame memory storing invalid data on a frame-by-frame basis.

[0010] In the MPEG image display control method of the present invention, the decoding process of one frame of encoded image data is performed within one frame display period, and the decoding process and the display process are synchronized on a frame basis. Moreover, the decoded image data output from the MPEG decoder is written frame by frame to the frame memory storing the invalid data, and the frame memory storing the decoded image data which is the base data of the currently displayed image. Further, the decoded image data output from the MPEG decoder is not written in the frame memory storing the decoded image data to be held as the reference image data. As a result, MP
When an error occurs in the decoded image data in the EG decoder, the currently displayed image can be repeatedly displayed.

[0011] The MPEG image display control device of the present invention comprises:
An MPEG decoder that decodes an MPEG stream by performing decoding of one frame of encoded image data during a frame display period, a display image data storage frame memory, a decoded image data storage frame memory, and first and second references The display image data storage frame memory, the decoded image data storage frame memory, and the first and second reference image data storage frame memories are switchably allocated so that the image data storage frame memories exist simultaneously. It has a plurality of frame memories.

In the MPEG image display control device of the present invention, one frame of the encoded image data is decoded within one frame display period, and the decoding process and the display process are synchronized on a frame basis. In addition, by allocating the frame memory storing invalid data among the plurality of frame memories as the decoded image data storage frame memory, the frame storing the decoded image data which is the base data of the currently displayed image is allocated. The decoded image data output from the MPEG decoder can be prevented from being written into the memory or the frame memory storing the decoded image data to be held as the reference image data.
As a result, if an error occurs in the decoded image data in the MPEG decoder, the currently displayed image can be repeatedly displayed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
First to fourth embodiments of the MPEG image display control method of the present invention and one embodiment of the MPEG image display control device of the present invention will be described.

[0014] First of the MPEG image display control method of the present invention
Embodiments FIGS. 1 and 2 A first embodiment of the MPEG image display control method of the present invention is as follows.
It uses four frame memories M0, M1, M2, and M3. The MPEG decoder performs decoding of an MPEG stream so that decoding of one frame of encoded image data is performed within one frame display period. In addition, the process of writing one frame of decoded image data output from the MPEG decoder into the frame memory storing invalid data is included in the image display control process.

FIG. 1 is a timing chart showing a first specific example of the first embodiment of the MPEG image display control method according to the present invention. FIG. 1A shows a decoded image output from an MPEG decoder, and FIG. 1B shows a decoded image displayed on a display. FIG. 1C shows decoded images stored in the frame memories M0 to M3.

In the first specific example shown in FIG.
In the G decoder, I2 image → B0 image → B1 image →
The decoding process is performed in the order of P6 image → B3 image → B4 image → B5 image → P10 image.
B0 image → B1 image → I2 image → B3 image → B4 image →
The images are displayed in the order of the B5 images.

In addition, B1 image, P6 image, B3 image, B4 image, B5 image, P10 after decoding of I2 image and B0 image, which must be performed prior to the display processing.
Each decoding process of the image is executed in synchronization with each display process of the B0 image, the B1 image, the I2 image, the B3 image, the B4 image, and the B5 image on a frame basis.

Further, the I2 image data is written into the frame memory M0 storing the initial value which is invalid data, and the B0 image data is stored into the frame memory M1 storing the initial value which is invalid data. Written, B
One image data is written to the frame memory M2 storing the initial value which is invalid data, and the P6 image data is written to the frame memory M1 which stores B0 image data which is displayed invalid data.

The B3 image data is a frame memory M for storing B1 image data which is displayed invalid data.
2, the B4 image data is written to the frame memory M3 storing the initial value which is invalid data, and the B5 image data is displayed as B3 which is displayed invalid data.
The P10 image data is written to the frame memory M0 for storing the I2 image data which is the displayed and referenced invalid data.

Therefore, for example, as shown in FIG.
When an error occurs in the B4 image data in the MPEG decoder, after the display of the B3 image is completed, the B3 image can be subjected to repeat processing based on the completely retained B3 image data without being overwritten. In this case, the B5 image data output from the MPEG decoder during the repeat display of the B3 image is the frame memory M3 storing the invalid B4 image data.
Is written to.

As described above, according to the first embodiment of the MPEG image display control method of the present invention, the MPEG decoder decodes one frame of the encoded image data within one frame display period, and outputs the decoded image data from the MPEG decoder. Since the decoded image data to be written is written to the frame memory storing the invalid data, if an error occurs in the decoded image data in the MPEG decoder, the image currently displayed is repeatedly displayed. By performing the error concealment process, it is possible to make the disturbance of the displayed image inconspicuous.

Second Embodiment of the MPEG Image Display Control Method of the Present Invention
Embodiments FIGS. 3 to 6 A second embodiment of the MPEG image display control method of the present invention is as follows.
In the first embodiment of the MPEG image display control method of the present invention, the decoding process of one frame of encoded image data is performed by using an image header (Picture Header) of the corresponding frame.
Thereafter, the processing starts before the image data (Picture Data) of the corresponding frame, and stops after the image header of the next frame and before the image data of the next frame.

FIG. 3 is a timing chart showing a specific example of the second embodiment of the MPEG image display control method of the present invention. FIG. 3A shows a decoded image output from an MPEG decoder, and FIG. 3B shows a display image displayed on a display. FIG. 3C shows a decoded image stored in the frame memories M0 to M3.

DEC means that the frame memory is assigned as a frame memory for storing decoded image data, DISP means that the frame memory is assigned as a frame memory for storing display image data, BWD means that the frame memory is allocated as a backward reference image data storage frame memory, and FWD means that the frame memory is allocated as a forward reference image data storage frame memory.

The frame memory allocated as the decoded image data storage frame memory has an MPEG format.
The decoded image data output from the decoder is stored, and the decoded image data stored in the frame memory allocated as the display image data storage frame memory is treated as the display image data, and is allocated as the backward reference image data storage frame memory. The decoded image data stored in the frame memory that is stored is treated as backward reference image data, and the decoded image data stored in the frame memory allocated as the forward reference image data storage frame memory is treated as forward reference image data. become.

In the specific example shown in FIG. 3, in the B0 image display frame, the image data of the B1 image stream and the image header (PHD) of the P6 image stream are decoded, and in the B1 image display frame, the image data of the P6 image stream is decoded. And the image header of the B3 image stream are decoded. At the time of the I2 image display frame, the image data of the B3 image stream and the image header of the B4 image stream are decoded.
The image data of the four image streams and the image header of the B5 image stream are decoded.

FIG. 4 shows an example of the operation of allocating reference image data. The reference image data used by the MPEG decoder for decoding is determined by the image type of the decoded image. For example, when the decoded image is a B image, the transition of the reference image allocation does not occur. However, when the decoded image is the I image or the P image, the decoded image allocated as the backward reference image data (BWD). A change in assignment occurs, such as a transition of data to forward reference image data (FWD). As described above, the MPEG decoder cannot determine whether to assign the reference image data to the backward reference image data or the forward reference image data only after the image type of the decoded image is determined.

FIG. 5 schematically shows the structure of an MPEG stream. One frame image stream has a structure in which image data follows an image header. When the processing is performed in synchronization with the one-frame display processing, for example, as shown in FIG. 6, at the end of the display of the B0 image, the image header of the P6 image, which is the next decoded image, has not been decoded. Since it is not known that the image is the P6 image, the I2 image data cannot be allocated at the timing of the change of the allocation of the display frame from the B0 image to the B1 image, and after the decoding of the image header of the P6 image stream, Otherwise, I2 image data cannot be allocated.

At the end of the display of the B1 image, the image header of the B3 image which is the next decoded image has not been decoded, and it is not known that the next decoded image is the B3 image. The P6 image data cannot be allocated at the timing of the change of the display frame allocation to the I2 image, and the P6 image data cannot be allocated unless the image header of the B3 image stream is decoded. . To avoid such inconvenience, extremely complicated control is required.

However, in the specific example shown in FIG.
When displaying the B0 image, since the image header of the P6 image stream is decoded after the image data of the B1 image stream, the next image to be decoded is determined to be the P6 image, and the display frame from the B0 image to the B1 image is displayed. The inconvenience that the I2 image data cannot be allocated at the timing of the allocation change does not occur, and the image header of the B3 image stream is decoded after the image data of the P6 image stream when displaying the B1 image. The inconvenience that P6 image data cannot be allocated at the timing of the change in the allocation of the display frame from the B1 image to the I2 image does not occur.

As described above, according to the second embodiment of the MPEG image display control method of the present invention, in the first embodiment of the MPEG image display control method of the present invention, decoding of one frame of encoded image data is performed by: Since it starts after the image header of the corresponding frame and before the image data of the corresponding frame and stops after the image header of the next frame and before the image data of the next frame, the MPEG of the present invention is used.
The same operation and effect as the first embodiment of the image display control method can be obtained, and the inconvenience that the reference image data cannot be allocated at the timing of the change of the allocation of the display frame without performing complicated control. Can be avoided.

Third Embodiment of the MPEG Image Display Control Method of the Present Invention
Embodiment FIG. 7 A third embodiment of the MPEG image display control method of the present invention is as follows.
In the first embodiment of the MPEG image display control method of the present invention, if the decoding process of one frame of encoded image data is not completed within one frame display period,
The currently displayed frame image is displayed repeatedly.

FIG. 7 is a timing chart showing a specific example of the third embodiment of the MPEG image display control method of the present invention. FIG. 7A shows a decoded image output from an MPEG decoder, and FIG. 7B shows a display image displayed on a display. In the specific example shown in FIG. 7, since the decoding of the B3 image is not completed at the end of the display of the I2 image, the repeat display of the I2 image is performed, and the next B
The decoding processing of the four images and the display processing of the B3 image are synchronized.

As described above, according to the third embodiment of the MPEG image display control method of the present invention, in the first embodiment of the MPEG image display control method of the present invention, one frame of the encoded image is displayed within one frame display period. If the data decoding process is not completed, the currently displayed frame image is repeatedly displayed, so that the same operation and effect as the first embodiment of the MPEG image display control method of the present invention can be obtained. In addition, even if decoding of one frame of encoded image data is not completed within one frame display period due to delay of an input stream, decoding and display processing can be performed without performing inconvenient image display. Can be synchronized with.

Fourth Embodiment of the MPEG Image Display Control Method of the Present Invention
Embodiment: FIG. 8 A fourth embodiment of the MPEG image display control method of the present invention is as follows.
In the first embodiment of the MPEG image display control method according to the present invention, when repeat display is performed, the decoding process waits until a display switching timing after the end of the repeat display.

FIG. 8 is a timing chart showing a specific example of the fourth embodiment of the MPEG image display control method of the present invention. FIG. 8A shows a decoded image output from an MPEG decoder, and FIG. 8B shows a display image displayed on a display. 8 shows an example in which the I2 image is repeatedly displayed, and the decoding process of the B4 image is on standby until the display switching timing after the end of the repeat display of the I2 image. In the case of repeat display, switching of frame memory allocation is not performed.

As described above, according to the fourth embodiment of the MPEG image display control method of the present invention, when the repeat display is performed in the first embodiment of the MPEG image display control method of the present invention, Since the decoding process is to wait until the display switching timing after the end,
The same operation and effect as those of the first embodiment of the present invention can be obtained. In addition, when the repeat display is performed by a repeat display instruction included in the MPEG stream or an external display stop instruction, the decoding process can be performed. Synchronization with display processing can be achieved.

FIG. 9 is a block circuit diagram showing an essential part of an MPEG image display device provided with an embodiment of the MPEG image display control device of the present invention. 9, 8 is a display, 9 is an MPEG
1 is an embodiment of an MPEG image display control device of the present invention that decodes a stream and controls image display.

Further, in the ninth embodiment of the MPEG image display control apparatus according to the present invention, reference numeral 10 denotes a unit for decoding one frame of encoded image data within one frame display period, and one frame of encoded image data. Is started after the image header of the corresponding frame and before the image data of the corresponding frame, and is stopped after the image header of the next frame and before the image data of the next frame.
G decoder.

Reference numerals 11-0 to 11-3 denote frame memories for storing decoded image data output from the MPEG decoder 10 on a frame basis, and reference numeral 12 denotes a frame memory 11-0 for storing decoded image data output from the MPEG decoder 10. 11-3, and the distribution operation of the distribution circuit 12 is controlled by a decoded image data storage frame memory designation signal dec output from the MPEG decoder 10.

Reference numeral 13 denotes frame memories 11-0 to 1-1.
A selector for selecting any one of 1-3 and outputting decoded image data output from the selected frame memory;
14 selects the forward reference image data storage frame memory designation signal fwd or the backward reference image data storage frame memory designation signal bwd or the display image data storage frame memory designation signal disp output from the MPEG decoder 10 and selects and controls the selected signal. When the decoded image data output from the selector 13 is display image data, the selector 15 supplies the decoded image data to the selector 13 as a signal to control image display on the display 8.

In the MPEG decoder 10, 1
6 assigns each of the frame memories 11-0 to 11-3 to the decoded image data storage frame memory,
A frame memory allocation switching timing signal CHANGE for controlling switching timing of frame memory allocation for allocating to the forward reference image data storage frame memory, allocating to the backward reference image data storage frame memory, or allocating to the display image data storage frame memory. This is a frame memory allocation switching timing signal generation unit that outputs in synchronization with the frame synchronization signal FSYNC supplied from the control unit 15.

The frame memory allocation switching timing signal generator 16 includes a decode delay detector 17 for detecting a case where the decoding of one frame of encoded image data has not been completed within one frame display period, and an MPE.
A display repeat control unit for controlling display repeat in response to a repeat display instruction included in the G stream or an external display stop instruction, and the like; a decode delay detecting unit detecting a decoding delay or a display repeat control; When the section 18 instructs the display repeat, the frame memory allocation switching timing signal C
It is configured to mask HANGE.

Reference numeral 19 denotes a frame memory allocation control unit which controls the allocation of the frame memories 11-0 to 11-3 in synchronization with the frame memory allocation switching timing signal CHANGE, and 20 designates a frame memory for storing decoded image data. This is a decoded image data storage frame memory designation register. The content of the decoded image data storage frame memory designation register 20 is a decoded image data storage frame memory designation signal de.
It is supplied to the distribution circuit 12 as c.

The decoded image data storage frame memory designation register 20 stores the decoded image data output from the MPEG decoder 10 in the frame memory 11-0.
11-3, the contents are set so as to be written to the frame memory storing the invalid data.

Reference numeral 21 designates a forward reference image data storage frame memory designation register for designating a forward reference image data storage frame memory; 22 designates a backward reference image data storage frame memory designation register for designating a backward reference image data storage frame memory; Is a display image data storage frame memory designation register for designating a display image data storage frame memory.

Here, the content of the forward reference image data storage frame memory designation register 21 is input to the selector 14 as the forward reference image data storage frame memory designation signal fwd, and the content of the backward reference image data storage frame memory designation register 22 is entered backward. Is input to the selector 14 as a reference image data storage frame memory designation signal bwd,
The content of the display image data storage frame memory designation register 23 is the display image data storage frame memory designation signal di.
This is input to the selector 14 as sp.

Reference numeral 24 denotes frame memories 11-0 to 1-1.
1-3 is a memory control unit that controls which of the forward reference image data, the backward reference image data, and the display image data should be output. The selector 14 outputs the forward reference image data from the memory control unit 24. When the memory control unit 24 should output the backward reference image data, the forward reference image data storage frame memory designation signal fwd is selected. When the selection is made and the memory control unit 24 should output the display image data, the display image data storage frame memory designation signal disp is selected.

When the forward reference image data storage frame memory designation signal fwd is supplied, the selector 13 selects the output of the frame memory designated by the forward reference image data storage frame memory designation signal fwd, and When the data storage frame memory designation signal bwd is supplied, the output of the frame memory designated by the backward reference image data storage frame memory designation signal bwd is selected, and the display image data storage frame memory designation signal di is selected.
When sp is supplied, the output of the frame memory designated by the display image data storage frame memory designation signal disp is selected.

The MP having the ninth embodiment of the MPEG image display control apparatus of the present invention shown in FIG.
In the EG image display device, the MPEG decoder 10
Is to decode one frame of encoded image data within one frame display period, and to start decoding one frame of encoded image data after the image header of the frame and before the image data of the frame. Then, the MPEG stream is decoded by stopping after the image header of the next frame and before the image data of the next frame, and the decoded image data output from the MPEG decoder 10 is stored in the frame memory 11-0.
11 to 11-3, the invalid data is stored in the frame memory storing the invalid data.

That is, according to the ninth embodiment of the MPEG image display control device of the present invention, it is possible to execute the first and second embodiments of the MPEG image display control method of the present invention. In the case where no error has occurred in the decoded image data, the operation as shown in FIG.
For example, when an error occurs in the B4 image, the B3 image is repeatedly displayed as shown in FIG.

FIGS. 10A and 11A show a frame synchronizing signal FSYNC output from the display control unit 15, FIG.
10B and FIG. 11B are frame memory allocation switching timing signals CHANGE output from the frame memory allocation switching timing signal generation unit 16;
11C and 11C are decoded images output from the MPEG decoder 10, FIGS. 10D and 11D are assignment states of the frame memories 11-0 to 11-3, and FIGS.
1E shows a decoded image stored in the frame memories 11-0 to 11-3.

In the ninth embodiment of the MPEG image display control device according to the present invention, one frame is displayed within one frame display period.
When the decoding processing of the encoded image data of the frame is not completed, the decoding delay detection unit 17 detects this, and the frame memory allocation switching timing signal CHANGE is masked, so that the allocation of the frame memory is switched. Will not be.

When a repeat display instruction included in the MPEG stream or an external display stop instruction or the like is issued, the display repeat control unit 18 instructs display repeat. Also,
Frame memory allocation switching timing signal CHA
The NGE is masked, and the allocation of the frame memory is not switched.

That is, according to the ninth embodiment of the MPEG image display control device of the present invention, the third and fourth embodiments of the MPEG image display control method of the present invention can be executed. When the decoding process of the B1 image data is not completed within the frame display period, or when the repeat display instruction of the I2 image is issued, for example, FIG.
The operation will be as shown in FIG.

FIG. 12A shows the frame synchronization signal FSYNC output from the display control unit 15, and FIG. 12B shows the decode delay detection signal DE output from the decode delay unit 17.
LAY, FIG. 12C is a display repeat instruction signal REPEAT output from the display repeat control unit 18, and FIG. 12D is a frame memory allocation switching timing signal generation unit 1.
12E is a decoded image output from the MPEG decoder 10, FIG. 12F is an allocation state of the frame memories 11-0 to 11-3, and FIG. 12G is a frame memory 11-0. 11 to 11-3 show the decoded images stored.

As described above, according to the ninth embodiment of the MPEG image display control apparatus of the present invention, the first to fourth embodiments of the MPEG image display control method of the present invention can be executed. (1) In the case where an error occurs in decoded image data in the MPEG decoder 10, a simple error concealment process of repeatedly displaying the currently displayed image is performed so that disturbance of the displayed image is not noticeable. (2) it is possible to avoid the inconvenience that reference image data cannot be allocated at the timing of display frame allocation change without performing complicated control, and (3) input stream delay For example, the decoding process of one frame of the encoded image data did not end within one frame display period. Also in case, by performing the repeat display, without undesirable image display, can be synchronized with the display processing decoding, (4) M
Even when a repeat display is performed by a repeat display instruction included in the PEG stream or an external display stop instruction, the decoding process and the display process can be synchronized.

Here, the contents of the MPEG image display control method and apparatus of the present invention will be summarized. The MPEG image display control method and apparatus of the present invention include at least the following MPE.
A G image display control method and device are included.

[1] In the MPEG decoder, the decoding process of the MPEG stream is performed so that the decoding process of the encoded image data of one frame is performed within one frame display period, and the decoded image data output from the MPEG decoder is converted into a frame. An MPEG image display control method characterized by including a step of writing, in units, invalid data into a frame memory storing the invalid data.

[2] In the MPEG image display control method according to the above [1], the decoding process of the encoded image data of the one frame is started after the image header of the frame and before the image data of the frame. An MPEG image display control method, comprising: stopping after an image header of a next frame and before the image data of the next frame.

[3] In the MPEG image display control method according to [1], if the decoding process of the encoded image data of one frame is not completed within one frame display period, the current display is performed. MPEG, wherein the frame image is displayed repeatedly, and the next decoding process is not performed until the next display switching is performed.
Image display control method.

[4] In the MPEG image display control method according to [1], when repeat display is performed,
An MPEG image display control method, wherein a decoding process is waited until a display switching timing after the end of the repeat display.

[5] An MPEG decoder that decodes an MPEG stream by performing decoding of one frame of encoded image data within one frame display period, a display image data storage frame memory, a decoded image data storage frame memory, and The display image data storage frame memory, the decoded image data storage frame memory, and the first and second display image data storage frame memories so that the first and second reference image data storage frame memories simultaneously exist.
An MPEG image display control device, comprising: a plurality of frame memories which are switchably assigned to any of the reference image data storage frame memories.

[6] In the MPEG image display control device according to the above [5], the MPEG decoder performs a decoding process on the encoded image data of one frame.
An MPEG image display control device, which starts after an image header of a corresponding frame and before the image data of the corresponding frame, and stops after an image header of the next frame and before the image data of the next frame.

[7] In the MPEG image display control device according to the above [5], the MPEG decoder performs decoding of the encoded image data of one frame by one.
MPEG image display control, characterized in that if not completed within the frame display period, the currently displayed frame image is displayed repeatedly, and the next decoding process is not performed until the next display switching is performed. apparatus.

[8] In the MPEG image display control device according to the above [5], when performing the repeat display, the MPEG decoder waits for a decoding process until a display switching timing after the end of the repeat display. A characteristic MPEG image display control device.

[0067]

As described above, according to the MPEG image display control method of the present invention, the decoding process and the display process can be synchronized on a frame basis, and the decoded image data output from the MPEG decoder can be synchronized. Can be stored in the frame memory storing the invalid data and not written into the frame memory storing the decoded image data which is the base data of the image currently displayed. When an error occurs in the decoded image data, a simple error concealment process of repeatedly displaying the currently displayed image can be performed so that the disturbance of the displayed image is not noticeable.

According to the MPEG image display control device of the present invention, the MPEG image display control method of the present invention is executed, and when an error occurs in decoded image data in the MPEG decoder, the currently displayed image is displayed. By performing a simple error concealment process of performing a repeat display, it is possible to make disturbance of a display image inconspicuous.

[Brief description of the drawings]

FIG. 1 is a timing chart showing a first specific example of the first embodiment of the MPEG image display control method of the present invention.

FIG. 2 is a timing chart showing a second specific example of the first embodiment of the MPEG image display control method of the present invention.

FIG. 3 is a timing chart showing a specific example of a second embodiment of the MPEG image display control method of the present invention.

FIG. 4 is a timing chart showing an example of an operation of allocating reference image data.

FIG. 5 is a diagram schematically showing a structure of an MPEG stream.

FIG. 6 shows decoding processing of one frame image stream as 1
6 is a timing chart for explaining a problem that occurs when the processing is performed in synchronization with the frame display processing.

FIG. 7 is a timing chart showing a specific example of the third embodiment of the MPEG image display control method of the present invention.

FIG. 8 is a timing chart showing a specific example of the fourth embodiment of the MPEG image display control method of the present invention.

FIG. 9 is a block circuit diagram showing a main part of an MPEG image display device including one embodiment of the MPEG image display control device of the present invention.

10 is a timing chart showing a first operation example of the MPEG image display device shown in FIG.

11 is a timing chart showing a second operation example of the MPEG image display device shown in FIG.

12 is a timing chart showing a third operation example of the MPEG image display device shown in FIG.

FIG. 13 is a block circuit diagram showing a main part of an example of a conventional MPEG image display device.

FIG. 14 is a timing chart showing an operation example of the conventional MPEG image display device shown in FIG.

FIG. 15 is a timing chart for explaining problems of the conventional MPEG image display control device shown in FIG.

[Explanation of symbols]

(FIG. 9) 20 Decoded image data storage frame memory specification register 21 Forward reference image data storage frame memory specification register 22 Back reference image data storage frame memory specification register 23 Display image data storage frame memory specification register dec Decoded image data storage frame memory specification Signal fwd Forward reference image data storage frame memory designation signal bwd Rear reference image data storage frame memory designation signal disp Display image data storage frame memory designation signal FSYNC Frame synchronization signal CHANGE Frame memory allocation switching timing signal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) CA85 CB01 DA54 MM10

Claims (2)

[Claims] An MPEG decoder decodes an MPEG stream so that one frame of encoded image data is decoded within one frame display period, and decodes the decoded image data output from the MPEG decoder in frame units. A step of writing invalid data into a frame memory storing invalid data. 2. A method of decoding one frame of encoded image data within one frame display period.
The display image data storage frame memory so that the MPEG decoder for decoding the EG stream, the display image data storage frame memory, the decoded image data storage frame memory, and the first and second reference image data storage frame memories simultaneously exist. An MPEG image display control device, comprising: a plurality of frame memories that are switchably assigned to one of the decoded image data storage frame memory and the first and second reference image data storage frame memories.