JP2001125691A - Computer and CPU intermittent operation control method - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide a computer having a noise prevention function and a CPU intermittent operation control method capable of suppressing a constant frequency noise that may be generated during a power saving operation. And A power saving circuit performs an intermittent control under a control of a BIOS to repeat an operation state and a stop state so as to prevent the CPU from being continuously operated at the same cycle during a power saving operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer having control means for intermittently operating a CPU, and a CPU.
The present invention relates to an intermittent operation control method.

[0002]

2. Description of the Related Art In a personal computer which is easy to carry and can be driven by a battery power source, a control means for intermittently operating a CPU by alternately switching the CPU between an operating state and a stopped state as one measure for power saving. Exists. As a specific example, in JP-A-7-200111 (computer system), the operating speed of the CPU in the sleep mode is reduced by duty control in the stop grant state and the normal state. In Japanese Patent Application Laid-Open No. 10-198564 (data processor and its operation method), the power consumption of the data processor is reduced by throttling control.

However, in the conventional intermittent control of this kind of CPU, since the operation state and the stop state of the CPU are repeated at a constant cycle, there are the following problems.

That is, in the conventional intermittent control of the CPU, as shown in FIG. 6, the operation state and the stop state of the CPU are repeated at a constant cycle. In FIG. 6, T21 is the time when the CPU is in the operating state, T22 is the time when the CPU is in the stopped state, and T23 is the time of one cycle (T21 + T22).
The performance of the CPU can be adjusted by the ratio (duty) between T21 and T22. The power consumption of the CPU is different between when the CPU is operating and when it is stopped, and the difference in power consumption causes a voltage change. Specifically, the voltage of the power supply terminal of the CPU increases when the CPU shifts from the operating state to the stop state, and the voltage of the power supply terminal of the CPU decreases when the CPU shifts from the stop state to the operating state. This voltage fluctuation causes a voltage effect and causes the ceramic capacitor connected to the power supply circuit of the CPU to vibrate. The cycle of the vibration at this time is determined by T23. T2
If the period of 3 is in the audible range, the ceramic capacitor vibrates and generates noise. Further, when the ceramic capacitor vibrates, it resonates with the mounting board or the like, and the noise is further amplified.

Further, in the conventional intermittent control of the CPU, since the operating state and the stopped state of the CPU are repeated at a constant period as described above, the performance of the CPU is constant during that time, and thus the performance of the CPU is reduced. Efficient control of CPU performance, such as changing according to the processing load, cannot be performed, that is, precise power control for reducing power consumption cannot be performed.

[0006]

As described above, in the conventional intermittent control of the CPU, the operation state and the stop state of the CPU are repeated at a constant cycle. Therefore, when the cycle is in the audible range, the ceramic capacitor is not used. There was a problem that vibration and noise were generated.

[0007] While the operation state and the stop state of the CPU are repeated at a constant cycle, the performance of the CPU is constant.
Therefore, there is a problem that efficient control of CPU performance such as varying the performance of the CPU according to a processing load or the like cannot be performed, that is, precise power control for reducing power consumption cannot be performed.

[0008] The present invention has been made in view of the above circumstances,
Computer and CP with noise prevention function capable of suppressing constant frequency noise that may occur during power saving operation
An object of the present invention is to provide an intermittent operation control method for U.

Further, the present invention provides a power saving control period,
Computer with noise prevention function capable of performing precise power saving control without waste without deteriorating CPU performance and C
An object of the present invention is to provide a method of controlling an intermittent operation of a PU.

[0010] The present invention also provides a power-saving control period.
The vibration of the ceramic capacitor connected to the power supply circuit of the CPU is suppressed by electrical control, whereby the noise due to the vibration of the ceramic capacitor can be easily and reliably suppressed without performing physical measures.
An object of the present invention is to provide a computer having a noise prevention function and a method of controlling an intermittent operation of a CPU capable of precisely controlling the performance of a PU in accordance with a processing load or the like and efficiently performing power saving control.

[0011]

According to the present invention, a cycle in which a CPU repeats an operation state and a stop state during power saving control,
The period or the duty is switched while the PU remains in the operating state, and the time width of the cycle is changed so that the cycle of repeating the operating state and the stop state of the CPU in the power saving control period is not fixed to a constant frequency. With this, it is possible to suppress the noise generated in the audible range by eliminating the vibration of the ceramic capacitor provided in the power supply circuit of the CPU, and to perform the precise power saving control without wasting without deteriorating the performance of the CPU. Can be performed.

That is, according to the present invention, in a computer having a power saving control means for intermittently operating a CPU, the CPU intermittently operates by changing a cycle of an operation state and a stop state and a period of the operation state. It is characterized by comprising control means.

According to the present invention, there is provided a computer comprising a power saving control means for intermittently operating a CPU, wherein a cycle and a duty of an operating state and a stopped state are varied to change the CPU.
Is provided with control means for intermittently operating.

According to the present invention, in a computer having a power saving control means for intermittently operating a CPU, a plurality of types of control information for specifying a cycle of an operation state and a stop state and a period of the operation state are specified. A control means is provided in which a plurality of types of control information are prepared in advance, and using the control information, the cycle of the operation state and the stop state and the period of the operation state of the CPU are variably controlled according to the temperature change of the CPU. It is characterized by becoming.

According to another aspect of the present invention, there is provided a computer having a power saving control means for intermittently operating a CPU, a plurality of types of control information for designating a period of an operation state and a stop state, and a duty of the operation state and a stop state. Are prepared in advance, and using the control information, C
It is characterized by comprising control means for variably controlling the cycle and duty of the operation state and the stop state of the CPU according to the load state of the PU.

The present invention also relates to a computer having a power saving control means for intermittently operating a CPU.
A first means for changing the period of the operating state and the stopped state of U, a second means for changing the period of the operating state of the CPU, and a CPU for switching between the first means and the second means.
And means for intermittently operating.

The present invention is also applicable to a computer having power saving control means for intermittently operating a CPU.
A method of controlling an intermittent operation of a PU, wherein a cycle of an operation state and a stop state of the CPU and a period of the operation state of the CPU in the intermittent operation of the CPU are changed, so that the CPU is the same during the power saving control period. The intermittent operation is not performed continuously in the above cycle.

The present invention also relates to the above intermittent operation control method for a CPU, wherein the intermittent operation of the CPU includes at least a cycle of the operation state and a stop state and a period of the operation state, at least a change in the temperature of the CPU, It is characterized in that it is changed according to any of the load states.

The present invention is also applied to a computer having power saving control means for intermittently operating a CPU.
A PU intermittent operation control method, wherein a cycle and a duty of an operation state and a stop state of the CPU during the intermittent operation of the CPU are changed, and the CPU is controlled during the power saving control period.
Are not operated intermittently in the same cycle.

The present invention also relates to the above intermittent operation control method for a CPU, wherein at the time of the intermittent operation of the CPU, the cycle and duty of the operation state and the stop state of the CPU are changed at least by the temperature change of the CPU and the load state of the CPU. It is characterized in that it is changed according to any of them.

According to the present invention, there is provided a CPU for performing arithmetic processing,
In a computer having a control means for performing an intermittent operation of repeating the CPU between an operating state and a stopped state, and an element which vibrates when the intermittent operation by the control means becomes periodic, the vibration of the element is controlled by the intermittent operation. Characterized in that it is provided with means for reducing by changing

According to the present invention, there is also provided an intermittent operation control of a CPU which is applied to a computer on which a vibrating element is mounted when the intermittent operation is periodically repeated when the CPU is intermittently operated between an operating state and a stopped state. A method, wherein the vibration of the element is reduced by changing the intermittent operation.

By providing the intermittent operation control function of the CPU as described above, it is possible to reliably suppress a constant frequency noise that may occur during the power saving operation. Also, CPU
And precise power saving control without waste can be performed without deteriorating the performance. Specifically, by providing the above-described intermittent operation control function of the CPU, the vibration of the ceramic capacitor connected to the power supply circuit of the CPU can be suppressed by electrical control. It is possible to simply and surely suppress the power consumption without taking any appropriate measures, and to perform the power-saving control precisely by efficiently and variably controlling the performance of the CPU according to the processing load or the like.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of a computer according to the first embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a CPU for controlling the entire system.
In the power saving operation, the operation state and the stop state are repeated so as not to continuously perform the intermittent operation at the same cycle during the power saving operation. For example, the operation is performed by the intermittent control as shown in FIG. Vc is a power supply for operation of the CPU 11, and c is C
This is a bypass ceramic capacitor provided in the power supply circuit of the PU 11 and subject to vibration suppression.

Reference numeral 12 denotes a power saving circuit for controlling the CPU 11 to perform an intermittent operation during the power saving operation.
Under the control of 3, the operation state and the stop state are repeated so that the CPU 11 is not intermittently operated continuously in the same cycle.
For example, intermittent control as shown in FIG. 2 is performed.

Reference numeral 13 denotes a BIOS which causes the power saving circuit 12 to execute an intermittent control of repeating an operating state and a stopped state so that the CPU 11 is not continuously operated at the same cycle during the power saving operation. The power saving circuit 12 executes the intermittent control as shown in FIG.

Reference numeral 14 denotes other circuits including peripheral circuits of the CPU 11, which are circuits which are not directly related to the present invention, and a description thereof will be omitted.

FIG. 2 is a time chart showing the intermittent control timing of the CPU 11 during the power saving operation in the above-described embodiment. In the figure, T31 is a time when the CPU 11 is in an operating state, and T32 is a time when the CPU 11 is in a stopped state. Time. T33 is one cycle of (T3 and T32) (T3
1 + T32). T34 is the time during which T33 is continuous. T35 is a time during which the CPU 11 is in the operating state. Here, T34 and T35 described above are alternately repeated.

Here, the CPU 11 of the above-mentioned T33 and T34
Is (T31 ÷ T33 × 100)%. The operation rate of the CPU 11 at T35 is 100%.

The operating rate of the CPU 11 by this setting is ((T31 + T35) ÷ (T34 + T35) × 100).
%become.

During the period T34, since the cycle is constant, noise may be generated due to the vibration of the ceramic capacitor. However, during the period T35, no noise is generated because the state of the CPU 11 does not change. Since the time during which noise is generated and the time during which noise is not generated are alternately repeated in this manner, by setting the period of T35 to be as large as the system allows, the CPU 11 operates in the power saving mode.
The noise can be greatly reduced without lowering the performance of.

FIG. 3 shows a BIOS 13 for implementing intermittent control of the CPU 11 as shown in FIG. 2 during power saving control.
7 is a flowchart showing the processing procedure of FIG. 5, in the power saving mode, the setting processing shown in the figure is performed each time an interrupt occurs due to the interrupt time of the duty change set here.

The operation of the first embodiment of the present invention will now be described with reference to the drawings.

Under the control of the BIOS 13, the power saving circuit 12 repeats the operation state and the stop state so that the CPU 11 does not operate intermittently at the same cycle during the power saving operation, as shown in FIG. Perform intermittent control.

Here, in the processing of the normal main routine in the power saving control operation, when an interruption of the duty change occurs, the current duty setting content is determined (step S11 in FIG. 3), and the duty setting content is determined. According to the operation control mode indicated by T35 in FIG. 2 (hereinafter referred to as “duty 100%”), FIG.
An operation control mode indicated by reference numeral 33 (herein referred to as “duty T31 / T33”) is alternately set.

That is, the current duty setting content is "duty 100%" (duty = 100) indicated by T35 in FIG.
%), “Duty T31 / T33” (duty = T31 / T33) indicated by T31 / T33 in FIG. 2 is set (step S12 in FIG. 3), and the current duty setting content is “duty”. T31 / T33 ”(duty = T31 / T3
If 3), then “duty 100%” (duty = 100
%) Is set (step S14 in FIG. 3).

Here, "duty T31 / T33"
When (duty = T31 / T33) is set (step S12 in FIG. 3), the interrupt generation time of the next duty change (T34)
Is set (step S13 in FIG. 3), and “duty 100
% "(Duty = 100%) is set (step S14 in FIG. 3), the interrupt generation time (T3
5) is set (step S15 in FIG. 3), and the interrupt processing for the duty change is terminated.

In this way, every time a duty change interrupt occurs, the next duty change interrupt generation time (T3
4 / T35) is set (step S13 / S1 in FIG. 3).
5) At the set time, the above-described interrupt processing is repeatedly executed.

According to the setting contents under the control of the BIOS 13, the power saving circuit 12 operates in the power saving control so that the CPU 11 does not operate continuously and intermittently at the same cycle as shown in FIG. And the stop state are repeatedly controlled.

With the intermittent operation control function of the CPU 11, the vibration of the ceramic capacitor (c) connected to the power supply circuit of the CPU 11 can be suppressed by electrical control. This makes it possible to easily and reliably suppress noise due to the vibration of the ceramic capacitor (c) without performing physical measures, and to efficiently and variably control the performance of the CPU 11 according to the processing load and the like to save power. Can be performed precisely.

Next, a second embodiment of the present invention will be described with reference to FIG.

Here, in the interruption process of the duty change under the control of the BIOS 13, the CPU 11
By using a plurality of types of periods and duties of the operation state and the stop state, and switching and setting these, power saving control with further reduced noise can be performed.

FIG. 4 is a time chart showing the intermittent control timing of the CPU 11 during the power saving operation in the second embodiment. In FIG. 4, T41 and T45 denote the time when the CPU 11 is in the operating state, and T42 and T46 denote the time when the CPU 11 is in the operating state. This is the time when the CPU 11 is in the stop state. T43 is one cycle (T41 + T4
It is time 2). T44 is the time during which T43 continues. T47 is the time of one cycle (T45 + T46).
T48 is a time during which T47 is continuous. Here, T44
And T48 are alternately repeated.

Here, the CPU 11 of the above T43 and T44
Is (T41 ÷ T43 × 100)%.

The operating rate of the CPU 11 in T47 and T48 is (T45 ÷ T47 × 100)%.

The operating rate of the CPU 11 set as above is ((T4
1 ÷ T43) ÷ (T44 ÷ (T44 + T48)) +
((T45 ÷ T47) × (T48 ÷ (T44 + T4
8))) × 100%.

As described above, in the second embodiment of the present invention, the cycle of the operation state and the stop state of the CPU 11 and a plurality of types of duties are used, and the CPU 1 performs the power saving control.
By setting the performance of No. 1, the performance of the CPU 11 can be finely adjusted as compared with the conventional power consumption reduction method, and the noise due to the vibration of the ceramic capacitor (c) provided in the power supply circuit of the CPU 11 can be further reduced. .

Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 5 is a block diagram showing the configuration of a main part of a computer according to a third embodiment of the present invention. Here, the same components as those of the above-described first embodiment shown in FIG. And description thereof is omitted.

In the third embodiment, a temperature sensor 15 for detecting the temperature of the CPU 11 is added to the configuration of the first embodiment described above, and the temperature information detected by the temperature sensor 15 is transmitted to a circuit 14. Input to the power saving circuit 12 via
The performance of the CPU 11 is adjusted in consideration of the temperature detected by the temperature sensor 15.

The temperature sensor 15 is arranged near the CPU 11 or built in the CPU 11 to measure the temperature of the CPU 11.

Using the performance adjusting means of the CPU 11 of the second embodiment described above in the third embodiment shown in FIG.
By changing the performance of the CPU 11 in accordance with a change in the temperature of the CPU 11, C
The performance of the PU 11 can be finely adjusted and the CPU 1
Ceramic capacitor (c) provided in one power supply circuit
Can be further reduced by the vibration of
Heat generation of the PU 11 can be suppressed. Specifically, CP
When the temperature of U11 increases, control is performed so as to reduce the performance of the CPU 11 and suppress heat generation. Thereby, the CPU 1
1 can be more finely adjusted, and heat generation of the CPU 11 can be suppressed while minimizing performance deterioration of the CPU 11.

As described above, according to the embodiment of the present invention, under the power saving control, the control for switching the period of the operation state and the stop state of the CPU 11 and the control for switching the period during which the CPU 11 remains in the operation state are added. Accordingly, the noise of the ceramic capacitor (c) which may occur in the audible range depending on the cycle of the operation state and the stop state of the CPU 11 can be significantly reduced.

Further, by adding a control for preparing and switching a plurality of types of periods and duties of the operation state and the stop state of the CPU, the operation rate of the CPU 11 can be freely changed. Performance can be changed freely.

Further, by adding a control for preparing and switching a plurality of types of periods and duties of the operation state and the stop state of the CPU 11, the operation rate of the CPU can be freely changed in accordance with the temperature state of the CPU 11, and the CPU can be freely changed. Heat generation can be suppressed.

Further, by adding control for preparing and switching a plurality of cycles and duties of the operation state and the stop state of the CPU 11, the operation rate of the CPU 11 can be freely changed according to the load state of the CPU 11, and the heat generation of the CPU 11 can be changed. And the power consumption of the computer device can be suppressed.

The various set times and periods applied to the present invention and the switching pattern of the operating state / stop state of the CPU and the like are not limited to those of the above-described embodiments, and the range in which the switching control is permitted. More types are applicable in.

In the above-described embodiment, the ceramic capacitor provided in the power supply circuit of the CPU is targeted for noise suppression. However, the present invention is not limited to this. The intermittent control according to the present invention can also be applied to various circuit components.

[0061]

As described above in detail, according to the present invention, a computer and a CPU having a noise prevention function capable of suppressing a constant frequency noise that may occur during a power saving operation.
An intermittent operation control method can be provided.

Further, it is possible to provide a computer having a noise prevention function and a CPU intermittent operation control method capable of performing precise power saving control without loss of performance of the CPU during the power saving control period.

Further, during the power saving control period, the vibration of the ceramic capacitor connected to the power supply circuit of the CPU is suppressed by the electric control, so that the noise due to the vibration of the ceramic capacitor can be reduced without physical treatment. Intermittent operation control of a computer and a CPU with a noise prevention function that can easily and reliably suppress the noise and efficiently perform variable power control of the CPU according to the processing load and the like. A method can be provided.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a configuration of a main part of a computer according to a first embodiment;

FIG. 2 is a time chart showing intermittent control timing of a CPU during a power saving operation in the embodiment.

FIG. 3 is a diagram illustrating a BIOS during power saving control in the embodiment.
9 is a flowchart showing an intermittent control processing procedure of a CPU by control.

FIG. 4 is a time chart showing intermittent control timing of a CPU during a power saving operation according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a main part of a computer according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operating state and a stopped state of a conventional CPU during power saving control.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... Power saving circuit 13 ... BIOS 14 ... Other circuits 15 ... Temperature sensor

Claims (11)

[Claims] 1. A computer comprising control means for intermittently operating a CPU by changing a cycle of an operation state and a stop state, and a period of an operation state. 2. A computer comprising control means for intermittently operating a CPU by changing a cycle and a duty of an operation state and a stop state. 3. A plurality of kinds of control information for designating a period of an operation state and a stop state and a plurality of kinds of control information for designating a period of an operation state are prepared in advance, and using the control information,
A computer characterized by comprising control means for variably controlling a cycle of an operation state and a stop state and a period of an operation state of the CPU according to a temperature change of the CPU. 4. A plurality of types of control information for designating periods of the operating state and the stopped state and a plurality of types of control information for designating the duty of the operating state and the stopped state are prepared in advance, and using the control information, Depending on the load state of the CPU, the CPU
A computer comprising control means for variably controlling the cycle and duty of the operation state and the stop state of the computer. 5. A first means for changing a cycle of the operation state and the stop state of the CPU, a second means for changing a period of the operation state of the CPU, and the first means and the second means. Means for switching and causing the CPU to intermittently operate. 6. A computer comprising a power saving control means for intermittently operating a CPU, wherein a cycle of an operating state and a stopped state of the CPU during the intermittent operation of the CPU is provided.
And an intermittent operation control method for the CPU, wherein the period of the operation state of the CPU is changed so that the CPU is not operated intermittently at the same cycle during the power saving control. 7. A computer comprising a power saving control means for intermittently operating a CPU, wherein a cycle and a duty of an operating state and a stopped state of the CPU during the intermittent operation of the CPU are changed to save power. CP during control period
A method of controlling intermittent operation of a CPU, wherein U is not continuously operated in the same cycle. 8. The CPU according to claim 6, wherein, during the intermittent operation of the CPU, the cycle of the operation state and the stop state of the CPU and the period of the operation state are changed according to at least one of a temperature change of the CPU and a load state of the CPU. CPU intermittent operation control method. 9. The CPU according to claim 7, wherein the cycle and the duty of the operation state and the stop state of the CPU during the intermittent operation of the CPU are changed according to at least one of a temperature change of the CPU and a load state of the CPU. Intermittent operation control method. 10. A CPU for performing arithmetic processing, and the CPU
Control means for performing an intermittent operation of repeating the operation state and the stop state, an element that vibrates when the intermittent operation by the control means becomes periodic, and means for reducing the vibration of the element by changing the intermittent operation. A computer comprising: a computer; 11. A computer on which an element that vibrates when the CPU is intermittently repeated between an operating state and a stopped state and the intermittent operation becomes periodic is mounted on the computer. A method for controlling intermittent operation of a CPU, characterized in that the CPU is reduced by changing the CPU.