JP2001134488A - Cache control method for disk storage device - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide means for enabling read cache control using a space of a buffer memory divided and managed in segments by dedicated hardware. . An HD which is an LSI for controlling a disk storage device.
In a C (Hard Disk Controller), a host address latch unit 105, a hit determination unit 106, a cache data table 107
have. Here, the hit determination unit 106 determines whether or not a cache hit has occurred by referring to the data in the cache data table 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an HDC (Hard Disk Controller) which is an LSI for controlling a disk storage device used in an integrated circuit on a substrate of a disk storage device, and more particularly to a read command issued by a host from the disk storage device. By performing the cache hit processing when hardware is received, the cache hit processing time is reduced,
In addition, the present invention relates to means for increasing the probability of a cache hit.

[0002]

2. Description of the Related Art A disk storage device as shown in FIG. 3 will be described as an example. The function of each part in FIG. 3 is described below.

The host 300 is a PC or the like.

An HDC (Hard Disk Controller) 301 is an LSI for managing data transfer of a disk storage device.

The buffer memory 302 is an area for temporarily storing data to be transferred from the host to the disk medium or from the disk medium to the host.

[0006] The R / W channel 303 is the disk medium 30.
5 is an LSI for reading and writing the data on the LSI.

The head 304 is a mechanism for reading and writing data on a disk medium.

The disk medium 305 is a rotary storage medium for recording data.

The MPU 306 is an LSI for controlling the entire disk storage device.

An MC (Motion Controller) 307 is an LSI for controlling the motor driver 308.

The motor driver 308 is a disk medium 30
5 is an LSI for performing the rotation control and the positioning control of the head 304.

The HDC 301 shown in FIG. 3 is configured as shown in FIG. The function of each part in FIG. 4 is described below.

The HBI 400 (Host Bus Interface) is a circuit for transmitting and receiving commands, parameters, and data to and from the host.

A DF 401 (Disk Formatter) is a circuit that controls reading and writing of data from and to a disk medium.

The BM 402 is a circuit for controlling a buffer memory.

An MPU I / F 403 is an interface circuit between the MPU and the HDC.

The Buffer Sector Counter 404 is a circuit for counting the number of sectors stored in a segment of the buffer memory.

The data transfer control unit 405 is a circuit for controlling data transfer with the buffer memory.

The buffer address generator 406 is a circuit for generating an address to be output to the buffer memory.

The buffer control unit 407 is a circuit for generating a command to be output to the buffer memory.

The buffer address generator of FIG.
The address of the buffer memory is managed as shown in FIG. The function of each part in FIG. 5 is described below.

Host Segment Start Address 500 is HB
Indicates the start address of the segment used for data transfer between the I-BM.

The Host Segment Pointer Address 501 is H
In a segment used for data transfer between BI and BM, a pointer address for next data transfer is shown.

Host Segment End Address 502 is HBI
-Indicates the end address of the segment used for data transfer between BMs.

Disk Segment Start Address 503 is DF
-Indicates the start address of the segment used for data transfer between BMs.

Disk Segment Pointer Address 504 is D
In a segment used for data transfer between F-BM, a pointer address for next data transfer is shown.

Disk Segment End Address 505 is DF-
Indicates the end address of the segment used in data transfer between BMs.

The buffer memory 506 is an area for temporarily storing data to be transferred from the host to the disk medium or from the disk medium to the host. The buffer memory is used by being divided into a plurality of segments.

The operation when the host 300 of FIG. 3 writes data to the disk storage device will be described. The data sent at the time of the write command from the host 300 is HD
The data is temporarily written to the buffer memory 302 under the control of C301. The write address to the buffer memory 302 is Ho
st Transfer Pointer Address is indicated by the Host Transfer Start Ad
Move within the range of dress, Host TransferEnd Address.

When the Host Transfer Pointer Address moves by one sector, the Buffer Sector Counter is incremented by one sector. That is, the Buffer Sector Counter manages the number of sectors in the buffer memory. Buffer S
When the ector counter indicates 1 or more, the buffer memory 302
Read out the data written in. Buffer memory 3
02 read address is Disk Transfer Pointer Addr
This pointer is indicated by ess, and each time data transfer is performed, Disk Transfer Start Address, Disk Transfer End
Move within the range of Address.

When the Disk Transfer Pointer Address moves by one sector, the Buffer Sector Counter is decremented by one sector. The data read from the buffer memory 302 is written via the R / W channel 303 and the head 304. The disk medium 305 forms a large number of concentric tracks, and each track is divided into a plurality of sectors. In the disk storage device, data access is performed in sector units.

The operation when the host 300 reads data from the disk storage device will be described. Host 30
At the time of a read command of 0, data on the disk medium 305 is written to the buffer memory 302 via the head 304 and the R / W channel 303. The write address to the buffer memory 302 is indicated by the Disk Transfer Pointer Address, and this pointer is changed every time data is transferred.
sk Transfer Start Address, Disk Transfer End Addre
Move in the range of ss. Disk Transfer PointerAddress
When moved by one sector, the Buffer Sector Counter is incremented by one sector.

When the Buffer Sector Counter indicates 1 or more,
The data written in the buffer memory 302 is read again. The read address of the buffer memory 302 is Host T
The pointer is indicated by the ransfer Pointer Address, and this pointer is transferred every time data transfer is performed.
s, move within the range of Host Transfer End Address.

When the Host Transfer Pointer Address moves by one sector, the Buffer Sector Counter is decremented by one sector.

The data read from the buffer memory is transferred to the host 300.

The above is the basic operation when the host receives write and read commands. However, particularly in the case of a read command from the host, it is difficult to realize a high-speed disk storage device if the disk medium is accessed as described above every time the read command is received.

Therefore, a read cache function is well known as a technique for speeding up access to a disk storage device. The read cache function is a function that, when storing data read from a disk medium in response to a first read request from a host into a buffer memory, prefetches data on a storage medium whose addresses are consecutively larger than the number of data requested by the host and stores the data in a buffer memory. This is the process of storing the information. Only the number of data requested by the host is read from the buffer memory and transferred. Then, when a read request is received from the host next, if the requested data is stored in the buffer memory by being pre-read by the previous command, the read operation from the disk medium is not executed, and the host system does not execute the read operation. Execute the transfer process. With such a read cache function, frequently read data is directly transferred from the buffer memory to the host without performing a read operation on the disk medium.

Japanese Patent Application Laid-Open No. 10-171713 discloses that these processes can be executed by dedicated hardware without involving the MPU of the disk storage device.

[0039]

With the recent increase in the capacity of a disk storage device, a larger capacity buffer memory has been used. Generally, the probability of a read command from the host hitting the cache data is increased by managing the space of the buffer memory in a divided space called a segment and having a plurality of cache data. However, the conventional method described above cannot perform hardware management in such a case. Therefore, an object of the present invention is to make it possible to realize read cache control using a space of a buffer memory divided and managed by a segment by dedicated hardware, so that read cache processing can be performed as compared with the case where an MPU is involved. And a means for reducing the processing time required for the cache data and increasing the probability of hitting the cache data.

[0040]

In order to solve the above-mentioned problems,
The present invention provides buffer memory means for storing data read from a disk medium at the time of read access from a host,
When storing data in the buffer memory from the recording medium, the cache means stores the data in the buffer memory more than the number of data requested by the host, and the cache data read by the cache means when read access is again made from the host. A cache hit determining means for determining whether or not the data requested by the host is included, and storing the data requested by the host when the cache hit determining means determines that the requested data of the host is included in the buffer memory. An address generating means for determining an address of said buffer memory means, and a data transfer means for transferring cache data of the address determined by said address determining means from said buffer memory means to a host. A storage device is provided.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 of an HDC equipped with a read cache system according to the present invention will be described below with reference to FIG.

The operation of each part in FIG. 1 is described below.

The HBI 100 (Host Bus Interface) is a circuit for transmitting and receiving commands, parameters, and data to and from the host.

The DF101 (Disk Formatter) is a circuit for controlling the reading and writing of data from and to a disk medium.

The BM 102 is a circuit for controlling the buffer memory.

The MPU I / F 103 is an interface circuit between the MPU and the HDC.

The read cache control unit 104 is a circuit for controlling the read cache. The host address latch unit 105 is a circuit that holds a logical address (LBA) when the host issues a read command.

The hit judging unit 106 is a circuit for judging whether the data requested by the host by the read command is stored in the cache data on the buffer memory.

The cache data table 107 is a table for holding information on cache data stored in the buffer memory.

The Buffer Sector Counter 108 is a circuit for counting the number of sectors stored in a segment of the buffer memory.

The data transfer control unit 109 is a circuit for controlling data transfer with the buffer memory.

The buffer address generator 110 is a circuit for generating an address to be output to the buffer memory.

The buffer controller 111 is a circuit for generating a command to be output to the buffer memory.

The buffer memory 112 is an area for temporarily storing data to be transferred from the host to the disk medium or from the disk medium to the host.

The cache data table 107 is configured as shown in FIG. The function of each part in FIG. 2 is described below.

LBA n200 is a logical address of cache data. This corresponds to the address sent when the host issues a command to the HDC.

The segment start address n201 is the start address of the buffer memory in which the cache data is stored.

Segment Sector Count n 202 is a segment
This is the number of sectors of cache data stored from Start Address n.

The operation when a read command is received from the host will be described with reference to FIG. The HDC has a read cache control unit 104, and a hit determination unit 106 determines whether the command hits the cache. To make the determination, the BM stores the data request address of the host received by the HBI in the host address latch unit 105. As shown in FIG. 2, the cache data table 104 used when making the determination is an LBA which is a logical address of the cache data indicated by the host, and a Segment Star which is a head address where the cache data is stored in the buffer.
t Address, Segment indicating the number of cache data sectors
Consists of elements with Sector Count as the basic unit,
This is a table having this for the number of segments. If the address of the data requested by the host is RSA and the number of read sectors is RN, LBA n ≤ RSA RSA + RN
<= LBA n + Segment Sector Count n If both conditions are satisfied, it is determined that a cache hit has occurred. or,
If the condition is not satisfied, the value of n is incremented sequentially,
The above determination is repeated for each element.

When a hit occurs in the cache, the address of the buffer memory storing the data to be transferred to the host is calculated from the Segment Start Address n of the element, and is set as the Host Transfer Pointer Address. In addition, the number of sectors requested by the host is set to Buffer Sector Counter1.
08 to transfer the cache data in the buffer memory to the host.

If all cache data tables 107 are searched and there is no cache hit, HDC
An interrupt is issued to U to notify the MPU that a read command has been issued. The MPU that has recognized that the read command has been issued sets the HDC so that the host transfers the number of data requested by the read command + cache data to the buffer memory. The HDC writes the number of data requested by the host by the read command + the number of cache data to the buffer memory via the disk medium, the head, and the R / W channel. At this time, the BM 102 is connected to the HBI 100
The received data request address of the host is stored in the host address latch unit 105. Of the data stored in the buffer memory, only the number of data requested by the host with the read command is transferred to the host, and the command is completed.
In conjunction with the data transfer to the host, the address stored in the host address latch unit 105 is also added. And the Host Transfer Pointer Addr at the time this command is completed
The values of the ess, Buffer Sector Counter, and host address latch unit 105 are respectively the cache data storage start address (Segment Start Ad
dress), the number of sectors of cache data (Segment Secto
r Count) and the logical address (LBA) of the cache data indicated by the host. Then, these are recorded in the element of the cache data table. The element to be overwritten when recording is selected for the element with the lowest priority. The priority may be set in the order of access frequency or stored time.

As a second embodiment, data stored in the buffer memory by a write command from the host may be recorded in the cache data table 107. Thus, in the case where the data written by the host by the write command is immediately read, high-speed processing can be performed.

As a third embodiment, a cache hit determination may be made as follows.・ LBA n ≤ RSA ・ R
SA + RN> = LBA n + Segment Sector Count n HD
C transfers data corresponding to a part of the data requested by the host by the read command from the buffer memory, and interrupts the MPU to transfer the remaining data. Upon receiving the interrupt, the MPU recognizes the host read command and instructs the HDC to transfer the cache data shortage plus the cache data. H received the instruction
The DC writes to the buffer memory via the disk medium, the head, and the R / W channel. Of the data stored in the buffer memory, only the cache data shortage is transferred to the host, and the command is completed. Then, when this command is completed, the Host Transfer Pointer Addres
s, Buffer SectorCounter, and the value of the host address latch unit 105 are cached as the cache data storage start address (Segment Start Address), the number of sectors of the cache data (Segment Sector Count), and the logical address (LBA) of the cache data indicated by the host, respectively. Record in data table. As in the first embodiment, the selection of the element to be overwritten when recording is performed on the element having the lowest priority.

As a fourth embodiment, the cache data table may be stored in the buffer memory instead of being provided in the read cache control unit 104 of the BM 102. As a result, even if the number of elements in the cache data table increases due to the increase in the number of divisions of the buffer memory into segments, the circuit size of the HDC does not increase.

As described above, it is possible to control the cache of the buffer memory managed by the segment. The probability of a cache hit is Bs / Ds when the capacity of the disk storage device is Ds, the capacity of the buffer memory is Bs, and when the buffer memory is segment-managed and not.
Becomes However, for example, when the host makes a random access such as repeating a request for data on an address having an address space equal to or larger than the capacity Bs of the buffer memory by a read command, the buffer memory becomes smaller than when segment management is not performed. When management is performed with N segments, the cache hit rate becomes N times as large.

The embodiments of the present invention described above explain the principle of the present invention and do not limit the technical scope of the present invention. As will be apparent to those skilled in the art, various modifications and changes can be made to the above-described embodiment.

[0067]

According to the present invention, when a disk storage device performs read cache processing of a read command sent by a host, the operation related to these is realized by dedicated hardware, thereby shortening the command processing time and reducing the read time. It is possible to improve the probability that the command hits the cache data.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an HDC.

FIG. 2 is a configuration diagram of a cache data table.

FIG. 3 is a block diagram of a disk storage device.

FIG. 4 is a block diagram of a conventional example of an HDC.

FIG. 5 is a block diagram of an address generation unit.

[Explanation of symbols]

100: HBI (Host Bus Interface), 101: DF
(Disk Formatter), 102 ... BM, 103 ... MPU
I / F, 104: read cache control unit, 105: host address latch unit, 106: hit determination unit, 107
… Cache data table, 108… Buffer Sector
Counter, 109: data transfer control unit, 110: buffer address generation unit, 111: buffer control unit, 112 ...
Buffer memory, 200 ... LBA n, 201 ... Segment Sta
rt Address n, 202... Segment Sector Count n.

Continued on the front page (72) Inventor Jin Ogawa 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside System Development Laboratory, Hitachi, Ltd. 5B005 JJ13 MM11 NN22 5B065 BA01 CC08 CE14 CH02 CH05

Claims (8)

[Claims] 1. A disk storage device control LSI H
In a DC (Hard Disk Controller), buffer memory means for storing data read from a disk medium at the time of read access from the host, and buffer memory for storing data from the recording medium to the buffer memory in an amount equal to or more than the number of data requested by the host. A cache hit determining means for determining whether or not cache data read by the cache means includes data requested by the host when there is read access from the host again; and Address generation means for determining the address of the buffer memory means in which the data requested by the host is stored when the cache hit determination means determines that the data requested by the host is included in the buffer memory; and The determined address A disk storage device having data transfer means for transferring flash data from the buffer memory means to the host. 2. A disk storage device according to claim 1, wherein said cache means has means for prefetching data continuously stored at an address on a recording medium of data requested by a host. 3. The buffer memory according to claim 1,
A disk storage device having means for dividing and managing a buffer memory space into a plurality of spaces called segments. 4. A disk storage device according to claim 1, further comprising a dedicated table means for determining a cache hit for each segment of the buffer memory means as the cache hit determination means. 5. The disk storage device according to claim 1, wherein the cache hit determination means determines that a cache hit has occurred when all data requested by the host is stored in the cache data. 6. The cache hit determining means according to claim 1, wherein when the data requested by the host is partially stored in the cache data, it is determined that the cache hit has occurred, and the remaining missing data is read from the disk medium. Disk storage device characterized by the following. 7. A disk storage device according to claim 4, wherein said table means is provided as dedicated hardware in the HDC. 8. A disk storage device according to claim 4, wherein said table means is provided in said buffer memory means.