JP2001135687A - Semiconductor integrated circuit device and method for testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely execute a signal transmission test between an output buffer and an input buffer on a wafer on a condition close to a transmission path condition between LSI after the assembly of the LSI, and mounting of the LSI on a mounted substrate. SOLUTION: A first outside pad 15 connected with an outside output terminal 106 of an output buffer 10-1 and a second outside pad 16 connected with an outside input terminal 107 of an input buffer 11-2 are connected through a transmission path 18 formed on a wafer with a prescribed resistance and capacitance on a condition close to a transmission path condition between LSI after the mounting of the LSI on a mounted substrate. The transmission path 18 is formed on a scribe line 19, and a testing circuit is disconnected at the time of separating a wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device formed on a wafer, and more particularly, to a semiconductor integrated circuit device including a high-speed buffer as a component, and a test method in a wafer state.

[0002]

2. Description of the Related Art In recent years, the speed of an internal circuit of a semiconductor integrated circuit device has been remarkably increased, and accordingly, a higher data transfer speed between the semiconductor integrated circuit devices has been demanded.

For example, CMOS, which has features of low power consumption and high integration, has become a mainstream of semiconductor integrated circuit devices in recent years.
In a semiconductor integrated circuit device, the input buffer has an almost infinite input impedance because the external input terminal is connected to the gate terminal of the MOS transistor, the signal is reflected at the signal receiving end, and the data transfer speed is increased. Was a hindrance.

In order to cope with the above problem, in the case of an integrated circuit device requiring high-speed operation, an external input terminal of an input buffer which is a signal receiving end is generally terminated by a terminating resistor.
A method is adopted in which the signal receiving end and the transmission line between the CMOS semiconductor integrated circuit devices are impedance-matched to suppress signal reflection.

As a method of performing a signal transmission test between an input buffer and an output buffer as described above, generally, after dicing a semiconductor integrated circuit device formed on a wafer and assembling it into a package, It is mounted on a predetermined mounting board, and a signal transmission test between semiconductor integrated circuit devices is performed.

However, in the above-described method, signal transmission between the input buffer and the output buffer cannot be confirmed until the semiconductor integrated circuit device is assembled and mounted. Therefore, a simple operation test at the wafer level is desired. Rarely, a loopback method has been proposed for this purpose.

Hereinafter, the loopback method will be described with reference to the drawings. Referring to FIG. 5, the test circuit of the semiconductor integrated circuit device is formed on the integrated circuit device in a wafer state. The test circuit includes a mode switching terminal 1 for inputting a control signal for switching between a normal operation mode and a test mode.
And one of the normal operation signal from the output terminal O3-1 of the internal circuit 7 and the test signal from the output terminal O1 of the test signal generation circuit 5 is selected by the control signal input to the mode switching terminal 1. A first input / output buffer 10 to be tested, a first external PAD 15 connected to an external input / output terminal IO6 of the first input / output buffer 10, A terminal resistor 14 connected between the external input / output terminal IO6 of the input / output buffer 10 to be measured and the terminal power supply terminal 4, and a reference voltage input terminal of the input buffer 10-2 of the first input / output buffer 10 to be measured. The test signal from the reference voltage terminal 3 connected to REF6 and the internal output terminal O6 of the first output buffer under test is supplied to the input terminal 2I3-2 or the signal of the internal circuit 7 by the control signal input to the mode switching terminal 1. Input terminal I5 of detection circuit 9 A multiplexer 8 for outputting the signal, a signal detection circuit 9 for dividing the test signal output from the output terminal O4-2 of the multiplexer 8 and outputting the divided signal to the output buffer 13, and a test output from the output terminal O5 of the signal detection circuit 9. Output buffer 13 for extracting a signal to the outside
And a test output PAD17.

At the time of the test, the control signal input to the mode switching terminal 1 is input to the control terminal CTL2 of the selector 6, so that the output terminal O3 of the internal circuit 7 input to the input terminal 1 (I2-1) of the selector 6 is input. -1 and the signal generating circuit 5 input to the input terminal 2 (I2-2) of the selector 6
The latter test signal is selected from the test signal from the output terminal O1 of the ring oscillator or the like, and the test signal is output from the output terminal O2 of the selector 6, and the first test signal to be measured is output.
Is input to the internal input terminal I6 of the measured input / output buffer 10.

At this time, the first measured input / output buffer 1
0 is set to the output buffer state by the control signal input to the control terminal CTL6. In this output buffer state, the first measured input / output buffer 10 outputs a signal input to its internal input terminal I6 to the first external pad 15 via the tri-state output buffer 10-1. The output is output to the internal output terminal O6 via the input buffer 10-2.

The test signal output from the output terminal O2 of the selector 6 by the operation of the first measured input / output buffer 10 is output from the internal output terminal O6 via the first measured input / output buffer 10. Is done. At this time, according to the control signal input to the control terminal CTL4 via the mode switching terminal 1, the multiplexer 8 converts the signal input to its own input terminal I4 into the latter of the output terminal 104-1 and the output terminal 204-2. Is set to transmit a signal. For this reason, the test signal output from the internal output terminal O6 of the first input / output buffer under test 10 is supplied to the signal detection circuit 9 via the multiplexer 8.
Is output to the input terminal I5.

The test signal input to the input terminal I5 of the signal detection circuit 9 is frequency-divided by the signal detection circuit 9, further amplified by the output buffer 13, and output to the test output pad 17. Therefore, by electrically connecting the test output pad 17 to a test device (not shown) such as an LSI tester and observing a test signal, the tri-state of the first input / output buffer 10 to be measured is measured. Output buffer 10
A signal transmission test between -1 and the input buffer 10-2 becomes possible at the wafer test stage.

[0012]

However, in the above-mentioned prior art, as a signal transmission test between the input and output buffers, the output buffer and the input buffer constituting the input and output buffers at the wafer test stage are used as described above. Although the signal transmission test between the two is performed, the external output terminal of this output buffer and the external input terminal of the input buffer are connected only by a very short wiring inside the input / output buffer. Actual operating conditions, that is, transmission line conditions between semiconductor integrated circuits on a mounting board mounted after assembling the semiconductor integrated circuit are significantly different. For this reason, there is a problem that the signal transmission test between the input and output buffers cannot be performed with high accuracy.

An object of the present invention is to enable a signal transmission test between an input buffer and an output buffer constituting a semiconductor circuit device to be performed with high accuracy at the stage of a wafer test so that a signal between an input buffer and an output buffer can be obtained. Of the semiconductor integrated circuit device caused by the signal transmission failure of the semiconductor integrated circuit device is accurately selected at the wafer test stage, and the cost of the semiconductor integrated circuit device having such a defect in the post-process (dicing, assembly, mounting) is reduced. It is in.

[0014]

To achieve the above object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on a semiconductor wafer, comprising: a first integrated circuit connected to an external output terminal of an output buffer; A pad and a second pad connected to an external input terminal of the input buffer, wherein the first pad and the second pad are formed by a transmission line formed on a semiconductor wafer and having a predetermined resistance and capacitance. It is characterized by being electrically connected.

In the semiconductor integrated circuit device of the present invention, a signal transmission test is performed between the external output terminal of the output buffer and the external input terminal of the input buffer at the stage of a wafer test.
By appropriately setting the circuit constants of the resistance and the capacitance forming the transmission line, the output is obtained under a condition close to the transmission line condition of a signal transmission test performed after the semiconductor integrated circuit device is assembled and mounted on a mounting substrate. A signal transmission test between the buffer and the input buffer can be performed. That is,
According to the semiconductor integrated circuit device of the present invention, the condition close to the signal transmission condition between the external output terminal of the output buffer forming one semiconductor integrated circuit and the external input terminal of the input buffer forming the other semiconductor integrated circuit Thus, the test can be performed in a wafer state, so that the accuracy of the signal transmission test by the wafer test is improved.

In a preferred embodiment of the present invention, a predetermined resistor is connected between the signal line of the transmission line and at least one of a terminal power supply terminal and a ground terminal. A wafer test can be performed under conditions closer to the mounting state.

It is also a preferable embodiment that the transmission line is formed on a scribe line. In this case, since the test circuit can be automatically removed when the semiconductor chip is separated from the wafer state, the number of steps for removing the test circuit can be reduced.

It is also a preferred embodiment of the present invention that each of the output buffer and the input buffer comprises an input / output buffer having a three-state buffer and a signal input buffer connected to the external output terminal. In this case, a desired input / output buffer can be selected.

A method for testing a semiconductor integrated circuit device according to the present invention is a method for testing the semiconductor integrated circuit device according to the present invention in a wafer state, wherein a predetermined test signal is input to an internal input terminal of the output buffer. The predetermined test signal is supplied to the input buffer via the first pad connected to the external output terminal of the output buffer, the transmission line, and the second pad connected to the external input terminal of the input buffer. A signal transmission test between the output buffer and the input buffer is performed by outputting the signal to an internal output terminal and observing the signal.

[0020]

Next, the configuration of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention in a wafer state. The test circuit includes a mode switching terminal 1 for inputting a control signal for switching between a normal operation mode and a test mode, and an output of a signal generation circuit 5 for generating a normal operation signal or a test signal from an output terminal O3-1 of the internal circuit 7. A selector 6 for selecting and outputting any one of the test signals from the terminal O1 according to the control signal input to the mode switching terminal 1, and a first input / output to be measured having an output buffer 10-1 to be tested Buffer 10 and a first input / output terminal 10 connected to external input / output terminal IO6 of first input / output buffer 10 to be measured.
External PAD 15 and the input buffer 11-
2, a second external pad 16 connected to the external input / output terminal IO7 of the second input / output buffer 11, and a first input / output buffer 10 A control terminal 2 for inputting a control signal for switching an input state and an output state of the first input / output buffer 10 to the control terminal CTL6; a control terminal 2 and a control terminal CTL7 of the second input / output buffer to be measured; Control terminal CTL7
An inverter 12 that outputs an inverted signal of the control signal input to the control terminal 2 to the external input / output terminal IO6 of the first input / output buffer 10 and the second input / output buffer 1
1, a terminating resistor 14 connected between the external input / output terminal IO7 and the terminating power supply terminal 4, a reference voltage input terminal REF6 of the input buffer 10-2 of the first measured input / output buffer 10, and a second measured A reference voltage terminal 3 connected to a reference voltage input terminal REF7 of an input buffer 11-2 included in the input / output buffer 11, a first external pad 15 and a second external pad 16
A signal output from the transmission line 18 formed on the scribe line 19 and the internal output terminal O7 of the second input / output buffer 11 to be measured is electrically connected with the control signal input to the mode switching terminal 1, A multiplexer 8 input to either the input terminal 2I3-2 of the internal circuit 7 or the input terminal I5 of the signal detection circuit 9, a signal detection circuit 9 for dividing the frequency of the signal output from the output terminal 204-2 of the multiplexer 8, It comprises an output buffer 13 for amplifying the output signal of the output terminal O5 of the signal detection circuit 9, and a test output PAD17 for taking out the signal from the output buffer 13 to the outside. Here, the resistance and the capacitance shown on the transmission line 18 schematically show the transmission line, and do not show that the resistance element and the capacitance element are connected as shown.

FIG. 2 is a sectional view of the microstrip line constituting the transmission line 18 shown in FIG. The microstrip line includes a conductor layer 20, a dielectric layer 21, and a conductor line 22. Specifically, the conductor layer 20 and the conductor line 22 can be realized by an aluminum (Al) wiring layer, and the dielectric layer 21 can be realized by a silicon oxide film. The general characteristic impedance Zo of the transmission line is 5
In the case of forming a 0Ω line, the relative permittivity Er of the dielectric layer 21, that is, the silicon oxide film is 4.3, the thickness h is 1 μm,
Further, the thickness t of the conductor line 22, that is, the Al wiring is set to 0.5 μm.
m, HA Wheeler ("Transmission-Line Prope
rties of a Strip on a Dielectric Sheeton a Plane, "
IEEE Trnas.Microwave Theory Tech., Vol.MTT-25, p
p.631-647, Aug.1977.)

## EQU1 ## a = (1 + 1 / Er) / 2, ΔW / t = 1 / π × (1 + ln (4 / √ ((t / h)
² + (1 / π (W / t + 1.1)) ² )) W '= W + aΔW, b = ((14 + 8 / Er) / 11) (4h / W') Zo = 42.4 / √ (Er +1) × ln (1+ (4h / W ′)) (b + √ (b ² + aπ ² ))). For example, it can be realized by setting the width W of the Al wiring to 1.75 μm.

FIG. 3 is an overall view of a semiconductor integrated circuit device in a wafer state assuming a bus connecting a plurality of memories and the like as the transmission line 18 shown in FIG. The semiconductor integrated circuit device includes an internal circuit 7 and a buffer region 26.
A first measured I / O buffer 10 and a second measured I / O buffer 11 formed in the buffer area 26,
The first external pad 15 connected to the first input / output buffer under test 10 and the second external pad 16 connected to the second input / output buffer under test 11, the microstrip line shown in FIG. The transmission line 18 formed by a plurality of MOS capacitors 23 connected to the microstrip line 25 and the ground terminal 24 and connected between the first external pad 15 and the second external pad 16 as an alternative to the package PIN capacitance of FIG. And a scribe line 19 on which a transmission line 18 is formed. However, some of the components shown in FIG. 1 are omitted in FIG.

As shown in FIG. 3, the transmission line 18 is formed by forming a microstrip line 25 around a scribe line to secure a desired wiring length, and the PIN capacitance of the memory package is replaced by the MOS capacitance 23. It is connected to a predetermined position on the microstrip line 25. The PIN capacity of the memory package is usually about 5pF, and the MOS capacity is usually 5e
Since it is about -3 pF / μm ² , the PIN capacity of the memory package can be realized with an area of about 1000 μm ² .

Next, the test operation of the integrated circuit device of the embodiment will be described in detail with reference to FIG.
First, a control signal is input to the mode switching terminal 1, and the operation mode is set to the test mode. Accordingly, the selector 6 performs the latter test of the normal operation signal output from the output terminal 103-1 of the internal circuit 7 and the test signal output from the output terminal O1 of the signal generation circuit 5 according to the control signal input to the control terminal CTL2. A signal is selected, and this test signal is input to the internal input terminal I6 of the first input / output buffer under test 10. Further, the multiplexer 8 converts the signal input from the internal output terminal O7 of the second input / output buffer under test to the input terminal I4 of the multiplexer 8 into the input terminal 2I3-2 of the internal circuit 7 according to the control signal input to the control terminal CTL4. To the output terminal O4-1 of the multiplexer 8 connected to the input terminal I5 of the signal detection circuit 9 and the output terminal O4-2 of the multiplexer 8 connected to the input terminal I5 of the signal detection circuit 9.

Further, another control signal is inputted to the control terminal 2, and the control terminals CTL6,
Then, the control signal is input to the control terminal CTL7 of the second input / output buffer under measurement 11 via the inverter 12. With this control signal, the first measured I / O buffer 10 is set to the output state, and the second measured I / O buffer 11 is set to the input state. First measured input / output buffer 10
In the output state of FIG.
-1 is set to the output state, and the signal input to the internal input terminal I6 is output to the external input / output terminal IO6 via the tristate output buffer 10-1. In the input state of the second input / output buffer 11 to be measured, the tri-state output buffer 11-1 is set to a high impedance state, and the signal input to the external input / output terminal IO7 is affected by the tri-state output buffer 11-1. The signal is input to the input buffer 11-2 without being received and output to the internal output terminal O7.

According to the above setting and operation, in the test mode, the test signal output from the output terminal O1 of the signal generation circuit 5 is supplied to the selector 6, the first input / output buffer 10 to be measured.
Buffer 10-1 and first external pad 1
5, the transmission line 18, the second external pad 16, and the second
Input buffer 1 constituting input / output buffer 11 to be measured
The signal is output to the output terminal 2O4-2 of the multiplexer 8 via 1-2, is input to the input terminal I5 of the signal detection circuit 9, is divided, and is output to the test output pad 17 via the output buffer 13. You.

Therefore, by observing the test signal output to the test output pad 17 with a test device such as an LSI tester, the circuit operation of the output buffer 10-1 of the first input / output buffer 10 to be measured, Signal transmission from the external pad to the second external pad via the transmission line 18;
Can be confirmed whether the circuit operation of the input buffer 11-2 of the input / output buffer 11 to be measured is normal.

In the above test, as shown in the configuration of the semiconductor integrated circuit device, when the semiconductor integrated circuit device is mounted on the mounting board, the transmission connected between the output buffer and the input buffer of the semiconductor integrated circuit device is performed. By forming the transmission line 18 so as to match the line conditions, a signal transmission test can be performed at a wafer test stage under conditions close to the signal transmission conditions between the two integrated circuit devices mounted on the mounting substrate.
As a result, it is possible to accurately select a defect due to a signal transmission defect between buffers. Specifically, for example, for the highest operating frequency, a ratio A between the highest operating frequency F1 measured by the test method of the present invention and the highest operating frequency F2 measured by mounting the semiconductor integrated circuit device on the mounting board is determined in advance. In addition, a method of determining the frequency selection value Fs in the wafer test from the obtained ratio A in accordance with the actual operating frequency Fr required on the mounting board can be considered.

Formulating the above,

A = F1 / F2, Fs = A × Fr In this way, a defect caused by a signal transmission defect between buffers can be accurately selected at the wafer test stage, and the post-process (dicing, assembly, mounting) of the defective semiconductor circuit device is not performed. ,
Overall manufacturing costs can be reduced.

In FIG. 1, since the transmission line 18 is formed on the scribe line, the first external pad 15 and the second external pad 16 are electrically disconnected after dicing. Therefore, if the normal operation mode is set by the mode switching terminal 1, the first measured input / output buffer 10 and the second
The input / output buffer 11 to be measured is an input buffer for transmitting an external signal to an internal circuit or an output signal from an internal circuit circuit, which is an original function of the buffer, according to a control signal input to the control terminal 2. Can be used as an output buffer.

Next, the configuration of a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a circuit diagram showing a semiconductor integrated circuit device according to the second embodiment of the present invention, similarly to FIG. The semiconductor integrated circuit device of the present embodiment is different from the semiconductor integrated circuit device of the previous embodiment.
It has a similar configuration except for the points described below.

In the integrated circuit device of FIG. 4, the first input / output buffer under test 10 and the second input / output buffer under test 11 are dedicated buffers for the signal transmission test. The characteristics of the buffers used in the actual circuit are as follows.
It is estimated from the characteristics of 0 and 11. Since the selector 6 and the multiplexer 8 which are the components of the test circuit of the embodiment shown in FIG. 1 are not required, they are excluded from the components.
Further, it is not necessary to switch the input state and the output state between the first input / output buffer under test 10 and the second input / output buffer under test 11, and the control terminal 2 of FIG. Connected to The transmission line 18 is formed in a region other than the scribe line. The output terminal 27 connected to the internal output terminal O6 of the input buffer 10-2 constituting the first measured input / output buffer 10 is open, and the tri-state output buffer 11- constituting the second measured input / output buffer. One internal input terminal I7 is connected to the ground terminal 24.

When the test circuit of FIG. 4 is compared with the test circuit of FIG. 1, the configuration of the test circuit is simplified because the selector 6 and the multiplexer 8 of FIG. The effect of the defect can be eliminated.

Further, since the transmission line 18 is formed in a region other than the scribe line, even after dicing and assembling, the tri-state output buffer 10-1 forming the first measured input / output buffer 10 and the A signal transmission test with the input buffer 11-2 constituting the output buffer under test 11 can be performed. The input buffer 10-2 constituting the first measured input / output buffer 10 does not function particularly, and the output terminal 27 connected to its output terminal O6 is open. The tri-state output buffer 11-1 constituting the second input / output buffer under test 11 also does not function particularly, and its input terminal I7 is connected to the ground terminal 24.

Although the present invention has been described based on the preferred embodiment, the semiconductor integrated circuit device and the test method of the present invention are not limited only to the configuration of the above-described embodiment. Various modifications and changes from the configuration of the embodiment are also included in the scope of the present invention.

[0036]

As described above, according to the present invention,
By connecting the external output terminal of the output buffer constituting the semiconductor integrated circuit device formed on the wafer and the external input terminal of the input buffer with a transmission line formed with a predetermined resistance and capacitance, the wafer test stage A signal transmission test can be performed under conditions close to signal transmission conditions between semiconductor integrated circuits after the semiconductor integrated circuit device is mounted on a mounting substrate. Thereby, a defect of the semiconductor integrated circuit device caused by a signal transmission defect between the input buffer and the output buffer is accurately selected at a wafer test stage, and a post-process (dicing, assembling) of the defective semiconductor integrated circuit device is performed. , Mounting), and a remarkable effect of reducing the manufacturing cost of the entire semiconductor integrated circuit device can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device and a test method thereof according to the present invention.

FIG. 2 is a sectional view of a microstrip line constituting the transmission line of FIG. 1;

FIG. 3 is an overall view of a semiconductor integrated circuit device assuming a bus connecting a plurality of memories and the like as the transmission line in FIG. 1;

FIG. 4 is a circuit configuration diagram showing a second embodiment of a semiconductor integrated circuit device and a test method thereof according to the present invention.

FIG. 5 is a circuit configuration diagram showing a conventional semiconductor integrated circuit device and a loopback method as a test method thereof.

[Explanation of symbols]

 1: Mode switching terminal 2: Control terminal 3: Reference voltage terminal 4: Termination power terminal 5: Signal generation circuit O1: Output terminal 6: Selector CTL2: Control terminal I2-1: Input terminal 1 I2-2: Input terminal 2 O2 : Output terminal 7: Internal circuit I3-1: Input terminal 1 I3-2: Input terminal 2 O3-1: Output terminal 1 O3-2: Output terminal 2 8: Multiplexer CTL4: Control terminal I4: Input terminal O4-1: Output terminal 1 O4-2: Output terminal 2 9: Signal detection circuit I5: Input terminal O5: Output terminal 10: First input / output buffer under test 10-1: Tristate output buffer 10-2: Input buffer CTL6: Control Terminal REF6: Reference voltage input terminal I6: Internal input terminal O6: Internal output terminal IO6: External input / output terminal 11: Second measured input / output buffer 11-1: Tristate output buffer 11-2: Input buffer CTL7: Control Terminal REF7: Reference voltage input terminal I7: Internal input Terminal O7: Internal output terminal IO7: External input / output terminal 12: Inverter 13: Output buffer 14: Terminating resistor 15: First external PAD 16: Second external PAD 17: Test output PAD 18: Transmission line 19: Scribe line Reference Signs List 20: conductor layer 21: dielectric layer 22: conductor line 23: MOS capacitor 24: ground terminal 25: microstrip line 26: buffer region 27: output terminal

Claims (5)

[Claims] 1. A semiconductor integrated circuit device formed on a semiconductor wafer, comprising: a first pad connected to an external output terminal of an output buffer; and a second pad connected to an external input terminal of an input buffer. A semiconductor integrated circuit device, wherein the first pad and the second pad are electrically connected by a transmission line formed on a semiconductor wafer and having a predetermined resistance and capacitance. 2. The semiconductor integrated circuit device according to claim 1, wherein a resistor is connected between the signal line of the transmission line and at least one of a terminal power supply terminal and a ground terminal. 3. The semiconductor integrated circuit device according to claim 1, wherein said transmission line is formed on a scribe line. 4. The input buffer according to claim 1, wherein each of said output buffer and said input buffer comprises an input / output buffer comprising a three-state buffer and a signal input buffer connected to said external output terminal. The semiconductor integrated circuit device according to any one of the above. 5. A method for testing a semiconductor integrated circuit device according to claim 1, wherein a predetermined test signal is input to an internal input terminal of said output buffer, and wherein said output buffer is Through the first pad connected to an external output terminal of the input buffer, the transmission line, and a second pad connected to an external input terminal of the input buffer. A signal transmission test between the output buffer and the input buffer by observing the signal and outputting the signal to the input buffer.