JP2001255858A - Liquid crystal display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize satisfactory color reproduction in a liquid crystal display of field sequential image display system by eliminating the effect of crosstalk due to residual voltages of pixels and also to perform the fining of a display pixel by making the area of an auxiliary capacitance small. SOLUTION: In this display system, a coefficient K1 is multiplied to the video signal of a current frame supplied from a field sequential signal converting circuit 208 in a first coefficient circuit 212 and also the video signal of the current frame supplied from the circuit 208 is delayed by one frame in a one frame delaying circuit 211 and a coefficient K2 is multiplied to the video signal of a previous frame which is delayed by one frame in a second coefficient circuit 213 and video signals outputted from these two coefficient circuits are added in a adding circuit 214 and this video signal is made to be used for the write-in to pixels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display system used for, for example, a head mounted display, a view finder or a projection type display.
More specifically, the present invention relates to a liquid crystal display system that displays a color image by a frame sequential method.

[0002]

2. Description of the Related Art First, a basic structure of a color liquid crystal display device of a frame sequential system which is a premise of the present invention is described in a liquid crystal display device previously proposed by the present applicant (Japanese Patent Application No. 11-247621).
Will be described as an example.

FIG. 9 is a block diagram showing a configuration of a liquid crystal display device of a frame sequential method. This liquid crystal display device 100
Has a plurality of display pixels PX, and a horizontal scanning circuit 101 and a vertical scanning circuit 102 for driving the display pixels PX.

In the liquid crystal display device 100, a plurality of column signal lines D1, D2,.
.. (hereinafter collectively referred to as D as appropriate) are arranged in parallel, and a plurality of row signal lines G are arranged in a direction orthogonal to this.
1, G2... (Hereinafter collectively referred to as G as appropriate) are arranged. A display pixel PX is formed at each intersection of each column signal line D and each row signal line G.

The horizontal scanning circuit 101 includes a horizontal shift register and a sampling switch (not shown), and includes a horizontal start signal Hst and a horizontal clock signal H.
, and outputs video signals to the column signal lines D1, D2,... at predetermined timing.

The vertical scanning circuit 102 is composed of a circuit including a vertical shift register, and has a vertical start signal Vs
t and the vertical signal Vck, the row signal line G
A scanning signal is output for every one horizontal scanning period to 1, G2,.

The display pixel PX includes a first switching transistor Tr1 (hereinafter abbreviated as Tr1), a second switching transistor Tr2 (hereinafter abbreviated as Tr2), an auxiliary capacitor Cs, a pixel electrode 103, and a common electrode 104.
And a liquid crystal member 105 held between these electrodes. Of these, the drain of Tr1 is the column signal line D
1, D2... And the gate is connected to the row signal line G
1, G2... Further, the gate of Tr2 is connected to the batch transfer pulse supply line 109. The common electrode 104 is formed on a counter substrate (not shown) which is arranged to face the silicon substrate (not shown).

The video signal, the horizontal start signal Hs
t, horizontal clock signal Hck, vertical start signal Vs
t, the vertical clock signal Vck, and the batch transfer pulse are supplied from a display pulse driving circuit (205) described later.

The liquid crystal display device 10 configured as described above
At 0, the horizontal scanning circuit 101 is driven by a horizontal start signal Hst and a horizontal clock signal Hck supplied from a display panel driving circuit (not shown), and outputs a video signal for one line (one row) to be output in one horizontal scanning period. Are simultaneously sampled on the column signal lines D1, D2,. On the other hand, the vertical scanning circuit 102 is driven by a vertical start signal Vst and a vertical clock signal Vck, which are also supplied from a display panel driving circuit (not shown).
A scanning signal is output for every one horizontal scanning period to 1, G2,. As a result, Tr1 connected to the row signal lines G1, G2,.
The video signals for one line sampled at 1, D2,... Are stored as charge information in the auxiliary capacitance Cs. After this operation is repeated for one frame, when a collective transfer pulse is supplied to the Tr2 from a display panel drive circuit (not shown), all the Tr2s are turned on, and the image for one frame is applied to the pixel electrodes 103 of all the display pixels PX. Signals are transferred collectively (batch transfer method). As a result, each display pixel PX
A video signal is applied to the liquid crystal member 105 corresponding to the pixel signal via the pixel electrode 103, the degree of light modulation of the liquid crystal changes in accordance with the voltage value of the video signal, and a gradation image corresponding to the information amount of the video signal is displayed. Is displayed.

FIG. 10 shows such a liquid crystal display device 100.
5 is a timing chart showing the operation timing of FIG. In the batch transfer method, scanning from the first line to the last line of a video signal for one frame is performed in a period t1,
When this is completed, a batch transfer pulse is given. However, since the response of the liquid crystal is delayed by the period t2 from the start of the scanning of the first line, the readout light from the light source is emitted so as to match this timing. The image displayed in the current frame is the image of the video signal written in the previous frame. In the example of FIG. 10, in a period tF, a G (green) image sampled one frame before is displayed as a current frame, and during this time, a B (blue) image of the next one frame is sampled. You.

The above batch transfer method has the following three advantages. First, high luminance and high light utilization can be achieved. That is, a normal active matrix type liquid crystal display device performs line-sequential scanning, in which scanning from the first line to the last line is completed, and the reading light of each color is irradiated in a state where the liquid crystal of the display pixels on the last line is completely corresponded. Otherwise, uniform color reproduction cannot be obtained. For this reason, there is a problem that the reading light cannot be irradiated during one frame scanning period, and the light utilization rate is reduced. On the other hand, in the batch transfer method, all display pixels are switched at the same time, so that the irradiation period of the readout light can be made longer than in the conventional active matrix method, and high luminance and high light utilization can be achieved. Second, the scanning rate can be reduced. That is, in the batch transfer method, the video signal for the next one frame is accumulated while the video signal for one frame is displayed, so that the entire one frame scanning period is used as the video signal writing period. This makes it possible to reduce the scanning rate as compared with a normal active matrix system. Third, a lower breakdown voltage can be realized. For example, as shown in the signal waveform diagram of FIG. 11, in the batch transfer method, all the display pixels are switched at the same time. Thus, an AC bias corresponding to the threshold voltage can be supplied to the common electrode as a rectangular pulse having a polarity opposite to that of the signal voltage. Therefore, it is possible to reduce the breakdown voltage of the substrate.

FIG. 12 is a block diagram showing the overall configuration of a color liquid crystal display system 200 including the liquid crystal display device 100. The optical system of the color liquid crystal display system 200 includes a liquid crystal display device 100, a PBS (polarizing beam splitter) 201, an LED 202, a diffusion plate 203, and a lens 204. The drive circuit system includes a display panel drive circuit 205, a timing generation circuit 206,
It comprises an LED drive circuit 207 and a frame sequential signal conversion circuit 208.

The frame-sequential signal conversion circuit 208 is a frame buffer circuit, and converts video signals input simultaneously as RGB from an external circuit (not shown) as parallel data into RGB time-series data. From the timing generation circuit 206, a control signal necessary for converting the parallel data into the time-series data by the frame sequential signal conversion circuit 208 is supplied.

The video signal converted by the frame-sequential signal conversion circuit 208 is subjected to necessary signal processing by a display panel drive circuit 205 and then supplied to the liquid crystal display device 100 together with various start signals and clock signals. You.

In the liquid crystal display device 100, the scanning of the video signal is performed by the operation described above, and the image is displayed in a frame-sequential manner. On the other hand, the LED driving circuit 207 controls the emission color (RGB) of the LED 202 at a timing synchronized with this operation.
Are sequentially switched. The timing of the scanning of the video signal and the light emission of the LED is controlled based on the timing signal supplied from the timing generation circuit 206 to each drive circuit.

The light emitted from the LED 202 serving as a light source at the above timing is uniformly diffused by the diffusion plate 203, and then guided to the liquid crystal display device 100 by the PBS 201.
This light is reflected on the lower substrate surface of the liquid crystal display device 100 and passes through the display pixels as readout light. And LED2
The color image colored with the emission color of 02 is PBS20
1. It is taken out through the lens 204.

[0017]

FIG. 13 shows a display pixel P
FIG. 10 is a detailed equivalent circuit diagram of X (FIG. 9). In the figure, Cp is a parasitic capacitance of a pixel portion due to a transistor structure and wiring, and CL is
Is the liquid crystal capacity per pixel. Vs indicates the signal voltage of the video signal, and Vp (n-1) indicates the pixel residual voltage of the previous frame accumulated on the pixel electrode 103 side. Other parts are denoted by the same reference numerals as in FIG.

In FIG. 13, when the signal voltage Vs is transferred to the pixel electrode 103, the signal voltage Vs is not transferred with the potential of the signal voltage Vs. This is because charge redistribution occurs between the signal voltage Vs and the pixel residual voltage Vp (n-1), and the potential of the signal voltage Vs becomes the pixel residual voltage Vp (n-1).
Is reduced by the amount of A voltage (hereinafter, referred to as an effective voltage) V actually supplied to the pixel electrode 103 by the transfer
p (n) is obtained by the following equation (1).

Vp (n) = K · Vs + (1−K) · Vp (n−1) (1) where K = Cs / (Cs + Cp + CL) The effective voltage Vp (n) and the signal voltage Vs Figure 1 shows the relationship
It is shown in FIG. As is clear from FIG. 14, the effective voltage Vp
Since (n) is affected by the pixel residual voltage Vp (n-1), an error voltage ΔVp is generated with respect to the original signal voltage Vs. This error voltage ΔVp can be neglected under the condition that the auxiliary capacitance Cs is extremely large with respect to the pixel parasitic capacitance Cp and the liquid crystal capacitance CL. However, in practice, there is a limit to the area for forming the auxiliary capacitance due to the layout area. It is difficult to set the auxiliary capacitance Cs under the above conditions.
In such a color display by the frame sequential method, since the pixel residual voltage Vp (n-1) of the previous frame is a signal of a color different from the signal voltage Vs of the current frame, the color of the previous frame interferes with the color of the current frame. In other words, there is a problem that the so-called crosstalk occurs and the color reproducibility is significantly deteriorated.

In addition, in order to minimize the influence of such crosstalk, conventionally, the auxiliary capacitance Cs is formed as large as possible. It was impossible to develop.

The present invention provides a liquid crystal display system which realizes good color reproducibility by eliminating the influence of crosstalk due to pixel residual voltage, and makes it possible to miniaturize display pixels by reducing the area of an auxiliary capacitor. The purpose is to do.

[0022]

According to a first aspect of the present invention, there is provided a liquid crystal display system comprising: a first substrate on which display pixels including at least a first and a second switching transistor, an auxiliary capacitor, and a pixel electrode are arranged in a matrix; A signal conversion circuit supplies a display panel having a second substrate including a common electrode opposed to the pixel electrode and a liquid crystal member sealed between the first and second substrates. Each video signal corresponding to RGB is written to the auxiliary capacitor via the first switching transistor in frame order, and then the written video signal is simultaneously sent to all display pixels via the second switching transistor. At the same time, a liquid crystal display system that performs color display by sequentially switching readout light corresponding to the frame and irradiating all the display pixels is used. A delay circuit for delaying the video signal of the current frame supplied from the signal conversion circuit by one frame period, a first coefficient circuit for multiplying the video signal of the current frame supplied from the signal conversion circuit by a coefficient K1. A second coefficient circuit for multiplying the video signal of the previous frame delayed by one frame period output from the delay circuit by a coefficient K2, and a video signal of the current frame output from the first and second coefficient circuits, An addition circuit for adding the video signal of the frame and outputting the added video signal, wherein the video signal output from the addition circuit is used for the writing.

According to a second aspect of the present invention, there is provided a liquid crystal display system comprising: a first substrate on which display pixels including at least a first and a second switching transistor, an auxiliary capacitor, and a pixel electrode are arranged in a matrix; A second substrate including a common electrode opposed to the first and second substrates;
Writing each video signal corresponding to RGB supplied from the signal conversion circuit to the auxiliary capacitor via the first switching transistor in frame order with respect to a display panel having a liquid crystal member sealed between the substrates. Subsequently, the written video signal is simultaneously transmitted to all display pixels via the second switching transistor, and readout light corresponding to the frame is sequentially switched to irradiate the display pixels to perform color display. In the liquid crystal display system, the R input to the signal conversion circuit is
Three sets of coefficient circuits for multiplying each of the GB video signals by a coefficient K1 and a coefficient K2, and two-color images having a relationship between a continuous previous frame and a current frame for the video signals output from the three sets of coefficient circuits. And three adding circuits for adding and outputting signals, wherein each of the video signals corresponding to RGB output from the three adding circuits is supplied to the signal conversion circuit.

Further, in the liquid crystal display system according to a third aspect, in the first and second aspects, the coefficient K1 of the first coefficient circuit and the coefficient K2 of the second coefficient circuit are set such that the storage capacitance value is Cs, the pixel is When the parasitic capacitance of the electrode is Cp and the liquid crystal capacitance per pixel is CL, K1 = 1 / KK2 = (1-K) / K where K = Cs / (Cs + Cp + CL) It is characterized by being substantially equal.

According to a fourth aspect of the present invention, in the liquid crystal display system according to the first or second aspect, the video signal written to the auxiliary capacitance is such that the signal polarity is inverted for each of RGB based on a voltage value supplied to the common electrode. Characterized in that the signal is an AC signal.

According to a fifth aspect of the present invention, in the liquid crystal display system according to the first or second aspect, the video signal written to the storage capacitor repeats a video signal of each color of RGB twice and continuously in units of frames or fields. It is an AC signal in which the signal polarity of the same video signal is inverted for each of RGB with reference to the voltage value supplied to the common electrode.

According to the first to fifth aspects of the present invention, the video signal component of the previous frame is added to the video signal subjected to the predetermined signal processing by the signal processing circuit by (1−K) / K. Therefore, when this video signal is pixel-displayed as the video signal of the current frame, the residual pixel voltage Vp (n−1) of the previous frame accumulated on the pixel electrode side is obtained by the added video signal component of the previous frame. ) Is canceled.

In particular, according to the fourth aspect of the present invention, no DC component is generated in the liquid crystal layer due to writing of a video signal, so that deterioration of the liquid crystal member can be prevented.

According to the fifth aspect of the present invention, since an ideally converted video signal of which the positive and negative signal voltages are almost the target is applied to the liquid crystal layer, the generation of a DC component in the liquid crystal layer is suppressed. As a result, the deterioration of the liquid crystal member can be more effectively prevented.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a liquid crystal display system according to the present invention is applied to a color liquid crystal display system having a color liquid crystal display device of a frame sequential type will be described below with reference to the drawings.

In the color liquid crystal display systems 300 and 400 of the first and second embodiments described below,
As a basic configuration thereof, a conventional color liquid crystal display system 200 as shown in FIG. 12 can be applied. However, the configurations of the optical system such as the liquid crystal display device 100 and the drive circuit system such as the display panel drive circuit 205 are the same. Here, the description thereof will be omitted, and the description will focus on a signal processing circuit, an AC conversion circuit, and the like, which are characteristic configurations of the present invention.

First Embodiment FIG. 2 is a block diagram showing the overall configuration of a color liquid crystal display system 300 according to the first embodiment. This first
In the embodiment, a signal processing circuit 210 that performs a correction process of a video signal is disposed between the display panel drive circuit 205 and the frame sequential signal conversion circuit 208. Although not shown, the signal processing circuit 210 and the display panel driving circuit 205
An AC conversion circuit, a D / A conversion circuit, and the like, which will be described later, are arranged between the two.

FIG. 1 is a block diagram showing the configuration of the signal processing circuit 210. The signal processing circuit 210 includes a one-frame delay circuit 211, a first coefficient circuit 212, a second coefficient circuit 213, and an addition circuit 214. The video signals corresponding to RGB are input to the signal processing circuit 210 from the frame sequential signal conversion circuit 208.

The one-frame delay circuit 211 is a circuit composed of a buffer memory, and outputs the input video signal of the current frame with a delay of one frame period (T). The video signal delayed by one frame period is supplied to a second coefficient circuit 213 described later as a video signal of the previous frame.

The first coefficient circuit 212 and the second coefficient circuit 213 multiply the video signal of the current frame and the video signal of the previous frame delayed by the one-frame delay circuit 211 by different coefficients and output the result. It is. The coefficient of each coefficient circuit is set to a value obtained by the following equations (2) and (3) or a value substantially equal thereto. Where K
1 indicates the coefficient of the first coefficient circuit 212, and K2 indicates the coefficient of the second coefficient circuit 213. Further, Cs indicates an auxiliary capacitance value, Cp indicates a parasitic capacitance value of a pixel electrode, and CL indicates a liquid crystal capacitance value per pixel.

K1 = 1 / K (2) K2 = (1−K) / K (3) where K = Cs / (Cs + Cp + CL) The first coefficient circuit 212 and the second coefficient circuit When 213 is formed of, for example, a resistance circuit, a coefficient for each circuit can be set by resistance division.

The adder circuit 214 includes a first coefficient circuit 212
And the video signal of the current frame output from the second coefficient circuit 213 and the video signal of the previous frame are added and output as a corrected video signal. For example, the corrected video signal Gc at the time of the video signal Gs (n) of the current frame is obtained by Expression (4), where the video signal of the delayed previous frame is Rs (n-1).

Gc = {(1 / K) · Gs (n)} + {(1−k) / K} · Rs (n−1) (4) Corrected image obtained in this manner Since the video signal component of the previous frame is added to the signal Gc by (1-K) / K, if the corrected video signal Gc is pixel-displayed as the video signal of the current frame, the added video of the previous frame is displayed. The signal component cancels the pixel residual voltage Vp (n-1) of the previous frame accumulated on the pixel electrode side. Here, the corrected video signal Gc shown in Expression (4) is set as a signal voltage Vs for transferring to the pixel electrode, and the pixel residual voltage Vp (n-1) in the previous frame and Rs (n-1) in Expression (4) are used. Is assumed to be equal, and the signal voltage Vs is substituted into the equation (1), the effective voltage Vp (n) supplied to the pixel electrode is as follows.

Vp (n) = K · Gc + (1−K) · Vp (n−1) = K · [{(1 / K) · Gs (n)} + {(1−K) / K} · Rs (n-1)] + {(1-K) .Vp (n-1)} {Gs (n) That is, by the video signal component (1-K) / K of the previous frame added to the current frame, Since the pixel residual voltage Vp (n-1) of the previous frame accumulated on the pixel electrode side is canceled, the effective voltage Vp (n) becomes substantially equal to the video signal Gs (n) of the current frame.

FIG. 3 is a signal waveform diagram showing a change in the potential of the effective voltage supplied to the pixel electrode. FIG. 3 (a) shows RGB.
FIG. 3B shows an example in which each of the video signals is supplied as a pair of positive and negative polarities, and FIG. 3B is a diagram in which each of the RGB video signals is supplied with the positive and negative polarities inverted for each frame. is there. In any case, the pixel voltage after correction Gc cancels the pixel residual voltage Vp (n-1) of the previous frame, and the effective voltage Vp (n) becomes almost equal to the video signal G of the current frame.
It has been confirmed that it is equal to s (n). The dashed line indicates the effective voltage Vp (n) when the video signal Gs (n) without correction is applied.

Thus, inverting the polarity of the video signal and supplying it to the pixel electrode is important from the viewpoint of preventing deterioration of the liquid crystal material. That is, when a DC component occurs in the liquid crystal layer,
Although ions are generated in the liquid crystal and cause deterioration of the liquid crystal material, the deterioration of the liquid crystal material can be prevented by applying a video signal as an AC signal.

Here, the configuration and operation of an AC conversion circuit for converting the corrected video signal output from the signal processing circuit 210 into AC will be described.

FIG. 4 is a block diagram showing the configuration of the AC conversion circuit. The AC conversion circuit 230 is connected between the signal processing circuit 210 and a display panel driving circuit 205 (not shown), and the signal processing circuit 210 supplies RGB time-series data as video signals. AC circuit 2
Reference numeral 30 denotes a non-inverting amplifier 231, an inverting amplifier 232, and a switch circuit 233.

Non-inverting amplifier 231 and inverting amplifier 232
Is a circuit for amplifying the input video signal with a predetermined gain and outputting the amplified video signal. Among them, the non-inverting amplifier 231
Output the inverted video signal with its polarity inverted.

The switch circuit 233 includes the non-inverting amplifier 23
1 and one of the two video signals input from the inverting amplifier 232 is selected and output.
The selection of the video signal to be input is performed by the timing generation circuit 206.
Is switched in accordance with the selection signal supplied from.

FIG. 5 is a signal waveform diagram showing the operation timing of AC conversion circuit 230. Hereinafter, the operation of the AC conversion circuit 230 when converting the video signal into AC will be described with reference to FIG.

First, RGB parallel data as shown in FIG. 5A is supplied to the frame sequential signal conversion circuit 208 from an external circuit (not shown) as a video signal. The frame-sequential signal conversion circuit 208 converts this into an RG signal as shown in FIG.
The signal is converted into B time series data and output to the signal processing circuit 210. The video signal converted to the time-series data is RG
It is output as data corresponding to the repetition period Ts of B.

The signal processing circuit 210 corrects the signal components described above, and outputs the corrected video signal to the AC conversion circuit 230. In the AC conversion circuit 230, the video signal that has passed through the non-inverting amplifier 231 is amplified with a predetermined gain, and is output as a positive polarity video signal as shown in FIG. On the other hand, the video signal that has passed through the inverting amplifier 232 is amplified with a predetermined gain, is inverted in polarity, and is output as a negative-polarity video signal as shown in FIG. The video signals amplified by these two amplifiers are both output to the switch circuit 233. The switch circuit 233 is connected to the timing generation circuit 208 as shown in FIG.
A selection signal as shown in (e) is supplied. In this selection signal, two signal values of H level (selection of positive polarity) and L level (selection of negative polarity) are repeated in a cycle corresponding to each data cycle of RGB.

In the switch circuit 233, one of the outputs of the non-inverting amplifier 231 and the inverting amplifier 232 is selected by the selection signal. As a result, the video signal input as the RGB time series data is converted into an AC video signal as shown in FIG. FIG. 5 (f)
, Each of the RGB video signals is output as a data string whose polarity is inverted in the data cycle.

Although not shown in FIG. 5F, the center value of the AC-converted video signal is the potential of the common electrode (reference voltage:
Vf). In the driving method according to this embodiment, the polarity of the signal voltage supplied to the liquid crystal is inverted by swinging the video signal having the amplitude of the signal voltage and the threshold voltage to both sides of the reference potential. In addition, as described above, while driving only the signal voltage as a video signal with its polarity inverted and supplying the same, the AC bias corresponding to the threshold voltage is applied to the common electrode with the polarity opposite to the signal voltage. It may be a method.

FIG. 5 shows an example in which the RGB repetition period Ts is the same as the frame period Tf. However, when the RGB repetition period Ts is gradually shortened, the luminance flicker and the color breakup phenomenon occur. Is reduced,
A good color image can be obtained. For example, Ts =
If it is set to 11.1 ms (90 Hz) or more, luminance flicker and color breakup phenomenon can hardly be recognized. Further, the frame period Tf shown in FIG. 5 may be a field period.

When the video signal supplied to the pixel electrode is converted into an AC signal and supplied to the pixel electrode by the AC conversion circuit 230 as shown in FIG. 4, no DC component is generated in the liquid crystal layer. Deterioration of the liquid crystal material due to generation of ions in the liquid crystal can be prevented. Also, by shortening the RGB repetition period Ts, a high-quality color image with less luminance flicker and color breakup can be obtained.

Next, another embodiment in which a video signal is converted into an alternating current will be described. However, since the basic configuration of the AC conversion circuit 230 is the same as that of the previous embodiment, only the differences will be described.

FIG. 6 is a signal waveform diagram showing the operation timing of AC conversion circuit 230 in another embodiment. Hereinafter, another embodiment for converting an image signal into an alternating current signal will be described with reference to FIG.

First, RGB parallel data as shown in FIG. 6A is supplied to the frame sequential signal conversion circuit 208 as an image signal from an external circuit (not shown). The frame-sequential signal conversion circuit 208 converts this into an RG signal as shown in FIG.
The signal is converted into B time series data and output to the signal processing circuit 210. At this time, the video signal of each color of RGB is repeated twice for each frame, and is converted into a time-series RRGBB video signal.

In the signal processing circuit 210, the above-described correction of the signal components is performed, and the corrected video signal is output to the AC conversion circuit 230. In the AC conversion circuit 230, the video signal that has passed through the non-inverting amplifier 231 is amplified with a predetermined gain, and is output as a positive-polarity video signal as shown in FIG. On the other hand, the video signal that has passed through the inverting amplifier 232 is amplified with a predetermined gain, is inverted in polarity, and is output as a negative-polarity video signal as shown in FIG. The video signals amplified by these two amplifiers are both output to the switch circuit 233. The switch circuit 233 includes the timing generation circuit 206 shown in FIG.
A selection signal as shown in (e) is supplied. In the selection signal, two signal values of H level (selection of positive polarity) and L level (selection of negative polarity) are repeated in a cycle corresponding to each data cycle of the RRGGBB video signal.

In the switch circuit 233, one of the outputs of the non-inverting amplifier 231 and the inverting amplifier 232 is selected by the selection signal. As a result, the video signal input as the RGB time series data is converted into an AC video signal as shown in FIG. FIG. 6 (f)
, Each of the RRGGBB video signals is output as a data string whose polarity is inverted in the data cycle for each same color. Also in this embodiment, the center value of the AC-converted video signal is biased to the same voltage as the potential of the common electrode (reference voltage: Vf).

Since the video signal in this embodiment has a set of positive and negative continuous signal waveforms of the same color signal, the signal voltage amplitude is positive and negative in the liquid crystal layer. A video signal will be applied. Therefore, a DC component does not occur as in the case where a video signal whose signal voltage amplitude is positive / negative asymmetric is supplied to the liquid crystal layer.
The deterioration of the liquid crystal material due to the generation of ions in the liquid crystal can be more effectively prevented.

Further, the occurrence of luminance flicker can be further reduced. FIG. 6 (g) shows the liquid crystal response when the AC signal shown in FIG. 6 (f) is applied, and particularly shows how the luminance changes in the R image.

In general, a slight difference in response occurs between the liquid crystal and the polarity of the applied signal voltage as shown in FIG. 6 (g). Therefore, when alternating current is performed at a low frequency, the difference in luminance is recognized as luminance flicker. In this case, the display quality deteriorates. However, in this embodiment, since the video signals of the same color are continuously positive and negative, the human eye recognizes the brightness of the average value of the positive and negative poles as shown by the broken line in FIG. Become. According to this, since colors of the same brightness are repeatedly recognized by human eyes, luminance flicker is hardly recognized even if the RGB repetition period Ts becomes slightly longer.

In this embodiment, the RGB repetition period Ts is the same as the frame period Tf.
As the GB repetition period Ts is gradually shortened, luminance flicker and color breakup phenomenon are reduced, and a good color image can be obtained. For example, Ts = 11.1 ms
(90 Hz) or more, luminance flicker and color breakup phenomenon can hardly be recognized.

When Ts is increased, for example, Ts =
In the case of 16.7 ms (60 Hz), luminance flicker is hardly recognized. The fact that Ts can be increased in this way can reduce the processing speed of the display panel driving circuit 205 and the like, so that low-speed circuit elements can be used and power consumption can be suppressed. Further, the frame period Tf shown in FIG.
May be the field period.

Also in the embodiment shown in FIG. 6, by converting the video signal supplied to the pixel electrode into an AC signal and supplying the AC signal to the pixel electrode, no DC component is generated in the liquid crystal layer. Deterioration of the liquid crystal material due to ion generation can be prevented.

Further, when the RGB repetition period Ts is shortened, luminance flicker and color breakup become almost unrecognizable, and even when Ts is slightly increased, luminance flicker is hardly recognized. Color images can be obtained.

In the first embodiment, the video signal itself converted to RGB time-series data by the frame sequential signal conversion circuit 208 is delayed, and the video signal component of the previous frame is converted to the video signal of the current frame by (1- 1). K) / K, so that even if the polarity inversion of the signal and the color frame switching method are different as shown in FIGS. Good color reproducibility can be obtained without the influence of talk.

In the first embodiment, the example in which the signal processing circuit 210 is disposed between the display panel driving circuit 205 and the frame sequential signal conversion circuit 208 has been described. 205 or the frame sequential signal conversion circuit 208.

Second Embodiment FIG. 7 is a block diagram showing the overall configuration of a color liquid crystal display system 400 according to a second embodiment. This second
In the embodiment, a signal processing circuit 220 for correcting a video signal is disposed at a stage preceding the frame sequential signal conversion circuit 208.

In the second embodiment, although not shown, the alternating current described with reference to FIGS. 4 and 5 (and FIG. 6) is provided between the frame sequential signal converting circuit 208 and the display panel driving circuit 205. And a D / A conversion circuit.

FIG. 8 is a block diagram showing the configuration of the signal processing circuit 220. This signal processing circuit 220 does not use the one-frame delay circuit 211 as in the first embodiment, but is composed of three sets of coefficient circuits and three addition circuits.

The three sets of coefficient circuits include a first coefficient circuit 221 for R, a second coefficient circuit 222, a first coefficient circuit 223 for G, a second coefficient circuit 224, and a coefficient circuit for B It comprises a first coefficient circuit 225 and a second coefficient circuit 226. These three sets of coefficient circuits are circuits that multiply each of the RGB video signals by a different coefficient and output the result. The coefficients multiplied by the first coefficient circuit and the second coefficient circuit are set to the values obtained by the equations (1) and (2) shown in the first embodiment or to values substantially equal thereto. . Note that the polarity inversion of signals and the color frame switching method in this embodiment are based on the premise that RGB video signals are supplied with their positive and negative polarities inverted for each frame as shown in FIG. 3B.

The first adder 227 and the second adder 2
28 and the third adding circuit 229 are connected to the first coefficient circuit 22.
Among the video signals of each color output from the first to second coefficient circuits 226, video signals of two colors having a relationship between a continuous previous frame and a current frame are added, and a corrected video signal Rc,
Output as Gc and Bc. That is, if the color frames are switched in the order of RGB, the first adder 2
At 27, the R video signal output from the first coefficient circuit 221 and the B video signal output from the second coefficient circuit 229 are added to output a corrected video signal Rc. The second addition circuit 228 includes a first coefficient circuit 223
Is added to the R video signal output from the second coefficient circuit 222 to output a corrected video signal Gc. Further, in the third adding circuit 229,
The B video signal output from the first coefficient circuit 225 and the G video signal output from the second coefficient circuit 224 are added to output a corrected video signal Bc. Where RGB
The relationship between the original video signal and the corrected video signals Rc, Gc, Bc is as follows.

Rc = (1−K) · R + {(1−K) / K} · B Gc = (1−K) · G + {(1−K) / K} · RBc = (1−K) B + {(1-K) / K} G where K = Cs / (Cs + Cp + CL) The corrected video signals Rc, Gc, and B thus obtained.
In c, the video signal component of the previous frame is (1-K) / K
, The corrected video signals Rc, G
When c and Bc are converted into RGB time-series data by the plane-sequential signal conversion circuit 208 and supplied to the liquid crystal display device 100 from the display panel driving circuit 205, the pixel signal side is added by the added video signal component of the previous frame. , The pixel residual voltage Vp (n−1) of the previous frame stored in the pixel is canceled. That is, similarly to the first embodiment, the video signal component of the previous frame added to the current frame (1-K) /
K cancels the pixel residual voltage Vp (n-1) of the previous frame accumulated on the pixel electrode side, so that the effective voltage Vp (n) becomes almost equal to the video signal Gs of the current frame.
(N).

In the second embodiment, FIG.
As shown in (b), it has been confirmed that the effective voltage Vp (n) is almost equal to the video signal Gs (n) of the current frame, and the influence of the crosstalk due to the pixel residual voltage Vp (n-1) is eliminated. And good color reproducibility can be obtained.

In particular, in the second embodiment, since the one-frame delay circuit 211 of the first embodiment becomes unnecessary, the same effect can be obtained with a simple circuit configuration that does not use a frame buffer or the like.

Also, in the second embodiment, as shown in FIG. 5 or FIG. 6, the video signal is converted into an AC signal and supplied to the pixel electrode, so that no DC component is generated in the liquid crystal layer. In addition, deterioration of the liquid crystal material due to generation of ions in the liquid crystal can be prevented.

In the second embodiment, an example is described in which the signal processing circuit 220 is arranged in a stage preceding the frame sequential signal conversion circuit 208. However, the signal processing circuit 220 is built in the frame sequential signal conversion circuit 208. Is also good.

[0077]

According to the present invention, the corrected video signal obtained by adding the video signal component of the previous frame to the video signal of the current frame is supplied to the display panel. The pixel residual voltage of the previous frame accumulated on the pixel electrode side is canceled by the video signal component of the frame. Therefore, good color reproducibility can be realized without the influence of crosstalk due to the pixel residual voltage.

Further, since it is not necessary to increase the auxiliary capacitance in order to reduce the influence of crosstalk, the area of the auxiliary capacitance can be reduced as compared with the related art. According to this, it is easy to miniaturize the display pixels, and it is possible to develop a higher resolution system.

In particular, according to the second aspect of the present invention, in the case where the above-described signal processing is performed on video signals input simultaneously with RGB in the preceding stage of the frame sequential signal conversion circuit, a frame buffer or the like is not used. A simple circuit configuration can be obtained.

In the invention of claim 4,
Since the corrected video signal is an AC signal in which the signal polarity is inverted for each of RGB, no ions are generated in the liquid crystal, and deterioration of the liquid crystal material can be prevented.

Further, in particular, in the invention of claim 5,
Since the video signal of each color of RGB is repeated twice consecutively, and the alternating video signal is obtained by inverting the polarity of the repeated same video signal for each of RGB, the amplitude of the signal voltage is positive and negative in the liquid crystal layer. Can be applied to the liquid crystal layer. According to this, since the generation of the DC component in the liquid crystal layer is further suppressed, the deterioration of the liquid crystal material due to the generation of ions in the liquid crystal can be more effectively prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing circuit according to a first embodiment.

FIG. 2 is a block diagram showing the overall configuration of the color liquid crystal display system according to the first embodiment.

FIGS. 3A and 3B are signal waveform diagrams showing a change in potential of an effective voltage supplied to a pixel electrode.

FIG. 4 is a block diagram illustrating a configuration of an AC conversion circuit.

FIG. 5 is a signal waveform diagram showing operation timing of the AC conversion circuit.

FIG. 6 is a signal waveform diagram illustrating operation timings of an AC conversion circuit according to another embodiment.

FIG. 7 is a block diagram showing an overall configuration of a color liquid crystal display system according to a second embodiment.

FIG. 8 is a block diagram showing a configuration of a signal processing circuit according to a second embodiment.

FIG. 9 is a block diagram illustrating a configuration of a liquid crystal display device using a frame sequential method.

10 is a timing chart showing operation timings of the liquid crystal display device shown in FIG.

FIG. 11 is a signal waveform diagram of a video signal in a batch transfer method.

FIG. 12 is a block diagram showing an overall configuration of a color liquid crystal display system including a liquid crystal display device of a frame sequential method.

13 is a detailed equivalent circuit diagram of the display pixel PX shown in FIG.

FIG. 14 is a signal waveform diagram showing a relationship between an effective voltage Vp (n) and a signal voltage Vs.

[Explanation of symbols]

100: liquid crystal display device, 101: horizontal scanning circuit, 102
... vertical scanning circuit, 103 ... pixel electrode, 104 ... common electrode, 105 ... liquid crystal member, 200, 300, 400 ... liquid crystal display system, 205 ... display panel drive circuit, 208 ...
Plane-sequential signal conversion circuit, 210, 220 ... signal processing circuit,
211 ... one frame delay circuit, 212 ... first coefficient circuit, 213 ... second coefficient circuit, 214 ... addition circuit, 22
1,223,225... First coefficient circuit, 222,22
4,226... Second coefficient circuit, 227, 228, 229
... Addition circuit, 230 ... AC circuit, 231 ... Non-inverting amplifier, 232 ... Inverting amplifier, 233 ... Switch circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642J 680 680A 3/34 3/34 J F term (Reference) 2H093 NA16 NA33 NA34 NA43 NC03 NC16 NC21 NC22 NC24 NC28 NC34 ND10 ND15 ND34 ND47 ND49 NG02 NG20 5C006 AA01 AA02 AA22 AC02 AC11 AC21 AC28 AF03 AF04 AF11 AF23 AF44 AF85 BB16 BC16 BF02 EA01 EC13 FA00 5C080 AA10 BB05 CC03 DD03 GG05 DD03 JJ06

Claims (5)

[Claims] A first substrate on which display pixels including at least a first and a second switching transistor, an auxiliary capacitor, and a pixel electrode are arranged in a matrix; and a first substrate including a common electrode opposed to the pixel electrode. For a display panel including a second substrate and a liquid crystal member sealed between the first and second substrates, each of the video signals corresponding to RGB supplied from the signal conversion circuit is arranged in the first order in the frame order. Writing to the auxiliary capacitance via a switching transistor, and then simultaneously sending the written video signal to all display pixels via the second switching transistor, and sequentially switching read light corresponding to the frame, In a liquid crystal display system that performs color display by irradiating all display pixels, a current signal supplied from the signal conversion circuit is provided. Circuit for delaying the video signal of the current frame by one frame period, a first coefficient circuit for multiplying the video signal of the current frame supplied from the signal conversion circuit by a coefficient K1, and one frame period output from the delay circuit A second coefficient circuit for multiplying the delayed video signal of the previous frame by a coefficient K2, and adding and outputting the video signal of the current frame and the video signal of the previous frame output from the first and second coefficient circuits. A liquid crystal display system comprising: an addition circuit, wherein a video signal output from the addition circuit is used for the writing. 2. A first substrate having at least a first and a second switching transistor, a storage capacitor, and a display pixel including a pixel electrode arranged in a matrix, and a first substrate having a common electrode opposed to the pixel electrode. For a display panel including a second substrate and a liquid crystal member sealed between the first and second substrates, each of the video signals corresponding to RGB supplied from the signal conversion circuit is framed in the first order. Writing to the auxiliary capacitance via a switching transistor, and then simultaneously sending the written video signal to all display pixels via the second switching transistor, and sequentially switching read light corresponding to the frame, In a liquid crystal display system that performs color display by irradiating all display pixels, the RGB signal input to the signal conversion circuit is And three sets of coefficient circuits for multiplying the coefficients K1 and coefficient K2 relative to the video signal, the video signal output from said three sets of coefficients circuit,
Three addition circuits for adding and outputting two color video signals having a relationship between a continuous previous frame and a current frame, and converting each of the video signals corresponding to RGB output from the three addition circuits into a signal. A liquid crystal display system, characterized in that it is supplied to a circuit. 3. The liquid crystal display system according to claim 1, wherein the coefficient K1 of the first coefficient circuit and the coefficient K2 of the second coefficient circuit are an auxiliary capacitance value of Cs, and a parasitic capacitance value of a pixel electrode. Where Cp and the liquid crystal capacitance value per pixel are CL, K1 = 1 / K K2 = (1−K) / K, where K = Cs / (Cs + Cp + CL). LCD display system. 4. The liquid crystal display system according to claim 1, wherein a video signal written to the storage capacitor is obtained by inverting a signal polarity for each of RGB based on a voltage value supplied to the common electrode. A liquid crystal display system characterized in that it is an alternating signal. 5. The liquid crystal display system according to claim 1, wherein the video signal written to the storage capacitor repeats the video signal of each of RGB two times in frame or field units, and repeats the same. A liquid crystal display system, wherein the signal polarity of the video signal is an AC signal in which the signal polarity is inverted for each of RGB with reference to a voltage value supplied to the common electrode.