JP2001256209A - Method and mechanism for fault tolerant consensus for asynchronous shared object system - Google Patents
Method and mechanism for fault tolerant consensus for asynchronous shared object systemInfo
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- JP2001256209A JP2001256209A JP2000068746A JP2000068746A JP2001256209A JP 2001256209 A JP2001256209 A JP 2001256209A JP 2000068746 A JP2000068746 A JP 2000068746A JP 2000068746 A JP2000068746 A JP 2000068746A JP 2001256209 A JP2001256209 A JP 2001256209A
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】共有オブジェクトを通じて情
報を伝達する複数の非同期プロセッサからなる共有オブ
ジェクトシステムにおいて、故障していないプロセッサ
の全てが故障により停止したプロセッサの影響を受ける
ことなく有限ステップ後に合意を得る手法、耐故障性を
もつ非同期共有オブジェクトシステムにおける合意問題
を解く手法、および、それらの実現機構。BACKGROUND OF THE INVENTION In a shared object system comprising a plurality of asynchronous processors transmitting information through a shared object, all non-failed processors obtain an agreement after a finite step without being affected by a stopped processor due to a failure. Methods, methods for solving consensus problems in fault-tolerant asynchronous shared object systems, and their implementation mechanisms.
【0002】[0002]
【従来の技術】複数のプロセッサからなる共有オブジェ
クトシステムにおいて、故障して停止しているプロセッ
サに関わらず、故障していないプロセッサの全てが1つ
の値に合意する非同期共有オブジェクトシステムにおけ
る耐故障合意問題は非同期システムにおける同期化およ
びプロセッサの故障検出に有効な応用をもつ。非同期共
有オブジェクトシステムは複数のプロセッサと有限個の
共有2値変数配列の集合である共有オブジェクトからな
る。プロセッサは共有2値変数配列を介して通信する。
各プロセッサは入力動作や出力動作を行い外部と対話す
るためのポートをもつ。Vをある値の集合とし、1からn
までの自然数でラベル付けされたn個のプロセッサと共
有2値変数の集合Xからなる共有オブジェクトシステム
を考える。各プロセッサへの外部入力をinit(v)とす
る。ここで、vは集合Vの要素である。また、各プロセッ
サはdecide(v) の形で外部に出力する。2. Description of the Related Art In a shared object system comprising a plurality of processors, a fault-tolerant agreement problem in an asynchronous shared object system in which all non-failed processors agree on one value regardless of a failed processor has stopped. It has an effective application in synchronization and processor fault detection in asynchronous systems. The asynchronous shared object system includes a shared object which is a set of a plurality of processors and a finite number of shared binary variable arrays. The processors communicate via a shared binary variable array.
Each processor has a port for performing input operation and output operation and interacting with the outside. Let V be a set of values, 1 to n
Consider a shared object system consisting of n processors labeled with natural numbers up to and a set X of shared binary variables. The external input to each processor is init (v). Here, v is an element of the set V. Each processor outputs to the outside in the form of decide (v).
【0003】各プロセッサは特別な入力 Stop をもつ可
能性がある。Stop信号は特定できない外部からの入力
で、プロセスのStop信号受信後は動作を停止する。共有
オブジェクトシステムが以下の3つの条件を満たすとき
合意に達する。 (1) 任意のプロセッサに対して、そのプロセッサのi
nitとdecideとの時間的系列は列init(v)、 decide(w)の
ある接頭辞である。つまり、何もないか、init(v) のみ
であるか、init(v)、 decide(w)の2つの動作の列であ
る。 (2) 全ての決定値は同じ値である。(Agreement条件)
(3) 決定値はあるプロセッサの入力値である。(Va
lidity条件)[0003] Each processor may have a special input Stop. The Stop signal is an external input that cannot be specified, and stops operation after receiving the Stop signal of the process. Agreement is reached when the shared object system meets the following three conditions: (1) For any processor, i of that processor
The temporal sequence of nit and decide is a prefix with columns init (v) and decide (w). That is, there is nothing, only init (v), or a sequence of two actions of init (v) and decide (w). (2) All the determined values are the same value. (Agreement condition)
(3) The determined value is an input value of a certain processor. (Va
lidity condition)
【0004】共有オブジェクトシステムで1からn-1ま
での任意の個数のプロセッサがStop信号を受信して停止
した場合でも、残りの停止していないプロセッサの全て
が合意するとき、システムが耐故障合意に達する。[0004] Even if an arbitrary number of processors from 1 to n-1 are stopped in the shared object system upon receiving the Stop signal, when all the remaining non-stopped processors agree, the system will pass a fault-tolerant agreement. Reach.
【0005】この耐故障合意を共有オブジェクトの各2
値変数配列を適用可能な操作でタイプ分けした場合、ど
のような手法が存在するかを示す。従来、共有オブジェ
クトの2値変数配列は1命令中に読み出しまたは書き込
みのみを許すread-write 2値変数配列と書き込みと読
み出しの両方を1命令中に実行可能な read-modify-writ
e 2値変数配列に大別される。非同期共有オブジェクト
システムでは、read-write 2値変数配列のみでは耐故
障合意が得られない。初期値unknownである共有2値変
数配列xを用いる合意手法の具体例を示す。[0005] This fault-tolerant agreement is assigned to each of the two shared objects.
It shows what methods exist when value variable arrays are typed by applicable operations. Conventionally, a binary variable array of a shared object allows only reading or writing in one instruction. Read-write A binary variable array and a read-modify-writ that can execute both writing and reading in one instruction
e It is roughly divided into a binary variable array. In an asynchronous shared object system, a fault-tolerant agreement cannot be obtained only with a read-write binary variable array. A specific example of an agreement method using a shared binary variable array x whose initial value is unknown will be described.
【0006】外部からの入力値をkとする。次に、read
(x)命令により共有2値変数配列xの値を戻り値vとして
受け取る。もし、値vが初期値unknownのままであれば、
write(x、k)命令により共有2値変数配列xにkの値を代
入しdecide(k)で値kに合意する。そうでなければ、deci
de(v)で値vに合意する。この場合共有オブジェクトの内
容を読み込んで、プロセッサがその内容に従って書き込
みを行う前に共有オブジェクトの内容が変化してしまう
ことで不合意を導いてしまう。It is assumed that an external input value is k. Next, read
(x) The value of the shared binary variable array x is received as the return value v by the instruction. If the value v remains unknown,
The value of k is assigned to the shared binary variable array x by the write (x, k) instruction, and agree with the value k by decide (k). Otherwise, deci
Agree on the value v in de (v). In this case, the content of the shared object is read, and the content of the shared object changes before the processor performs writing according to the content, which leads to disagreement.
【0007】そこで、読み出しと書き込みの両方を1命
令で行うread-modify-write により耐故障性をもつ合意
手法が考えられる。read-modify-write命令の1つである
compare-and-swap命令について説明する。共有2値変数
配列xと値v、 値kにおいてcompare-and-swap(x、v、k)
命令は共有2値変数配列xの値wがvと一致するなら共有
2値変数配列xに値kを書き込み値wを戻り値として返
す。そうでなければ何もせず、値wを戻り値として返
す。この手続きを1命令ステップ中に実行する。Therefore, a consensus method having fault tolerance by read-modify-write in which both reading and writing are performed by one instruction is considered. One of the read-modify-write instructions
The compare-and-swap instruction will be described. Compare-and-swap (x, v, k) for shared binary variable array x, value v, value k
The instruction writes a value k to the shared binary variable array x and returns a value w as a return value if the value w of the shared binary variable array x matches v. Otherwise, do nothing and return the value w as the return value. This procedure is executed during one instruction step.
【0008】compare-and-swap命令による耐故障合意を
得る手法の例を示す。初期値がunknownである共有2値
変数配列xにおいて、始めに外部からの入力値をkとす
る。次に、compare-and-swap(x、unknown、k)命令によ
り共有2値変数配列xの値wがunknownならxにkを書き込
み戻り値としてunknownを受け取る。そうでなければ、w
を戻り値として受け取る。compare-and-swap命令の戻り
値vがunknownなら、decide(k)により値kに合意する。そ
うでなければ、decide(v)により値vに合意する。An example of a method of obtaining a fault-tolerant agreement by a compare-and-swap instruction will be described. In a shared binary variable array x whose initial value is unknown, an external input value is initially set to k. Next, if the value w of the shared binary variable array x is unknown by the compare-and-swap (x, unknown, k) instruction, k is written to x and unknown is received as a return value. Otherwise, w
Is received as the return value. If the return value v of the compare-and-swap instruction is unknown, agree with the value k by decide (k). Otherwise, agree value v with decide (v).
【0009】共有2値変数配列内容の多重書き込みを許
さない単一書き込みのみ可能な2値配列変数xの場合、r
ead-modify-write命令を実行中、変数xはロックされ、
変数xに対する他の全ての命令が実行不能となる。In the case of a binary array variable x that allows only a single write without allowing multiple writes of the shared binary variable array contents, r
During execution of the ead-modify-write instruction, the variable x is locked,
All other instructions for variable x become unexecutable.
【0010】複数のプロセッサが同時に変数xに対するr
ead-modify-write命令を発行した場合、プロセッサ数の
長さをもつロックの連なりができてしまう。この状況を
競合と呼ぶ。また、1つの命令に対してできる可能性の
あるロックの連なりに属しているロックの最大個数、つ
まり、長さを競合のコストとする。A plurality of processors simultaneously execute r for a variable x.
When the ead-modify-write instruction is issued, a lock having a length equal to the number of processors is formed. This situation is called a conflict. In addition, the maximum number of locks belonging to a lock sequence that can be performed for one instruction, that is, the length is defined as the contention cost.
【0011】[0011]
【発明が解決しようとしている課題】上記従来手法のre
ad-modify-write 命令では競合コストはシステム内のプ
ロセッサ数に比例して大きくなる。理論的にはread-mod
ify-write 命令を用いる任意の耐故障合意手法の競合コ
ストがプロセッサ数に比例して大きくなることが示され
ている。この競合コストの削減を目的にread命令とwrit
e命令だけで合意が失敗する確率を保証する手法も存在
する。この場合、競合のコストはプロセス数に依存しな
いが、手法の実行ステップ数はプロセッサ数の二乗ない
し三乗に比例する。本発明は競合のコストがプロセッサ
数に依存しない耐故障性をもち、特にほとんど同期して
プロセッサが動作する場合に効率よく合意を得る手法と
その実現機構を提案する。Problems to be Solved by the Invention
With the ad-modify-write instruction, the contention cost increases in proportion to the number of processors in the system. Read-mod in theory
It has been shown that the competitive cost of any fault-tolerant agreement method using ify-write instructions increases in proportion to the number of processors. Read instruction and writ to reduce the contention cost
There is also a method that guarantees the probability that an agreement will fail only with e-commands. In this case, the cost of the competition does not depend on the number of processes, but the number of execution steps of the method is proportional to the square or the cube of the number of processors. The present invention proposes a method and a mechanism for obtaining a consensus efficiently when the contention cost has a fault tolerance independent of the number of processors, and particularly when the processors operate almost synchronously.
【0012】[0012]
【課題を解決するための手段】上記の目的を達成するた
め、本発明の共有オブジェクトシステムでは全てのプロ
セッサが同時に書き込み、読み出しができる多重読み出
し多重書き込み可能な共有2値変数配列xと各プロセッ
サごとにそのプロセッサのみが書き込みができ他の全て
のプロセッサが同時に読み出しができる単一書き込み多
重読み出し可能な2値変数配列を設定する。In order to achieve the above object, in the shared object system according to the present invention, a shared binary variable array x capable of simultaneous reading and writing by all processors and capable of simultaneous reading and writing is provided for each processor. , A single-write-multiple-read binary variable array is set which allows only that processor to write and all other processors to read simultaneously.
【0013】さらに、本発明の共有オブジェクトシステ
ムでは新たな命令read-and-write(x、y、k)を備えも
つ。read-and-write命令は共有2値変数配列xの読み込
みと共有2値変数配列yの書き込みを1ステップで行う
命令であり、命令開始から終了まで書き込む変数yがロ
ックされ、他のプロセッサが読み書きできない。しか
し、読み出しの対象である変数xは排他的制御を必要と
しない、つまり、多重読み出し、書き込みを許す。具体
的には変数xが1ならば変数yにkを書き込み1を返し、変
数xが1でなければ何もせずに0を返すという以下の手続
きを1命令ステップで実行する。Further, the shared object system of the present invention has a new instruction read-and-write (x, y, k). The read-and-write instruction is an instruction for reading the shared binary variable array x and writing the shared binary variable array y in one step. The variable y to be written from the start to the end of the instruction is locked, and other processors read and write. Can not. However, the variable x to be read does not require exclusive control, that is, multiple reading and writing are permitted. Specifically, when the variable x is 1, k is written to the variable y and 1 is returned. When the variable x is not 1, the following procedure of returning 0 without performing anything is executed in one instruction step.
【0014】[0014]
【発明の実施の形態】このとき、共有オブジェクトシス
テムは全ての多重書き込み多重読み出し可能な2値配列
xと単一書き込み、多重読み出し可能なレジスタをプロ
セッサnの2倍であるn×2個の2次元2値変数配列y[n]
[2]を備えもつ。各プロセッサiは配列yではi行目の要素
であるy[i][1]とy[i][2]のみを書き込むことが可能であ
る。初期設定x=1、 y[n][2]の全ての2n個の要素をNULL
として、各プロセッサiにおいて以下のプロトコルを実
行する。DESCRIPTION OF THE PREFERRED EMBODIMENTS At this time, the shared object system is a binary array capable of all multiple writing and multiple reading.
n × 2 two-dimensional binary variable arrays y [n], which is twice as many registers as processor n and single write and multiple read registers
It has [2]. Each processor i can write only elements i [i] [1] and y [i] [2] which are elements in the i-th row in the array y. Initial setting x = 1, all 2n elements of y [n] [2] are NULL
The following protocol is executed in each processor i.
【0015】始めに入力値をkとする。write(y[i][2]、
k)命令により共有2値変数配列y[i][2]に値kを書き込
む。次に、 read-and-write(x、y[i][1]、1)命令により
共有2値変数配列xの値が1ならば共有変数配列y[i][1]
に値1を書き込む、そうでなければなにもしない。次に
write(x、0)命令によって共有2値変数配列xに1を書き
込む。その後、局所変数jによりインデックス付けされ
たループ内においてread(y[j][1])命令による戻り値が
1となるインデックスjを見つけるまでjを1からnまで1
づつ増加する。ループを抜けた後、read(y[j][2])命令
を実行して共有2値変数配列y[j][2]の値をvとする。最
後にdecide(v)により値vに合意する。First, let the input value be k. write (y [i] [2],
k) Write the value k to the shared binary variable array y [i] [2] by the instruction. Next, if the value of the shared binary variable array x is 1 by the read-and-write (x, y [i] [1], 1) instruction, the shared variable array y [i] [1]
Write the value 1 to, otherwise do nothing. next
Write 1 to the shared binary variable array x by the write (x, 0) instruction. Then, j is changed from 1 to n until the index j whose return value by the read (y [j] [1]) instruction is 1 is found in the loop indexed by the local variable j.
Increase by one. After exiting the loop, the read (y [j] [2]) instruction is executed to set the value of the shared binary variable array y [j] [2] to v. Finally, agree on the value v by decide (v).
【0016】[0016]
【発明の効果】発明合意プロトコルではシステム中に故
障したプロセッサが存在しても、故障していないプロセ
ッサはプロトコルを終了することができる。発明合意プ
ロトコルにおいて発明機構を用いた場合、各プロセッサ
はwrite命令でy[i][2]を、read-and-write命令でy[i]
[1]のみをロックする。xに対するwrite命令は多重書き
込み読み出しが可能であるためロックを必要としない。
よって、各命令に対するロックの連なりの長さは高々1
であり、発明合意プロトコルの競合コストは1である。
つまり、競合コストはシステム中のプロセス数に依存し
ない。特にほとんど同期したシステム中ではどんなにプ
ロセス数が大きくともプロトコルの終了はほとんど同時
に小さいステップ数で終了する。According to the invention agreement protocol, even if there is a failed processor in the system, a non-failed processor can terminate the protocol. When the invention mechanism is used in the invention agreement protocol, each processor writes y [i] [2] with a write instruction and y [i] with a read-and-write instruction.
Lock only [1]. The write instruction for x does not require a lock because multiple writing and reading are possible.
Therefore, the lock length for each instruction is at most 1
And the contention cost of the invention agreement protocol is 1.
That is, the contention cost does not depend on the number of processes in the system. Especially in an almost synchronized system, no matter how many processes are performed, the end of the protocol is almost simultaneously completed in a small number of steps.
【図1】共有オブジェクトシステムの実施例を示す図で
ある。FIG. 1 is a diagram showing an embodiment of a shared object system.
【図2】共有2値変数配列の実施例を示す図である。FIG. 2 is a diagram showing an embodiment of a shared binary variable array.
Claims (4)
と2値変数配列群から成る、非同期共有オブジェクトシ
ステムで、2値変数配列群には、1つのプロセッサに対
して書き込み可能な領域が2つ備えられており、1つに
は入力値を書き込み、もう一方には真偽を問うことので
きる値“1”を書き込む、書き込みの実行される2つの
領域のそれぞれと、プロセッサのインデックス番号は1
対1の関係があり、かつすべての領域は互いに素であ
る、複数の非同期プロセッサが、受け取った入力値を共
有2値変数配列群へ書き込む手段と、共有2値変数配列
の真偽を読み出し、その結果によって共有2値変数配列
群の後者の領域へ値を単一ステップ時間で書き込む手段
と、共有2値変数配列の値の真偽を逆転するように書き
込む手段と、プロセッサのインデックス番号の最も小さ
いものから順に、共有2値変数配列群の後者の値を読み
出す手段と、読み出した入力値に決定する手段とを有す
ることを特徴とした合意解決手法。1. An asynchronous shared object system comprising a plurality of asynchronous processors, a binary variable array, and a binary variable array group, wherein the binary variable array group has two writable areas for one processor. It is provided with one for writing an input value and the other for writing a value "1" which can be asked for true or false.
A plurality of asynchronous processors having a one-to-one relationship and all regions being disjoint, means for writing a received input value to a shared binary variable array group, and reading true / false of the shared binary variable array; A means for writing a value to the latter area of the group of shared binary variable arrays in a single step time based on the result, a means for writing the value of the shared binary variable array so as to reverse the true / false, An agreement solution method characterized by comprising: means for reading the latter value of a shared binary variable array group in ascending order, and means for determining the read input value.
クトを通じて情報を伝達する共有オブジェクトシステム
において、2つの共有オブジェクトの2値変数配列xと
2値変数配列yと値kにおいて、共有2値変数配列xの読
み出しと共有2値変数配列yの書き込みを1命令ステッ
プで実行するread-and-write命令。2. In a shared object system in which a plurality of asynchronous processors transmit information through a shared object, a binary variable array x, a binary variable array y, and a value k of two shared objects are used for the shared binary variable array x. A read-and-write instruction that executes reading and writing of the shared binary variable array y in one instruction step.
有オブジェクトを通じて情報を伝達する共有オブジェク
トシステムにおいて、2つの共有オブジェクトの2値変
数配列xと2値変数配列yと値kにおいて、共有2値変数
配列xの読み出しと共有2値変数配列yの書き込み終了ま
で書き込まれる変数yがロックされ、他のプロセッサが
読み書きできない、しかし、readの対象である変数xは
排他的制御を必要としない、つまり、多重読み出し、書
き込みを許すという手続きを1命令ステップで実行する
read-and-write命令。3. The shared object system according to claim 2, wherein the plurality of asynchronous processors transmit information through the shared object, wherein the binary variable array x, the binary variable array y, and the value k of the two shared objects are shared binary. The variable y that is written until the reading of the variable array x and the writing of the shared binary variable array y are locked and cannot be read or written by other processors, but the variable x to be read does not require exclusive control, that is, , Multiple read and write procedures are executed in one instruction step
read-and-write instructions.
クトを通じて情報を伝達する共有オブジェクトシステム
での、請求項1の合意を得る手法において、上記の各プ
ロセッサが同時に書き込み、読み出しができる多重書き
込み多重読み出し可能な2値変数配列と上記の各プロセ
ッサごとにそのプロセッサのみが書き込みができ他の全
てのプロセッサが同時に読み出しができる単一書き込み
多重読み出し可能な2値変数配列が設定されており、請
求項3のread-and-write命令を上記の多重書き込み多重
読み出し可能な2値変数配列と上記の各プロセッサごと
にそのプロセッサのみが書き込みができ他の全てのプロ
セッサが同時に読み出しができる単一書き込み多重読み
出し可能な2値変数配列に対して適用して故障して停止
しているプロセッサに関わらず故障していないプロセッ
サの全てが有限ステップ後に合意を得る高速な耐故障合
意手法を実現する機構。4. A shared object system in which a plurality of asynchronous processors transmit information through a shared object, in the method for obtaining consensus of claim 1, wherein said processors can write and read at the same time. 4. A read / write binary variable array which is readable by only one processor and readable by all other processors at the same time for each processor. A binary variable array capable of performing the -and-write instruction in the above-described multiple-write multiple-read, and a single-write multiple-read capable in which only the processor can write to each processor and all other processors can simultaneously read each processor. It applies to the value variable array and Mechanism in which all of the processors that do not Razz failure to realize a high-speed fault-tolerant agreement technique to obtain the agreement after a finite step.
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| JP4923288B2 JP4923288B2 (en) | 2012-04-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003108540A (en) * | 2001-09-28 | 2003-04-11 | Noriyoshi Yoshida | Failure resistance agreeing technique and asynchronous common object system for guaranteeing its high speed operation |
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| JPH0512100A (en) * | 1991-07-05 | 1993-01-22 | Fujitsu Ltd | Cell management method and cell management table |
| JPH08329020A (en) * | 1995-05-30 | 1996-12-13 | Kofu Nippon Denki Kk | Parallel computer |
| JPH09138778A (en) * | 1995-09-29 | 1997-05-27 | Hewlett Packard Co <Hp> | Device and method using semaphore buffer for semaphore instruction |
| JPH11134307A (en) * | 1997-10-31 | 1999-05-21 | Toshiba Corp | Program development support apparatus and method, and recording medium recording program development support software |
| JPH11312148A (en) * | 1998-04-28 | 1999-11-09 | Hitachi Ltd | Barrier synchronization method and apparatus |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0512100A (en) * | 1991-07-05 | 1993-01-22 | Fujitsu Ltd | Cell management method and cell management table |
| JPH08329020A (en) * | 1995-05-30 | 1996-12-13 | Kofu Nippon Denki Kk | Parallel computer |
| JPH09138778A (en) * | 1995-09-29 | 1997-05-27 | Hewlett Packard Co <Hp> | Device and method using semaphore buffer for semaphore instruction |
| JPH11134307A (en) * | 1997-10-31 | 1999-05-21 | Toshiba Corp | Program development support apparatus and method, and recording medium recording program development support software |
| JPH11312148A (en) * | 1998-04-28 | 1999-11-09 | Hitachi Ltd | Barrier synchronization method and apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003108540A (en) * | 2001-09-28 | 2003-04-11 | Noriyoshi Yoshida | Failure resistance agreeing technique and asynchronous common object system for guaranteeing its high speed operation |
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| JP4923288B2 (en) | 2012-04-25 |
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