JP2001256782A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which amplification speed of a sense amplifier can be improved by reducing dependence on a data pattern of amplification speed. SOLUTION: This device is an SDRAM constituted of a memory array, a row decoder, a column decoder, a row address buffer, a column address buffer, an input/output buffer, a timing signal generating circuit, a voltage generating circuit, and the like, in a sense amplifier blocks including plural sense amplifiers of the memory array, a P side common source line CSP* (*: 1-n) and an N side common source line CSN* are divided for each sense amplifier SA*, and thereby, even when data is different among sense amplifiers SA*, a current from an adjacent sense amplifier SA* is reduced or stopped, and common source levels of each sense amplifier SA* are made levels corresponding to 'H' and 'L' data. Therefore, amplifying operation can be simultaneously performed in each sense amplifier SA*.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit technology for a semiconductor device, and more particularly to a technology effective when applied to a semiconductor device suitable for improving the amplification speed of a sense amplifier in a memory.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a memory such as a DRAM, a memory array including a plurality of word lines and a plurality of data lines and a plurality of sense amplifiers adjacent to the memory array are provided. A configuration is conceivable in which a common source line is commonly connected within the sense amplifier block, and between the sense amplifier blocks.

[0003] As a technique relating to such a memory, for example, on November 5, 1994, Baifukan Co., Ltd., "Advanced Electronics I-9 Ultra L"
SI memory "on page 161 to P167.

[0004]

By the way, the present inventor has studied a technique of a configuration in which a common source line is commonly connected in a sense amplifier block and the sense amplifier blocks are also connected as described above. As a result, the following became clear. For example, it is conceivable that a difference occurs in the amplification speed depending on the data pattern amplified by the sense amplifier, and the amplification speed is deteriorated.

That is, in the above-described configuration, for example, there is a problem that the amplification speed is deteriorated with respect to "L" data among many "H" data. This is because the current from the sense amplifier amplifying the “H” data flows into the sense driver near the sense amplifier that amplifies the “L” data, so that the sense amplifier attempting to amplify the “L” data cannot operate. That is the cause.

Accordingly, an object of the present invention is to focus on a difference in amplification speed due to a data pattern, and to provide a semiconductor device capable of improving the amplification speed of a sense amplifier by reducing the dependence of the amplification speed on the data pattern. Is what you do.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor device according to the present invention has a memory array including a plurality of word lines and a plurality of data lines, and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. In the block, the common source line of the sense amplifier is divided.

In this configuration, the common source line switch MOS transistor and the common source precharge switch M
An OS transistor is arranged, and a sense amplifier overdrive switch MOS transistor is arranged for each divided common source line.

Specifically, in the sense amplifier block, a first switch MOS transistor for setting the N-side common source line of the sense amplifier to a first voltage is provided for each one or two to eight sense amplifiers. And a second switch MOS transistor for supplying a second voltage to the P-side common source line of the sense amplifier is disposed for each of the sense amplifiers or one to two to eight. Is divided for each sense amplifier driver.

In this specific configuration, a third switch MOS transistor for connecting the N-side common source line and the P-side common source line to an equal third voltage is connected, and the third voltage is An average value of the first voltage and the second voltage, and the third switch MOS transistor is constituted by a switch for short-circuiting the N-side common source line and the P-side common source line; A switch MOS transistor for short-circuiting the common source line and the P-side common source line, and a switch MOS for applying a predetermined potential to the N-side common source line and the P-side common source line
It consists of a transistor.

Therefore, according to the semiconductor device, the dependence of the amplification speed on the data pattern is reduced, and the amplification speed can be improved. As a result, the row access time can be improved as a product. This is because, by dividing the common source line in units of sense drivers, the current from the adjacent sense amplifier is reduced or eliminated, and the sense amplifier common source level becomes “H”.
This is because the level matches the “L” data, the amplification operation is performed simultaneously, and the amplification speed is improved.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a functional block diagram showing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is an arrangement view showing a bank portion and a partially enlarged view of the semiconductor device of this embodiment. 3 is a circuit diagram showing a sense amplifier block, FIG. 4 is a circuit diagram showing a sense amplifier, FIG. 5 is an explanatory diagram showing power supply wiring of the sense amplifier, and FIG. 6 is a waveform diagram showing the operation of the sense amplifier block.

First, an example of the configuration of the semiconductor device of the present embodiment will be described with reference to FIG. The semiconductor device of the present embodiment is, for example, an SDRAM (Synchronous).
DRAM), a memory array MA, a row decoder X
-DEC, column decoder Y-DEC, row address buffer XAB, column address buffer YAB, input / output buffer I / OB, timing signal generation circuit TG, voltage generation circuit VG, etc.
One such as single crystal silicon by known integrated circuit technology
It is formed on individual semiconductor substrates.

Each circuit block of the SDRAM operates at the timing of an internal control signal formed by a timing signal generation circuit TG to which a control signal is input. The control signal input to the timing signal generation circuit TG includes a chip selection signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, etc. input at the timing of the clock signal CLK. There is. The combination of these control signals and address signals is called a command. The clock enable signal CKE determines whether the clock signal CLK is valid or invalid. The input / output mask signal DQM is a signal for controlling the input / output buffer I / OB to mask data input / output from the input / output terminals (DQ0 to DQn).

In the SDRAM, an address input terminal (A0
To An), an address multi-method in which a row address and a column address are input in a time-division manner. The row address input to the row address buffer XAB is decoded by the row decoder X-DEC, a specific word line in one memory array MA is selected, and the memory cells for one word are selected accordingly. Subsequently, when the column address is input to the column address buffer YAB,
A memory cell to be read or written is further selected by the column decoder Y-DEC. Note that SD
The RAM usually has a plurality of memory arrays (or memory banks) specified by bank addresses, but only one memory array MA (BANK0) is representatively shown in FIG.

The internal power supply system generated by voltage generation circuit VG shown in FIG. 1 employs a single power supply system in which VCC (for example, 2.5 V) is externally supplied with respect to VSS (0 V). ing. The internal power supply having the highest potential is VPP (for example, 3.0 V), is formed by a booster circuit including a charge pump circuit, and is supplied to a word line drive circuit and the like. VCL (for example, 2.5V = V
CC) is an operation power supply for peripheral circuits such as a row address buffer XAB, a column address buffer YAB, a row decoder X-DEC, a column decoder Y-DEC, and an input / output buffer I / OB. VDL (for example, 1.5 V) and VSS are potentials supplied to the sense amplifier. VD
L is formed by a step-down circuit (voltage limiter). In this embodiment, since the half precharge method is employed, VDL / 2 supplied to the data line or the like during standby is used.
(Eg 0.75V) is also formed from VDL. VD
L / 2 is also used as the plate potential of the memory cell. Finally, VBB (eg -0.75V) is
This is a substrate potential for biasing to the lowest potential of the back gate system of the S transistor, and is formed by a booster circuit including a charge pump.

Next, the inside of the memory array MA will be described in detail with reference to FIG. Memory array MA includes sub memory arrays SMA arranged in a matrix. Although not particularly limited, the memory array MA adopts a hierarchical word line system, and a main word driver MWD is arranged on one side of the memory array MA. Main word driver M
A main word line MWL connected to WD is provided in an upper metal wiring layer so as to extend over a plurality of sub memory arrays SMA (row direction: vertical direction in FIG. 2). The column direction is selected by a common Y provided so that a plurality of column selection lines YS output from the column decoder Y-DEC cross over a plurality of sub memory arrays SMA (column direction: left-right direction in FIG. 2). A decoder system is employed.

Each sub memory array SMA is shown in FIG.
As shown in the partially enlarged view of FIG. 3, the memory cell area MCA, the sense amplifier block SAB, the sub-word driver area S
It is divided into WD and cross area XA. For the memory cell area MCA, a sense amplifier block SAB is arranged adjacent to the memory cell area MCA in the column direction, and a sub word driver area SWD is arranged in the row direction.
A, and is arranged so as to surround the sense amplifier block S.
The area where AB crosses the sub-word driver area SWD is the cross area XA.

Next, the sense amplifier block SAB will be described in detail with reference to FIGS. Each sense amplifier block SAB is adjacent to the memory cell area MCA. In this memory cell area MCA, the data line pair D1
, Dnt, Dnb intersect a plurality of word lines WL in the memory cell area MCA, and a dynamic memory cell MC is connected to a predetermined intersection. This memory cell MC has one capacitor and one MOS transistor for accumulating data, here N
It is composed of MOS transistors. In this embodiment, the arrangement of the so-called two-intersection type data lines and the memory cells MC is taken as an example.

In the sub-word driver area SWD, a plurality of sub-word drivers provided for each of the plurality of word lines WL are provided. This sub-word driver is activated by the logical sum of the main word line MWL and the control signal of the FX driver. The FX driver is provided in the cross area XA, but is omitted in FIG. When the word shunt system is adopted instead of the hierarchical word line system, the sub-word driver region S
In the WD, a through-hole and a contact are provided in place of the sub-word driver to connect a backing word line formed of a metal such as aluminum provided in an upper layer and a common word line with a gate of a lower polysilicon layer. In this case, the sub-word driver area SWD is called a word shunt area.

The description now turns to the sense amplifier block SAB. A pair of data line pairs (eg, D1t, D1b)
Corresponding to the left and right shared switches SHR, precharge circuit PC, sense amplifier SA1, column switch I
OG and the like are provided. One memory cell area MC
The number of data line pairs of A is assumed to be 512 to 2048 pairs. Therefore, the number of sense amplifiers SA in the sense amplifier block SAB is 256 to 1024. This is because the number of sense amplifiers SA is half the number of data line pairs due to the alternate arrangement structure of the sense amplifiers SA.

The shared switch SHR is a changeover switch for sharing the sense amplifier SA1 with the left and right memory cell areas MCA. Here, the shared switch is an NMOS transistor, and its gate control signals SHRL and SHRR are set to the potential of the power supply VPP or VDL during the precharge period of the data line. For example,
When accessing the left memory cell area MCA, S
HRL = VPP, SHRR = VDL, only one side is NM
Conduction is performed without lowering the threshold voltage of the OS transistor. The precharge circuit PC supplies VDL / 2 to the data line pair by the control signal PCS during the data line precharge period. The column switch IOG is connected to the column decoder Y-
The data line pair selected by the DEC column selection signal YS is connected to the common input / output line pair IOt, IOb to form an input / output path for data with the outside.

The sense amplifier SA is a latch-type amplifier circuit in which two CMOS inverters are cross-coupled. That is, as shown in detail in FIG. 4, the sense amplifier SA includes a PMOS transistor pair having a source commonly connected and a gate and a drain cross-coupled to each other, and a NMOS transistor pair similarly coupled,
The sources of the transistor pair and the NMOS transistor pair are commonly connected to a P-side common source line CSP and an N-side common source line CSN, respectively.

Further, in the present embodiment, P-side common source line CSP and N-side common source line CSN
Is a CSP for each of the sense amplifiers SA1,.
, CSPn, CSN1,..., CSNn. That is, the P-side common source line CSP
The drain of the PMOS transistor QDP whose source is connected to the power supply VDL is connected to * (*: 1 to n). The gate of the PMOS transistor QDP is controlled by a control signal SP. Also, the N-side common source line C
The drain of the NMOS transistor QDN whose source is connected to the power supply VSSA (0 V) is connected to SN *. The gate of the NMOS transistor QDN is controlled by a control signal SN. Further, a short-circuit NMOS transistor QPC is connected between the P-side common source line CSP * and the N-side common source line CSN *.
MOS transistor QPC is gate-controlled by control signal PCS. Further, in addition to the shorting NMOS transistor QPC, a precharging MOS transistor for supplying a half level can be connected.

Next, the wiring for supplying the power supplies VDL and VSSA to the sense amplifier SA will be described with reference to FIG. Power supply V
DL and VSSA are supplied by a mesh-shaped power supply wiring having a low wiring impedance shown in FIG. The vertical wiring in this figure is formed on a second metal (such as aluminum) wiring layer M2. Memory cell area MC
In A, wirings for supplying the power supplies VDL and VSSA are provided in parallel with the main word lines MWL so as to sew between the main word lines MWL. It is assumed that one main word line MWL is provided for every four word lines, for example. Further, a wiring for supplying the power supplies VDL and VSSA also to the sense amplifier block SAB is a main word line MW.
L is provided in parallel.

On the other hand, the horizontal wiring is the second metal wiring layer M
It is formed on the third metal wiring layer M3 above the second metal wiring layer M3. A column selection line YS is provided so as to straddle the memory cell area MCA and the sense amplifier block SAB. For example, one column selection line YS is provided for every four pairs of data lines. Then, wirings for supplying the power supplies VDL and VSSA are provided in parallel with the column selection lines YS so as to sew between the column selection lines YS. The power supply lines of VDDA and VSSA of the second metal wiring layer M2 and the third metal wiring layer M3 are connected at a crossing point by a through-hole contact TH2 connecting M2 and M3. A power supply VDL coupled to the power supply wirings of the intersecting second metal wiring layer M2 and third metal wiring layer M3 through through holes TH2.
And the mesh-like power supply wiring of VSSA have low impedance.

Next, the operation of the present embodiment will be described with reference to FIG.
The operation of the sense amplifier block SAB will now be described. In the SDRAM, when a row active command is input, memory cells MC connected to a specific word line WL in a specific bank are read out to the sense amplifier SA and amplified at the same time. Thereafter, when a precharge command is input, the selection of the memory cell MC ends, and the memory cell MC is set to a precharge state, which is a waiting state for the next read.
The waveforms in the figure show the operations from the row active command to the input of the precharge command.

After the control signal PCS of the data line and the common source line falls and the precharge of the power supply VDL / 2 of the data line and the common source line is stopped, one of the plurality of word lines WL is selected, and The potential level changes from VSS to VPP. As a result, the power supply VPP is applied to the gate of the NMOS transistor of the selected memory cell MC to be activated, and the charge stored from the capacitor storing data is transferred to the data line D1t connected to the memory cell MC. ,..., Dnt. A small voltage difference is generated in the data line pair by the electric charge of the memory cell MC, and when the data of the memory cell MC is "H", D1t becomes a level higher by about 100 mv than D1b. Here, "H" is applied to the capacitor of the memory cell MC.
Is assumed, but the same applies except that the potential drops even when a low level “L” is stored.

At the start of sensing after the data in the memory cell MC has been completely read, the N-side common source drive control signal line SN is set to the level of VDL from the power supply VSS and set to NDL.
MOS transistor QDN is activated to drive N-side common source line CSN from power supply VDL / 2 to VSSA. At the same time or with the delay of the number of delay stages, the P-side common source drive control signal line SP is switched from the power supply VPP to VSS, thereby activating the PMOS transistor QDP and driving the P-side common source line CSP from the power supply VDL / 2 to VDL. Let it.

At this time, the memory cell M is connected to the data line pair.
The small voltage difference due to the electric charge of C is amplified, the high-level data line D1t is opened by the power supply VDL, and the low-level data line D1b is opened by the power supply VSSA, and the amplified signal is read out and output data. Becomes The amplification operation in this case is
Since the P-side common source lines CSP1, ..., CSPn and the N-side common source lines CSN1, ..., CSNn are divided for each of the sense amplifiers SA1, ..., SAn,
Even when the data differs among the sense amplifiers SA1,..., SAn, the level of the common source line is determined for each of the sense amplifiers SA, so that the amplification operation is performed simultaneously.

For example, when "L" data is output on data line D1t and "H" data is output on data line Dnt, sense amplifier SA for data line D1t is used.
1 and P-side and N-side common source lines CSP1, CSN1
Of the sense amplifier SAn with respect to the data line Dnt, and the levels of the P-side and N-side common source lines CSPn and CSNn of the sense amplifier SAn correspond to the "H" data. Since the current from the sense amplifier SAn amplifying the "data" does not flow into the sense driver of the sense amplifier SA1 amplifying the "L" data, the sense amplifier SA1
And the sense amplifier SAn can simultaneously perform an amplification operation.

The operation after the input of the precharge command is as follows. The selected word line WL changes from the power supply VPP to VSS. Thereafter, the N-side common source drive control signal line SN is changed from the power supply VDL to VSS,
Disconnect the side common source line CSN from the power supply VSSA.
Almost simultaneously, the P-side common source drive control signal line SP
From the power supply VSS to VPP, and the P-side common source line CS
Disconnect P from power supply VDL. N disconnected from power supply
, Dnt, Dn, the common source line CSN, the common source line CSP, and the pair of data lines D1t, D1b,.
b is the power supply VDL / 2 by the precharge control signal PCS.
Precharged.

Therefore, according to the present embodiment, the P-side and N-side common source lines CSP * (*: 1 to n), CSN
By dividing * into sense driver units, the current from the adjacent sense amplifier SA * is reduced or eliminated, and the common source level of each sense amplifier SA * becomes a level corresponding to the “H” and “L” data. Since the amplification operation is performed simultaneously by the sense amplifier SA *, the amplification speed is improved. Therefore, the data pattern dependence of the amplification speed is reduced, and the amplification speed can be improved.

(Embodiment 2) FIG. 7 is a circuit diagram showing a sense amplifier in a semiconductor device according to Embodiment 2 of the present invention. The semiconductor device of the present embodiment is an SDRAM as in the first embodiment, and includes a memory array MA, a row decoder X-DEC, a column decoder Y-DEC, a row address buffer XAB, and a column address buffer YA.
B, an input / output buffer I / OB, a timing signal generation circuit TG, a voltage generation circuit VG, and the like.
The point is that the circuit configuration is such that the S transistor is removed.

That is, in the present embodiment, FIG.
, The P-side common source line CSP and the N-side common source line CSN are connected to the sense amplifiers SA1,.
CSP1,..., CSPn, CSN1,.
, CSNn and P-side common source line C
SP * (*: 1 to n) and N-side common source line CSN
* Indicates the PMO whose source is connected to the power supply VDL
S-transistor QDP, NMO connected to power supply VSSA
The drain of the S transistor QDN is connected, and each PMO
The gates of the S transistor QDP and the NMOS transistor QDN have a circuit configuration controlled only by control signals SP and SN.

Therefore, according to the present embodiment, the P-side and N-side common source lines CSP * (*: 1 to n), CSN
* Is divided in units of sense drivers, and a short-circuit MOS transistor is removed, thereby forming an adjacent sense amplifier SA * as in the first embodiment.
Reduce or eliminate the current from each sense amplifier SA
The common source level of * becomes a level corresponding to the “H” and “L” data, the amplification operation is performed simultaneously by each sense amplifier SA *, the amplification speed can be improved, and the layout area of the sense amplifier SA * Can be reduced.

(Embodiment 3) FIG. 8 is a circuit diagram showing a sense amplifier in a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device of the present embodiment is an SDRAM as in the first and second embodiments, and includes a memory array MA,
A row decoder X-DEC, a column decoder Y-DEC,
It is composed of a row address buffer XAB, a column address buffer YAB, an input / output buffer I / OB, a timing signal generation circuit TG, a voltage generation circuit VG, and the like. In addition, the circuit configuration further includes an overdrive MOS transistor.

That is, in the present embodiment, FIG.
, The P-side common source line CSP and the N-side common source line CSN are connected to the sense amplifiers SA1,.
CSP1,..., CSPn, CSN1,.
, CSNn and P-side common source line C
SP * (*: 1 to n) and N-side common source line CSN
* Indicates the PMO whose source is connected to the power supply VDL
S transistor QDP2, NM connected to power supply VSSA
The drain of the OS transistor QDN is connected, and each PM
OS transistor QDP2, NMOS transistor QD
The gate of N is controlled by control signals SP2 and SN, and the P-side common source line CSP * and the N-side common source line C
NMOS transistor QPC for short circuit between SN *
And this NMOS transistor is connected to a control signal PC.
The gate is controlled by S.

Further, a PMOS transistor QDP for overdrive is connected to the P-side common source line CSP *.
1 is connected. PMO for this overdrive
The source of the S transistor QDP1 is connected to the power supply VDDA (for example, 2.5 V), the drain is connected to the P-side common source line CSP *, and the gate is controlled by the control signal SP1. Therefore, when the minute voltage difference due to the charge of the memory cell MC is amplified, the data line on the high level side is opened with the power supply VDDA higher than the power supply VDL, and the amplified signal is read out faster to output data. Becomes This power supply VDDA is also a mesh-shaped power supply wiring having a low impedance as in FIG.

Therefore, according to the present embodiment, the P-side and N-side common source lines CSP * (*: 1 to n), CSN
* Is divided for each sense driver and NMO for short circuit
PMOS for overdrive in addition to S transistor
By adopting a circuit configuration in which the transistor QDP1 is connected, similarly to the first embodiment, the current from the adjacent sense amplifier SA * is reduced or eliminated, and the common source level of each sense amplifier SA * is set to “H” or “H”. L "data, and the sense operation is performed simultaneously by each sense amplifier SA *, so that the amplification speed can be improved, the overdrive operation can be realized, and the amplification operation can be performed at high speed even at a low voltage. Can be.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, an example in which the common source line is divided for each sense amplifier has been described. However, the present invention is not limited to this.
It is also possible to divide the common source line for every four, eight or eight sense amplifiers.

In the above description, the invention made mainly by the present inventor is described in the technical field to which the SDRAM belongs.
Has been described, but the present invention is not limited to this. For example, an RDRAM (Rambus D)
RAM), SLDRAM (SyncLink DRA)
M) and the like, and can also be applied to a logic embedded memory and the like.

[0047]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Since the common source line of a sense amplifier is divided in a sense amplifier block including a plurality of sense amplifiers, the current from an adjacent sense amplifier is reduced or eliminated, and the common source line of each sense amplifier is reduced. Since the level becomes a level corresponding to the “H” and “L” data, the amplification operation can be performed simultaneously to improve the amplification speed.

(2) By arranging the common source shorting switch MOS transistor in divided common source line units, the P-side common source line of each sense amplifier and N
It is possible to make the side common source lines have the same voltage.

(3) By disposing the common source precharge switch MOS transistors in divided common source line units, it becomes possible to supply a half-level precharge voltage to the common source line of each sense amplifier.

(4) By arranging the sense amplifier overdrive switch MOS transistor for each divided common source line unit, the overdrive operation of each sense amplifier can be realized, so that high-speed amplification can be performed even at a low voltage. The operation can be performed.

(5) According to (1) to (4), the dependence of the amplification speed on the data pattern is reduced, and the amplification speed can be improved. As a result, the row access time of the memory can be improved. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A and 2B are a layout diagram and a partially enlarged view showing a bank portion in the semiconductor device according to the first embodiment of the present invention; FIGS.

FIG. 3 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a sense amplifier block.

FIG. 4 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a sense amplifier.

FIG. 5 shows a semiconductor device according to the first embodiment of the present invention.
FIG. 4 is an explanatory diagram illustrating power supply wiring of a sense amplifier.

FIG. 6 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a waveform chart showing an operation of the sense amplifier block.

FIG. 7 shows a semiconductor device according to a second embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a sense amplifier.

FIG. 8 shows a semiconductor device according to a third embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a sense amplifier.

[Explanation of symbols]

 MA memory array X-DEC row decoder Y-DEC column decoder XAB row address buffer YAB column address buffer I / OB input / output buffer TG timing signal generation circuit VG voltage generation circuit SMA sub memory array MWD main word driver MWL main word line YS column Selection line MCA Memory cell area SAB Sense amplifier block SWD Sub word driver area XA Cross area D1t, D1b,..., Dnt, Dnb Data line pair WL Word line MC Memory cell SHR Shared switch PC Precharge circuit SA1,. , CSPn P-side common source line CSN1,..., CSNn N-side common source line QDP, QDP1, Q P2 PMOS transistor QDN NMOS transistor QPC NMOS transistor

Continuation of the front page (72) Inventor Tomoki Sekiguchi 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5B024 AA15 BA07 BA09 CA07 CA21

Claims (5)

[Claims] 1. A semiconductor device comprising: a memory array including a plurality of word lines and a plurality of data lines; and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. Wherein the common source line of the sense amplifier is divided. 2. A semiconductor device, comprising: a memory array including a plurality of word lines and a plurality of data lines; and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. Wherein the common source line of the sense amplifier is divided, and a common source shorting switch MOS transistor is arranged for each of the divided common source lines. 3. A semiconductor device comprising: a memory array including a plurality of word lines and a plurality of data lines; and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. A common source line of the sense amplifier is divided, and a common source precharge switch MOS transistor is arranged for each of the divided common source lines. 4. A semiconductor device comprising: a memory array including a plurality of word lines and a plurality of data lines; and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. Then, the common source line of the sense amplifier is divided, and the sense amplifier overdrive switch MO is divided for each of the divided common source lines.
A semiconductor device, wherein an S transistor is provided. 5. A semiconductor device comprising: a memory array including a plurality of word lines and a plurality of data lines; and a sense amplifier block including a plurality of sense amplifiers adjacent to the memory array. And N of the sense amplifier
Switch M for setting the common source line on the first side to a first voltage
OS transistor is one of the sense amplifiers or 2 to 2
The second switches MO are arranged one by one for supplying a second voltage to the P-side common source line of the sense amplifier.
S transistor is one of the sense amplifiers or 2 to 8
Wherein the N-side and P-side common source lines are divided for each sense amplifier driver.