JP2001257338A - Solid-state imaging device - Google Patents

Abstract

[PROBLEMS] To provide a solid-state imaging device that solves an increase in reverse bias voltage for sweeping out charges accumulated in a photoelectric conversion unit to a semiconductor substrate while suppressing blooming between adjacent photoelectric conversion units. . SOLUTION: An n-type semiconductor substrate 24, a p-type well 27 provided at an intermediate portion in a depth direction from the surface thereof, and an accumulated charge according to incident light arranged in a matrix on the n-type semiconductor substrate 24 are provided. The generated photodiode 22 and an element isolation region 23 formed between the photodiode 22
In the solid-state imaging device provided with
In addition, a p-type first element isolation impurity diffusion layer 30 and a p-type second element isolation impurity diffusion layer 31 are provided immediately below and separated therefrom.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device having, for example, a vertical overflow drain structure.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. 8 is a cross-sectional view of a main part, FIG. 9 is an impurity concentration distribution diagram in the depth direction of each impurity diffusion layer along the A'-A 'cutting line in FIG. 8, and FIG. ′
FIG. 11 is an impurity concentration distribution diagram in the depth direction of each impurity layer along the section line B-B '. FIG. 11 shows each impurity diffusion along the section lines A'-A' and B'-B 'in FIG. FIG. 12 is a diagram showing a potential profile in a layer depth direction, FIG. 12 is an impurity concentration distribution diagram corresponding to FIG. 10 for explaining a conventional problem avoidance method, and FIG. 13 is a diagram illustrating a conventional problem avoidance method. FIG. 12 is a diagram showing a potential profile corresponding to FIG.

In FIGS. 8 to 13, reference numeral 1 denotes a photodiode 2 of a photoelectric conversion unit which generates electric charges in accordance with incident light, for example, arranged in a matrix (two-dimensional) with element isolation regions 3 provided therebetween. A thin p-type well 5 is provided in a deep portion of an n-type semiconductor substrate
An n-type impurity diffusion layer 6 is formed on the upper portion of
Photodiode 2 having p-type impurity diffusion layers 7 arranged in a matrix on the upper surface of n-type impurity diffusion layer 6 and forming a PN junction at a boundary between n-type impurity diffusion layer 6 and p-type impurity diffusion layer 7. Is provided.

Then, the p-type impurity diffusion layer 7 is fixed at the GND level, whereby the surface 8 having an unstable coupling is shielded and the generation of dark current is suppressed. Further, a reverse bias for inverting the p-type well 5 by being connected to the power supply is applied to the n-type semiconductor substrate 4 so that excessive charge exceeding the storage capacity of the photodiode 2 due to excessive incident light or the like is generated. The excess charge is swept out to the n-type semiconductor substrate 4 to form a vertical overflow drain structure.

On the other hand, the element isolation region 3 is located at a slightly deeper portion that does not extend from the surface 8 of the n-type semiconductor substrate 4 between the adjacent photodiodes 2 to the p-type well 5, and has a p-type first impurity of a predetermined impurity concentration. The element isolation impurity diffusion layer 9 is formed.

Further, an insulating layer 1 is formed on the n-type semiconductor substrate 4 on which the photodiode 2 and the element isolation region 3 are formed.
The transfer electrode wirings 11 and 12 are provided above the element isolation region 3 so as to interpose 0, and a light-shielding device in which a window 13 for taking incident light into the photodiode 2 portion on the insulating layer 10 is opened. A layer 14 is formed.

The impurity concentration distribution and the potential profile in the depth direction of each impurity diffusion layer in the photodiode 2 and the element isolation region 3 are as shown in FIGS. 9, 10 and 11, respectively. The portion where the diode 2 is formed is along the A'-A 'cutting line, and the concentration distribution is C
_a ′, the potential profile is shown by each curve of D _a ′, and the portion where the element isolation region 3 is formed is B′-B ′.
Along the cutting line, the concentration distribution is indicated by C _b ′, and the potential profile is indicated by D _b ′.

The impurity concentration in the portion where the photodiode 2 is formed is such that the peak portion 7a on the left side in FIG. 9 showing the concentration distribution C _a ′ is _a p-type impurity diffusion layer 7.
The peak portion 6a adjacent to this corresponds to the n-type impurity diffusion layer 6, and the right peak portion 5a corresponds to the p-type well 5. On the other hand, the impurity concentration in the portion where the element isolation region 3 is formed is such that the left peak portion 9b in FIG. 10 showing the concentration distribution C _b ′ is in the first element isolation impurity diffusion layer 9 and the right peak portion. 5a is a p-type well 5
It corresponds to.

In the depth profile X ₁ ′ from the surface 8 of the potential profile D _a ′ in the portion where the photodiode 2 is formed, the potential P ₁ ′ of the portion of the p-type well 5 corresponding to the overflow drain is n-type. It is formed by a reverse bias voltage applied to the semiconductor substrate 4. Since the p-type well 5 has such a potential P ₁ ′, when a charge exceeding the potential P ₁ ′ is generated in the photodiode 2, it can be discharged to the n-type semiconductor substrate 4 as excess charge. .

From this, the position in the depth direction of the depth X ₁ ′ at the potential P ₁ ′ becomes a boundary for storing charges. For this reason, the position in the depth direction where the p-type well 5 is provided becomes a photosensitive limit. For example, the surface of the n-type semiconductor substrate 4 is usually used to obtain long-wavelength sensitivity of incident light in order to approach human visibility. The p-type well 5 is formed at a depth of about 8 to 3 μm.

On the other hand, the first element isolation impurity diffusion layer 9 in the element isolation region 3 needs to be formed deep in the n-type semiconductor substrate 4 for element isolation. However, a region of the n-type semiconductor substrate 4 remains between the p-type well 5 and the first element isolation impurity diffusion layer 9 alone.

[0012] Therefore, if the impurity concentration of the first element isolation impurity diffusion layer 9 formed is thin, the surface 8 of the 'potential profile D _b along section _line' B'-B as shown in FIG. 11 At the depth X ₂ ′ of A′−
The depth X ₁ ′ of the potential profile D _a ′ along the A ′ cutting line, that is, the potential P ₂ ′ that is deeper than the potential P ₁ ′ in the p-type well 5 appears.

[0013] is' potential _{P 2} in the 'depth _{X 2,} depth _X 1'
In the case where excess charge is generated in the photodiode 2 because the potential is deeper than the potential P ₁ ′, the excess charge is discharged to the deep potential P before being discharged to the n-type semiconductor substrate 4. ₂ 'adjacent photodiode 2
And cause a blooming phenomenon. To prevent this problem, n-type a reverse bias voltage increased to be applied to the semiconductor substrate 4, _'a potential profile D _b' potential P ₁ at potential profile D _{a 'depth} X _1' depth X ₂ 'Must be deeper than the potential P ₂ ' at However, when the problem is avoided in this way, a new problem occurs in that the maximum accumulated charge amount of the photodiode 2 decreases.

In order to avoid the above problem, it is preferable to increase the impurity concentration of the first element isolation impurity diffusion layer 9. As a result, the concentration distribution of the impurity in the portion where the element isolation region is formed is like the concentration distribution C _b ″ of FIG. 12 corresponding to the concentration distribution C _b ′ along the cutting line B′-B ′ of FIG. And the potential profile is shown by B'- in FIG.
A potential profile D _b ″ of FIG. 13 corresponding to the potential profile D _b ′ along the cutting line B ′ is obtained. The potential profile D _a ′ of the portion where the photodiode is formed in FIG. This is the same as that of the portion where the photodiode 2 is formed along the A'-A 'cutting line, and the left peak portion 9b' in the concentration distribution _Cb "of FIG. This corresponds to the isolation impurity diffusion layer.

By doing so, the potential P ₂ ″ at the depth X ₂ ″ from the substrate surface of the potential profile D _b ″ becomes
The potential profile D _a ′ is shallower than the potential P ₁ ′ at the depth X ₁ ′ and the potential profile D _a ′ is deeper than the potential P ₁ ′, and the potential profile D _b ″ is the depth from the same substrate surface. is does not appear until X _{1 '.} Therefore, it is not necessary to increase the reverse bias voltage applied to the n-type semiconductor substrate 4 for suppressing blooming phenomenon, the maximum accumulated charge amount of the photodiode 2 is The problem of being reduced can be avoided.

However, in the above prior art,
As the impurity concentration of the first element isolation impurity diffusion layer 9 increases, the potential P ₁ ′ at the depth X ₁ ′ from the surface 8 becomes less likely to vary with respect to the reverse bias voltage applied to the n-type semiconductor substrate 4. . Accordingly, in order to increase the potential P ₁ ′ of the p-type well 5, a high reverse bias voltage must be applied to the n-type semiconductor substrate 4. As a result, the electronic shutter mode in which all the charges accumulated in the photodiode 2 are temporarily swept to the n-type semiconductor substrate 4 does not function.

As described above, in the conventional technique, the element isolation between the adjacent photodiodes 2 by the element isolation region 3 cannot be sufficiently performed. Therefore, when a large amount of electric charge is generated, excessive charge is accumulated in the n-type semiconductor substrate 4. If the charges are mixed into the adjacent photodiodes 2 before being swept out and blooming occurs, or if the reverse bias voltage applied to the n-type semiconductor substrate 4 is increased to suppress the blooming, the maximum accumulated charge of the photodiodes 2 is increased. The amount will be small. Further, when the impurity concentration of the first element isolation impurity diffusion layer 9 is increased in order to suppress the blooming phenomenon, all the electric charges accumulated in the photodiode 2 are swept out to the n-type semiconductor substrate 4, so that the charge is high. A reverse bias voltage must be applied, and the electronic shutter mode does not work.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to ensure reliable separation of adjacent photoelectric conversion units by element isolation regions, and An object of the present invention is to provide a solid-state imaging device capable of sweeping out all accumulated charges to a semiconductor substrate without increasing a reverse bias voltage.

[0019]

According to the present invention, there is provided a solid-state imaging device, comprising: a semiconductor substrate; a photoelectric conversion unit which is provided on the semiconductor substrate so as to have a predetermined arrangement and generates accumulated charges according to incident light; An element isolation region for isolating the photoelectric conversion unit,
In a solid-state imaging device having a first impurity diffusion layer for discharging excess charges generated in the photoelectric conversion unit to the outside, an element isolation region is provided below the second impurity diffusion layer and the second impurity diffusion layer. A third impurity diffusion layer, wherein the photoelectric conversion units are two-dimensionally arranged, and the third impurity diffusion layer is provided in a region immediately below the photoelectric conversion unit. And a third impurity diffusion layer formed substantially in a lattice at a predetermined depth from the surface in the semiconductor substrate. And a position where the maximum peak concentration in the impurity profile of the second impurity diffusion layer is substantially the same depth as a position where the maximum potential of the photoelectric conversion unit is indicated. And the third The impurity diffusion layer is provided at a position substantially in the middle in the depth direction between the second impurity diffusion layer and the first impurity diffusion layer, and the third impurity diffusion layer is further provided. The layer has the same pattern as the second impurity diffusion layer.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 1 is a cross-sectional view of a main part, FIG. 2 is an impurity concentration distribution diagram in the depth direction of each impurity diffusion layer along the cutting line AA in FIG. 1, and FIG. 3 is BB in FIG. FIG. 4 is an impurity concentration distribution diagram in the depth direction of each impurity diffusion layer along a cutting line, and FIG.
FIG. 5 is a diagram showing potential profiles in the depth direction of each impurity diffusion layer along the A-cut line and the BB cut line, and FIG.
FIG. 9 is a cross-sectional view for explaining a process of forming the first element isolation impurity diffusion layer and the second element isolation impurity diffusion layer,
6 is a plan view showing a pattern of a first element isolation impurity diffusion layer and a second element isolation impurity diffusion layer, and FIG. 7 is a plan view showing a first element isolation impurity diffusion layer and a second element isolation impurity diffusion in a modified embodiment. It is a top view which shows the pattern of a layer.

In FIG. 1 to FIG. 7, reference numeral 21 denotes a photodiode 22 of a photoelectric conversion unit which generates an electric charge according to incident light, which is arranged in a matrix (two-dimensional), for example, with an element isolation region 23 provided therebetween. A solid-state imaging device,
In order to obtain sensitivity to long wavelengths of incident light, for example, in order to obtain a deep portion of the mold semiconductor substrate 24, for example, a photosensitive limit closer to human visibility, a thin p-type well is formed at a depth of about 3 μm from the substrate surface 26. 27 and the n-type semiconductor substrate 2
4, an n-type impurity diffusion layer 28 and a p-type impurity diffusion layer 29 are arranged in a matrix on the upper surface of the n-type impurity diffusion layer 28, respectively. Is provided with a photodiode 22 having a PN junction formed at the boundary portion of.

In the element isolation region 23, an upper portion of the n-type semiconductor substrate 24 between the adjacent photodiodes 22 is formed.
A p-type first element isolation impurity diffusion layer 30 is provided. The p-type first element isolation impurity diffusion layer 3
The maximum concentration position of 0 does not extend from the substrate surface 26 to the p-type well 27 and is a predetermined depth X _3b substantially equal to the depth X ₄ of the position of the maximum potential P ₄ of the photodiode 22.
And are arranged at predetermined pitches in the vertical and horizontal directions, respectively, and are formed so as to form a predetermined pattern shown in FIG.

Further, the element isolation region 23 has an n-type semiconductor
The p-type well 27 in the substrate 24 and the first element isolation impurity
Intermediate portion between the layers 30 and, for example, a depth of approximately 1/2
Sa X _2bP-type second element isolation impurity having maximum concentration
The diffusion layer 31 is a p-type first element isolation impurity diffusion layer 30.
And is formed to have the same pattern as.

The position in the depth direction in the n-type semiconductor substrate 24 where the p-type second element isolation impurity diffusion layer 31 is provided depends on the dose of the impurity in the p-type second element isolation impurity diffusion layer 31. For example, the distance may be between the p-type well 27 and the p-type first element isolation impurity diffusion layer 30.

Then, the p-type impurity layer 29 is fixed at the GND level, whereby the substrate surface 26 with unstable coupling is shielded, and the generation of dark current is suppressed. Further, a reverse bias for inverting the p-type well 27 by being connected to the power supply is applied to the n-type semiconductor substrate 24, and an excessive charge exceeding the storage capacity of the photodiode 22 due to excessive incident light or the like is generated. Form a vertical overflow drain structure in which this excess charge is swept out to the n-type semiconductor substrate 24.

Further, on the n-type semiconductor substrate 24 on which the photodiode 22 and the element isolation region 23 are formed, transfer electrode wirings 33 and 34 are formed above the element isolation region 23 with an insulating layer 32 interposed therebetween. Is formed on the insulating layer 32, and a light-shielding layer 36 having an opening 35 for taking in incident light into the photodiode 22 is formed on the insulating layer 32.

In the above-described structure, the impurity concentration distribution and the potential profile in the depth direction of each impurity diffusion layer in the photodiode 22 and the element isolation region 23 are shown in FIG. 2, FIG. 3, and FIG. It is as shown,
The portion where the photodiode 22 is formed is along the AA cutting line, the concentration distribution is C _a , and the potential profile is D
_a , the portion where the element isolation region 23 is formed is along the BB cutting line, and the concentration distribution is C
_b, the potential profile is shown in the curves of the D _b.

Then, a photodiode 22 is formed.
The impurity concentration of the part _aFigure showing
2, the left peak 29a is a p-type impurity diffusion layer.
29, a peak portion 28a adjacent thereto is an n-type impurity.
In the diffusion layer 28, the peak 27a on the right side is the p-type well 2
7, which corresponds to FIG. On the other hand, the element isolation region 2
The impurity concentration in the portion where 3 is formed is determined by the concentration distribution C_bShows
The left peak 30b in FIG.
Of the first element isolation impurity diffusion layer 30 adjacent to
The peak portion 31b is a p-type second element isolation impurity diffusion layer
31, the right peak 27 a corresponds to the p-type well 27.
It has been adapted.

Further, among the potential profile _{D a} in the formation portion of the photodiode 22, the depth _{X 1} from the substrate surface 26, the potential _{P 1} part of p-type well 27 which corresponds to an overflow drain, n-type semiconductor substrate 24 is formed by a reverse bias voltage applied. On the other hand, in the element isolation region 23, the p-type second element isolation impurity diffusion layer 31 having a predetermined concentration is provided between the p-type first element isolation impurity diffusion layer 30 and the p-type well 27.
The depth X ₂ and X ₃ from the substrate surface 26 of the potential profile D _b along the B-B section line shown in FIG. 4, which from along the deep position of the A-A cutting line potential profile D _a depth X ₁ shallow potential _{P 2} and _{P 3} than the potential _{P 1} appears. As a result, if the charge exceeds the potential P ₁ in the photodiode 22 is generated it became excessive charge will be swept to the n-type semiconductor substrate 24 exceeds the potential P _1.

[0030] Then, since a configuration as described above, without reducing the maximum accumulated charge amount of the photodiode 22, before the excessive charges are swept to the n-type semiconductor substrate 24, than the depth X ₁ It is possible to suppress the blooming phenomenon that occurs when charges are mixed into the adjacent photodiode 22 from a shallow position. Furthermore, since there is no need to increase the impurity concentration of the first element isolation impurity diffusion layer 30 of p-type, high reverse bias voltage applied to the n-type semiconductor substrate 24 in order to deep potential P ₁ of the p-type well 27 You don't have to worry. Then, all the charges accumulated inside the photodiode 22 are temporarily stored in the n-type semiconductor substrate 24.
The electronic shutter mode that sweeps out to the right can also function normally.

As described above, the p-type well 27 in the element isolation region 23 and the n-type semiconductor substrate 24
In order to form the first element isolation impurity diffusion layer 30 of the p-type and the second element isolation impurity diffusion layer 31 of the p-type, a known photoetching technique and a high-acceleration ion implantation technique are used. That is, after the buffer oxide film 37 is formed on the upper surface of the n-type semiconductor substrate 24 on which the p-type well 27 is formed, a photoresist film 38 is deposited on the upper surface. Next, the deposited photoresist film 38 is etched by patterning using a photolithography method, and as shown in FIG.
A predetermined resist film pattern 40 having an implantation opening 39 is formed at a position where the first and second element isolation impurity diffusion layers 30 and 31 of the mold are formed.

Subsequently, implantation of boron (B) ions at a high acceleration voltage is performed through the implantation openings 39 of the resist film pattern 40 to the p-type second element isolation impurity diffusion layer 31 of the n-type semiconductor substrate 24. The process is performed to the formation position to a predetermined depth. In another step in which the ion implantation conditions are changed, boron ions are implanted to a predetermined depth at the formation position of the p-type first element isolation impurity diffusion layer 30 by using the same resist film pattern 40.

Then, after removing the resist film pattern 40, a heat treatment also serving as annealing is performed to diffuse the impurities, and the p-type first element isolation impurity diffusion layer 30 and the p-type Second element isolation impurity diffusion layer 3
Form one. Thereafter, through a well-known manufacturing process, the solid-state imaging device 21 shown in FIG. 1 is formed. The order of forming the p-type first element isolation impurity diffusion layer 30 and the p-type second element isolation impurity diffusion layer 31 may be reversed.

By manufacturing through the above-described high-acceleration ion implantation process, the formation of the p-type first element isolation impurity diffusion layer 30 and the p-type second element isolation impurity diffusion layer 31 becomes n-type. This can be performed at a required appropriate position in the semiconductor substrate 24, and the solid-state imaging device 21 having the above effects can be obtained.

In the above embodiment, the pattern of the p-type first element isolation impurity diffusion layer 30 and the pattern of the p-type second element isolation impurity diffusion layer 31 are the same. As shown in the modification, the p-type first element isolation impurity diffusion layer 30 is replaced with a p-type first element isolation impurity diffusion layer 30 formed in a lattice pattern including the pattern of the p-type first element isolation impurity diffusion layer 30. A second element isolation impurity diffusion layer 31 'may be provided. In this way, the p-type second element isolation impurity diffusion layer 31 ′ has a lattice-like pattern surrounding the region immediately below the photodiode 22, and in addition to the above effects, sandwiches the lower part of the vertical transfer path. Blooming caused by mixing of charges from the adjacent photodiodes 22 can be prevented.

Although the photodiodes 22 are arranged two-dimensionally (in a matrix) in the above-described embodiment, the same effects can be obtained when the photodiodes 22 are arranged one-dimensionally.

[0037]

As is apparent from the above description, according to the present invention, the adjacent photoelectric conversion portions can be reliably separated by the element isolation region, and all the electric charges accumulated in the photoelectric conversion portions can be obtained. Can be swept out to the semiconductor substrate without increasing the reverse bias voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing an embodiment of the present invention.

FIG. 2 is an impurity concentration distribution diagram in a depth direction of each impurity diffusion layer along a cutting line AA in FIG. 1;

3 is an impurity concentration distribution diagram in a depth direction of each impurity diffusion layer along a cutting line BB in FIG. 1;

FIG. 4 is a diagram showing a potential profile in a depth direction of each impurity diffusion layer along an AA cutting line and a BB cutting line in FIG. 1;

FIG. 5 is a cross-sectional view for explaining a process of forming a first element isolation impurity diffusion layer and a second element isolation impurity diffusion layer in one embodiment of the present invention.

FIG. 6 is a plan view showing a pattern of a first element isolation impurity diffusion layer and a second element isolation impurity diffusion layer in one embodiment of the present invention.

FIG. 7 is a plan view showing a pattern of a first element isolation impurity diffusion layer and a second element isolation impurity diffusion layer according to a modification of one embodiment of the present invention.

FIG. 8 is a sectional view of a main part showing a conventional technique.

9 is an impurity concentration distribution diagram in the depth direction of each impurity diffusion layer taken along the line A′-A ′ in FIG. 8;

FIG. 10 is an impurity concentration distribution diagram in the depth direction of each impurity diffusion layer along a cutting line B′-B ′ in FIG. 8;

11 is a sectional view taken along line A'-A 'in FIG. 8 and B'-
FIG. 7 is a diagram showing a potential profile in a depth direction of each impurity diffusion layer along a cutting line B ′.

FIG. 12 is an impurity concentration distribution diagram corresponding to FIG. 10 for describing a conventional problem avoidance method.

FIG. 13 is a diagram showing a potential profile corresponding to FIG. 11 for explaining a conventional problem avoidance method.

[Explanation of symbols]

 Reference Signs List 22 photodiode 21 element isolation region 24 n-type semiconductor substrate 27 p-type well 28 n-type impurity diffusion layer 30 first p-type element isolation impurity diffusion layer 31 31 ′ second p-type Element isolation impurity diffusion layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA05 AA10 AB01 BA10 CA04 CA18 DA31 DA32 EA01 EA16 FA06 FA08 FA13 FA26 5C024 BX00 CX12 CX54 GX03 GZ03

Claims (6)

[Claims] A semiconductor substrate; a photoelectric conversion unit provided on the semiconductor substrate in a predetermined arrangement to generate accumulated charges according to incident light; an element isolation region separating the photoelectric conversion unit; In a solid-state imaging device comprising: a first impurity diffusion layer for discharging excess charges generated in the photoelectric conversion unit to the outside, the element isolation region includes a second impurity diffusion layer and a second impurity diffusion layer. A solid-state imaging device comprising a third impurity diffusion layer below the third impurity diffusion layer. 2. The photoelectric conversion unit according to claim 1, wherein the photoelectric conversion units are arranged two-dimensionally, and a third impurity diffusion layer is provided so as to surround a region immediately below the photoelectric conversion unit. 20. The solid-state imaging device according to claim 20. 3. The solid-state imaging device according to claim 2, wherein the third impurity diffusion layer is formed in a substantially lattice shape at a predetermined depth from the surface in the semiconductor substrate. 4. The method according to claim 1, wherein the position showing the maximum peak concentration in the impurity profile of the second impurity diffusion layer is substantially the same depth as the position showing the maximum potential of the photoelectric conversion unit. Solid-state imaging device. 5. The semiconductor device according to claim 1, wherein the third impurity diffusion layer is provided at a position substantially in the middle in the depth direction between the second impurity diffusion layer and the first impurity diffusion layer. 20. The solid-state imaging device according to claim 20. 6. The solid-state imaging device according to claim 1, wherein the third impurity diffusion layer has the same pattern as the second impurity diffusion layer.