JP2001263155A - Engine control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an engine control device capable of reducing processing load at the time of an engine stall. SOLUTION: An edge time measuring counter 103 inputs a crank signal of a pulse string for every prescribed angle interval corresponding to rotation of a crankshaft of an engine, performs a count operation, measures a pulse interval and is reset by a pulse input of the crank signal. When a count value of the edge time measuring counter 103 exceeds a prescribed decision value, a CPU 11 resets the counter 103 and switches a decision value for starting of an engine stall processing interruption task and resetting of the counter 103 to a small value of 8 msec from 600 msec until that time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control device, and more particularly, to engine stall determination and activation of a processing task when the engine stalls.

[0002]

2. Description of the Related Art An engine control device is a device for controlling fuel injection control, ignition timing control, idle speed control, and the like, and operates an engine in an optimum state. That is, signals from various sensors that detect the engine operating state, such as a crank sensor and an engine water temperature sensor, are transmitted as E.
Input to a CU (Electronic Control Unit) to control the optimal fuel injection amount, injection timing, ignition timing, etc. More specifically, control synchronized with engine rotation, such as ignition control and injection control, that is, control synchronized with the crank angle generates a signal such as an ignition pulse when an offset time from a crank edge (edge of a crank signal) elapses. Let's do it.

In addition, it is determined that the engine has stopped unless a pulse of a crank signal (rotation sensor signal) is input for a certain period of time, and this is generally realized by software. However, in recent years, to reduce the load on software,
Techniques for realizing the engine stall determination by hardware have been proposed. Specifically, as shown in FIG. 9, when a pulse of the crank signal is input (t10, t11), the engine stall determination counter is reset. When the counter value exceeds a predetermined value without inputting a pulse (t12), an engine stall determination flag is turned on, and thereafter, every predetermined time (for example, 8
Every msec), the engine stall processing interrupt task is activated, and a calculation value for the restart is obtained according to a change in the engine state when the engine stall state continues (such as a decrease in cooling water temperature). By incorporating a hardware function in this way, the load on software can be reduced.

However, in this method, it is necessary to constantly monitor the engine stall determination flag to determine the content thereof, resulting in an increase in load. That is, as shown in FIG. 9, it is necessary to determine whether the engine stall determination flag is on or off. Therefore, it is necessary to always start the process (for example, every 8 msec).

[0005]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and an object of the present invention is to provide an engine control device capable of reducing a processing load at the time of engine stall. is there.

[0006]

According to the first aspect of the present invention, the engine stall determination counter inputs a crank train of a pulse train at predetermined angular intervals corresponding to the rotation of the crankshaft of the engine, and performs a counting operation. To measure the pulse interval, and reset by the pulse input of the crank signal. When the count value of the engine stall determination counter exceeds a predetermined determination value by the processing unit, the engine stall determination counter is reset, and
The determination value for starting the engine stall interrupt task and resetting the counter is switched to a small value. When the count value of the engine stall determination counter exceeds this determination value, the counter is reset, and an engine stall interrupt task is activated to perform a process such as obtaining a calculated value for restart.

Conventionally, if a hardware function for turning on the engine stall determination flag is provided when the counter value exceeds a predetermined value without inputting a pulse, it is necessary to constantly monitor the engine stall determination flag and determine its contents. This caused an increase in the load. On the other hand, according to the present invention, in the first engine stall process, the counter reset and the engine stall determination time are switched to short values so that the task is started by hardware, and the task start by software after the first engine stall is unnecessary. As a result, the necessary engine start can be started. Thus, the processing load at the time of engine stall can be reduced.

According to the second aspect of the present invention, the pulse interval is measured by the pulse interval measuring means with respect to the crank signal of the pulse train at every predetermined angular interval corresponding to the rotation of the crankshaft of the engine, and the multiplied signal is obtained. By means of generation
Based on the current pulse interval by the pulse interval measuring means, a multiplied signal of an integral multiple frequency is generated until the next pulse. Further, the control means controls the engine based on the multiplied signal. As described above, by providing a system that generates a multiplied signal at a predetermined angular interval and synchronizes with the engine rotation, the calculation for converting from angle to time can be omitted, and the processing load for engine control can be reduced. Reduction and improvement in accuracy can be achieved. In this system, the pulse interval measuring means can be used as an engine stall counter.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. The present embodiment is embodied in a control device for a multi-cylinder gasoline engine for an automobile. FIG. 1 shows a configuration of an engine control ECU 1 according to the present embodiment. The engine is a five-cylinder four-cycle engine.

The engine control ECU 1 includes a microcomputer (hereinafter referred to as a microcomputer) 10, a power supply circuit 20, an input / output circuit 30, and an EEPROM 40. The power supply circuit 20 receives power from the battery 2 and supplies a predetermined voltage to each device in the ECU 1. The microcomputer 10 is a CP
A U11, a ROM 12, a RAM 13, an A / D converter 14, an input / output interface 15, and a timer module 16 are provided. Data is exchanged between these members via a data bus. An EEPROM 40 is connected to the input / output interface 15, and data is exchanged with the EEPROM 40 via the input / output interface 15. The input / output circuit 30 inputs signals from sensors, switches, and the like, and outputs drive signals to injectors (fuel injection valves) and ignition devices. Further, the communication line 3 is connected to the input / output circuit 30, and data is exchanged with another ECU via the input / output circuit 30. The CPU 11 of the microcomputer 10 has a sensor
A signal (data) from a switch or the like and data from the communication line 3 are transmitted to the input / output circuit 30 and the input / output interface 1.
5, various calculations are performed based on the data, and the injectors and the like are driven and controlled via the input / output interface 15 and the input / output circuit 30.

Here, the signals captured by the engine control ECU 1 include a crank signal from a crank sensor and a cam signal from a cam sensor. FIG. 2 shows a crank signal and a cam signal for one engine cycle (720 ° CA).

The crank signal generated by the crank sensor is composed of a pulse train at predetermined angular intervals corresponding to the rotation of the crankshaft of the four-stroke engine. Have.
The crank signal in the present embodiment has a missing tooth configuration in which two pulses are missing every 60 pulses (60-2 tooth structure).
That is, the pulse interval of the pulse train is 6 ° CA, and the missing tooth portion from which the pulse is removed in the middle of this pulse train is 360 ° C.
A for each A, and one of them (missing teeth every 720 ° CA) is a front missing tooth and the other (the other missing teeth every 720 ° CA) is a back missing tooth. The cam signal generated by the cam sensor is synchronized with the rotation of the camshaft of the engine,
This is a cylinder discrimination signal for specifying the cylinder position, and the falling edges are at 144 ° CA intervals. In the cam signal, the cam signal is at the L level at the falling edge (timing at t10) immediately after the front missing tooth of the crank signal, and the H level is at the falling edge immediately after the back missing tooth (timing at t20). . That is, if the cam signal level is L at the missing tooth position, it can be determined that the tooth is a front missing tooth, and if it is H, it can be determined that the tooth is a back missing tooth.

The crank signal is generated by the timer module 1 shown in FIG.
6 is input to the hard crank 100. The cam signal is taken into the microcomputer 10 via the input / output circuit 30. On the other hand, the hard crank 100 provided in the timer module 16 of FIG. 1 is a functional unit that processes a crank signal in a hardware manner. With this hard crank 100,
The processing of the crank signal shown in FIG. 2 (the generation of an angle signal obtained by dividing the time between crank edges) can be performed by hardware.

FIG. 3 shows the configuration of the hard crank 100. In FIG. 3, a prescaler 101 and a frequency divider 1
02, edge time measurement counter 103, multiplication register (edge time storage register) 104, and multiplication counter 10
5, an input capture register (ICR) 106, a guard counter 107, a reference counter 108, a follow-up counter (angle counter) 109, an ignition / injection angle counter 110, and an output compare register (OCR).
111 is provided. Signal P from prescaler 101
φ is the edge time measurement counter 1 via the frequency divider 102
03 is sent. The signal Pφ is sent to a tracking counter (angle counter) 109. Further, the crank signal is sent to the edge time measurement counter 103, the input capture register (ICR) 106, and the guard counter 107.

FIG. 4 shows an angle clock (angle signal).
4 shows a time chart of occurrence. FIG. 4 shows the input crank signal, the count value of the edge time measurement counter 103, the stored value of the multiplication register 104, and the multiplication counter 105.
Count value, output signal (multiplication clock) of the multiplication counter 105, n times the value of the guard counter 107, count value of the reference counter 108, count value of the follow-up counter 109, count value of the ignition / injection angle counter 110 Is shown.

The edge time measurement counter 103 in FIG.
A crank signal is input to measure a time (pulse interval) between crank edges. More specifically, the edge time measurement counter 103 as a pulse interval measurement means is a counter that counts up in a time-synchronized manner as shown in FIG. 4, and measures a time between crank edges (between falling edges of a crank signal). This count value is reset every time a crank edge (pulse) is input. Each time a crank edge is input, an input capture register (ICR) 106 captures a pulse interval (count value) of the edge time measurement counter 103, multiplies this value (measured value) by 1 / n, and multiplies the value by a multiplication register. Transfer to 104. The transferred data becomes an initial value of the multiplication counter 105 which is a down counter. As the multiplication value (n value), for example, “32” can be cited. The input capture register (ICR) 106 outputs an interrupt signal each time a crank edge is input (every 6 ° CA).

The multiplication counter 105 shown in FIG. 3 uses the time between crank edges measured by the edge time measurement counter 103 to generate a multiplied clock whose crank edge time is 1 / n. Specifically, the multiplication counter 105
As shown in FIG. 4, the operation of counting down with time synchronization and generating an increased clock when the underflow occurs and repeating the operation of returning the count value to the initial value are repeated. When the next crank edge (falling edge of the crank signal) is input, the value of the multiplication register 104 and the initial value of the multiplication counter 105 are updated to the latest values. As described above, the multiplying counter 105 as the multiplied signal generating means generates a multiplied signal (multiplied clock) having a frequency of an integral multiple until the next pulse based on the current pulse interval by the edge time measuring counter 103.

As shown in FIG. 4, the reference counter 108 of FIG. 3 performs a count-up operation with a multiplied clock.
The follow-up counter 109 in FIG. 3 counts up with a time synchronous clock (counts with an internal clock). The guard counter 107 is a counter that counts up each time a falling edge of the crank signal is input, and transfers a value n times (multiplied) the value before counting up to the reference counter 108 at the same time as the input of the crank edge.

Here, as shown in FIG.
The count value of 8 is the value (n times the count value) transferred from the guard counter 107 when the crank edge is input.
Cannot be exceeded. In addition, the tracking counter 109
Counts up only when it is smaller than the count value of the reference counter 108. An angle clock (angle signal) is generated in synchronization with the count-up of the tracking counter 109. Thus, the three counters 107, 10
8, 109 generates an angle clock.

In the present embodiment, the internal clock (signal Pφ from the prescaler) is set to 20 MHz, and the tracking counter 109 can operate at a higher speed than other counters. In FIG. 4, at the time of deceleration, as the count operation of the reference counter 108 and the follow-up counter 109, the value of the reference counter 108 reaches n times the value of the guard counter 107 before the input of the crank edge. The count-up of 109 is prohibited. In this way, the guard counter 107 makes the reference counter 1
08 and the count-up operation of the tracking counter 109 stops at the multiple. As a result, the follow-up counter 10
The counting operation of No. 9 is stopped to prevent the generation of an angle clock having a certain value or more.

The angle counter 110 for ignition / injection in FIG. 3 receives the angle clock from the follow-up counter 109 and counts up (see FIG. 4). Based on the count value of the ignition / injection angle counter 110, ignition / injection control is performed in synchronization with crank angle using a compare register. That is, the ignition / injection angle counter 110 can perform hardware control of ignition / injection and the like in synchronization with crank angle. As described above, a system for generating a multiplied signal (multiplied clock) at predetermined angular intervals and synchronizing with engine rotation can eliminate a calculation for converting from angle to time, thereby reducing a processing load. And accuracy improvement (n =
32 means that LSB = 0.1875 ° CA) can be achieved. In the present embodiment, the CPU 11 performs engine control based on the multiplied clock.

In FIG. 2, the side of the missing tooth of the crank signal is the system initialization location. This system initialization position is the position of BTDC 6 ° CA of the fourth cylinder. When the count value of the follow-up counter 109 is initialized at this position (timing of t11), the ignition / injection angle counter 110
, The ignition / injection angle counter 110 is initialized and synchronized with the reset signal.

The edge time measurement counter 10 shown in FIG.
3 is a count value and an output compare register (O
When the count value reaches a value set in the output compare register (OCR) 111, an engine stall determination signal is generated. That is, when the count value of the edge time measurement counter 103 reaches the value set in the output compare register (OCR) 111, an interrupt is generated, and it can be detected that the edge input has stopped for a predetermined time or more. As described above, in the present embodiment, the edge time measurement counter 1
03 is used as an engine stop determination counter. Here, in the present embodiment, the output compare register (OCR) 111 has 60
0 msec is initially set, and when the pulse interval of the crank signal is 600 msec or more, it is determined that an engine stall has occurred. Further, the value of the output compare register (OCR) 111, that is, the engine stall determination time can be set by software (by the CPU 11).
And an engine stall process is performed.

Next, the engine control E configured as described above will be described.
The operation of the CU (engine control device) will be described. FIG. 5 shows a time chart at the time of engine stall. FIG. 5 shows the count values of the crank signal and the engine stop determination counter (edge time measurement counter 103).

The engine stall determination counter is set to t1, t2 in FIG.
At this timing, the counting operation is performed while being initialized at the falling edge of the pulse of the crank signal. Then, the pulse output of the crank signal is stopped by the occurrence of the engine stall, and when the count value of the engine stall determination counter reaches the value of the output compare register (OCR) 111 (timing at t3), the engine stall determination signal is generated.

On the other hand, the CPU 11 executes the processing shown in FIGS. First, the CPU 11 activates the processing in FIG. 6 when an interrupt occurs at each crank edge input (at timings t1 and t2 in FIG. 5). Then, in step 100, the CPU 11 outputs the output compare register (OC).
R) The engine stall determination time at 111 is 600 msec.
Is set. That is, when the pulse of the crank signal is input, the engine stall determination time is reset to the initial value (600 msec) in the interrupt task. Thereby, it can be set as the first engine stall determination value.

Further, the CPU 11 executes step 10 in FIG.
In step 1, crank signal processing such as ignition control and injection control is performed. Further, the CPU 11 activates the processing in FIG. 7 when an engine stall determination interrupt occurs (timing at t3 in FIG. 5).
Then, in step 200, the CPU 11 resets the engine stall determination counter (the edge time measurement counter 103) to zero. Further, in step 201, the CPU 11 sets 8 msec as an engine stop determination time in the output compare register (OCR) 111. That is,
First engine stall judgment task by hardware (600mse
(Start when no pulse is input during c)), and set the next engine stall determination value to 8 msec.

Further, the CPU 11 executes step 20 in FIG.
In 2, the engine stall task is started. As the engine stall process, the CPU 11 clears the rotation system RAM value in step 300 of FIG. Specifically, the rotation speed and the 6 ° CA time value are cleared. Further, the CPU 11 determines in step 30
In step 1, a calculation and a set process for restart at the time of engine stall are executed. As described above, in the engine stall process, the restart calculation is performed. In the restart calculation, the rotational system RA such as the cylinder number is used.
M is initialized, the injection width is initialized, and the ignition timing is initialized.

Then, the engine stall determination counter is reset at the timing of t3 in FIG. 5, and when the count value of the engine stall determination counter reaches the OCR value 8 ms later (timing of t4), the engine stall processing interrupt task is activated and FIG. Is performed. Similarly, t5 in FIG.
For example, when the engine stall continues, the calculated value is updated every 8 msec.

As described above, this embodiment has the following features. (A) The edge time measurement counter 103 as an engine stall determination counter inputs a crank signal and counts to measure a pulse interval, and is reset by the input of a pulse of the crank signal. The CPU (processing unit) 11 When the count value of the engine stall determination counter exceeds a predetermined determination value, steps 200 and 20 in FIG.
In step 1, 202, the engine stall determination counter is reset, and the determination value for starting the engine stall interrupt task and resetting the counter is set to 600 m.
The value is changed from the second to a small value (8 msec). When the count value of the engine stall determination counter exceeds the determination value (8 msec), the counter is reset, and the engine stall processing interrupt task is activated to perform processing such as obtaining a calculation value for restart. Will be

Therefore, conventionally, as shown in FIG. 9, if a hardware function for turning on an engine stall determination flag is provided when a counter value exceeds a predetermined value without inputting a pulse,
It is necessary to constantly monitor the engine stall determination flag to determine its contents, which has resulted in an increase in load. In this embodiment, however, in the first engine stall process, the counter reset and the engine stall determination time are switched to short values. In this way, the task can be started by hardware, so that the task start by software after the first engine stall process becomes unnecessary, and the necessary engine start operation can be started while using the hardware interrupt function. Thus, the processing load at the time of engine stall can be reduced.

Further, in the conventional method shown in FIG. 9, a delay τ occurs from the timing t12 when the engine stall determination counter reaches the judgment value to the task activation, but in the present embodiment, the task activation is performed in the first engine stall process. As a result, as shown in FIG. 5, when the engine stall judgment counter reaches the judgment value (timing at t3), the task is started immediately, so that the engine stall process can be performed quickly. (B) Hard crank 100 (at least includes edge time measurement counter 103 and multiplication counter 105)
In the system in which the CPU 11 as the control means performs the engine control based on the multiplied clock,
Since the edge time measurement counter 103 is used as an engine stall determination counter, it is practically preferable.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an engine control ECU according to an embodiment.

FIG. 2 is a time chart of one engine cycle (720 ° CA).

FIG. 3 is a configuration diagram of a hard crank.

FIG. 4 is a time chart for explaining generation of an angle clock by a hard crank.

FIG. 5 is a time chart for explaining the operation.

FIG. 6 is a flowchart for explaining the operation.

FIG. 7 is a flowchart for explaining the operation.

FIG. 8 is a flowchart for explaining the operation.

FIG. 9 is a time chart for explaining a conventional technique.

[Description of Signs] 1 ... Engine control ECU, 10 ... Microcomputer, 11 ... CP
U, 16: timer module, 100: hard crank, 103: edge time measurement counter, 104: multiplication register, 105: multiplication counter, 108: reference register, 109: follow-up counter, 110: ignition / injection angle counter.

Claims (2)

[Claims] 1. An engine stop input which receives a pulse signal of a pulse train at predetermined angular intervals corresponding to the rotation of a crankshaft of an engine, measures a pulse interval by performing a count operation, and is reset by a pulse input of the crank signal. A processing unit that resets the engine stall determination counter when the count value of the engine stall determination counter exceeds a predetermined determination value, and switches the determination value to a small value for activating an engine stall interrupt task and resetting the counter. An engine control device comprising: 2. A pulse interval measuring means for inputting a crank signal of a pulse train at a predetermined angular interval corresponding to the rotation of a crankshaft of an engine to measure a pulse interval, and based on a current pulse interval by said pulse interval measuring means. A multiplied signal generating means for generating a multiplied signal of an integer multiple frequency until the next pulse, and a control means for performing engine control based on the multiplied signal,
The engine control device according to claim 1, wherein the pulse interval measuring unit is used as the engine stall determination counter.