JP2001298099A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide a nonvolatile semiconductor memory device adaptable to miniaturization and high performance of a MIS transistor of a peripheral circuit and a method of manufacturing the same. SOLUTION: A floating gate electrode 13 is formed on a Si substrate 11 with a gate insulating film 12 interposed therebetween. Impurity ion implantation and activation are performed to form source / drain diffusion layers 18 and 19 in regions located on both sides of the floating gate electrode 13 in the Si base 11. After that, the floating gate electrode 13
After forming the sidewall spacer 20 on the side surface of
An alumina film 14 covering the floating gate electrode 13 and the sidewall spacer 20 (or an interlayer insulating film) and including a portion to be an inter-electrode insulating film 14a is formed, and a control gate electrode 15 including a metal film is formed thereon. After the impurity activation process, which is a high-temperature process, is performed, the inter-electrode insulating film 14 is removed.
a. Since the control gate electrode 15 is formed, a metal oxide film or a metal film can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a memory cell transistor having a floating gate structure and a method of manufacturing the same, and more particularly to miniaturization and high performance of a MIS transistor in a peripheral circuit portion. Regarding things to respond.

[0002]

2. Description of the Related Art In recent years, a memory section (non-volatile semiconductor memory device) in which a memory cell transistor (non-volatile memory element) having a floating gate structure is arranged, and a memory section for writing, reading and erasing information in the memory section. In a memory / CMOS hybrid non-volatile semiconductor memory device including a peripheral circuit section in which a MIS transistor and the like are arranged, miniaturization and high performance of the MIS transistor arranged in the peripheral circuit section and arrangement in the memory section are provided. There is a need for a manufacturing method that can ensure both reliability and high performance of memory cell transistors.

FIGS. 4A to 4C are cross-sectional views showing steps of manufacturing a memory cell transistor of a conventional nonvolatile semiconductor memory device.

First, in a step shown in FIG. 4A, a 9-nm thick gate insulating film 112 formed by pyro-oxidation on a Si substrate 111 made of P-type silicon is formed.
A floating gate electrode 113 made of a phosphorus-doped first polysilicon film and an interelectrode insulating film 11 made of an ONO film
4 and a control gate electrode 115 made of a phosphorus-doped second polysilicon film are sequentially formed.

Although the state of the MIS transistor in the peripheral circuit portion is not shown in FIG. 4A, generally, the control gate electrode 11 of the memory cell transistor is not shown.
5 and the gate electrode of the MIS transistor of the peripheral circuit are often patterned from a common polysilicon film. In this case, after a first polysilicon film and an ON film are sequentially deposited on the gate insulating film, the gate insulating film, the first polysilicon film, and the ON film of the memory section are left.
Gate insulating film of peripheral circuit portion, first polysilicon film, O
After removing the N film, thermal oxidation is performed to form a gate insulating film in the peripheral circuit portion, while turning on the ON film in the memory portion.
Change to O film. Then, after depositing a second polysilicon film on the substrate, in the memory section, the second polysilicon film, the ONO film, the first polysilicon film, and the gate insulating film are patterned, and FIG. The structure of a) is adopted. On the other hand, in the peripheral circuit portion, a gate electrode is formed by patterning the second polysilicon film and the gate insulating film.

Next, in the step shown in FIG.
Thermal oxidation is performed at 30 ° C. for 30 minutes. By this processing, a silicon oxide film 116 continuously covering the exposed surface of the Si substrate 111, the side surfaces of the floating gate electrode 113 and the control gate electrode 115, and the upper surface of the control gate electrode 115 is formed on the substrate. It is formed. This is because the side surface of the floating gate electrode 113 is covered with an oxide film to prevent implanted ions from penetrating the end of the floating gate electrode 113.

Next, in the step shown in FIG. 4 (c), phosphorus ions (P +) are accelerated to a region located on both sides of the floating gate electrode 113 in the Si substrate 111 at an acceleration energy of 40 keV and an energy of 40 keV.
The source region 118 and the drain region 119 are formed under the condition of a dose amount of 2 × 10 ¹⁵ cm ⁻² .

Thereafter, a high-temperature heat treatment or, for example, 850 ° C.
An oxidation treatment is performed for 30 minutes. This is the source
The impurities implanted into the drain regions 118 and 119 are activated to obtain desired diffusion depth and breakdown voltage characteristics.
This is to improve reliability by recovering damage to the gate insulating film 112 due to ion implantation or the like.

[0009]

In recent years, the gate electrode of the MIS transistor in the peripheral circuit section for processing signals to the memory cell array (memory section) is similar to the MIS transistor in a general CMOS device. In addition, there is an increasing demand to improve the performance by forming a polymetal structure in which a polysilicon film and a metal film are laminated. Therefore, there is a need for the control gate electrode of the memory cell transistor to have a polymetal structure. Attempts have been made to reduce the size of the transistor by changing the gate insulating film of the MIS transistor from a silicon oxide film to a metal oxide film such as a Ta ₂ O ₅ film having a high dielectric constant. It is necessary to adopt a structure corresponding to this for the inter-electrode insulating film.

However, if the control gate electrode and the inter-electrode insulating film of the memory cell transistor of the above-mentioned conventional nonvolatile semiconductor memory device are adapted to the structure of the MIS transistor in the peripheral circuit portion, the following problems may occur. There is.

First, in the process shown in FIG. 4B, when performing thermal oxidation, in the control gate electrode having a polymetal structure, if the thermal oxidation treatment is performed, the composition of the metal film may be changed. Further, when a metal oxide film having a high dielectric constant is used for the gate insulating film, the characteristics of the metal oxide film may be deteriorated. Such a problem may occur in the MIS transistor in the peripheral circuit section. That is, it has been difficult to realize both the miniaturization and high performance of the MIS transistor in the peripheral circuit portion and the high reliability and high performance of the memory cell transistor.

A first object of the present invention is to reduce the temperature after the step of forming a control gate electrode having a polymetal or single-layer metal structure or a step of forming an inter-electrode insulating film of a metal oxide film, thereby achieving high performance. It is an object of the present invention to provide a nonvolatile semiconductor memory device equipped with a simplified memory cell transistor and a method of manufacturing the same.

A second object of the present invention is to provide a nonvolatile semiconductor memory device which can be adapted to miniaturization and high performance of a MIS transistor such as a peripheral circuit portion, and a method of manufacturing the same.

[0014]

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a step (a) of forming a floating gate electrode on a semiconductor region of a substrate via a gate insulating film;
(B) implanting impurity ions into regions of the semiconductor region located on both sides of the floating gate electrode to form a source / drain implantation layer; and after the step (b), the source / drain (C) forming a source / drain diffusion layer by performing a heat treatment for activating the impurity introduced into the implantation layer; and (c) after the step (c),
A step (d) of forming an inter-electrode insulating film covering at least an upper surface of the floating gate electrode; and a step (e) of forming a control gate electrode facing the floating gate electrode with the inter-electrode insulating film interposed therebetween. In.

According to this method, the step of activating the impurities introduced into the source / drain diffusion layers and then forming the inter-electrode insulating film and the control gate electrode is performed. After forming the electrodes,
There is no need to perform high-temperature treatment that causes a change in metal properties. Therefore, a non-volatile semiconductor memory device in which a high performance memory cell transistor using a metal oxide film such as an alumina film as an inter-electrode insulating film or a polymetal film or a single-layer metal film as a control gate electrode is formed. It becomes possible. Further, when a CMOS device is to be arranged on a common substrate, a memory transistor having a MIS transistor with a finer and higher performance provided in a peripheral circuit portion or the like is suitable for a memory transistor suitable for a process of a hybrid CMOS device. The manufacturing process can be realized.

In the step (c), by performing the heat treatment in an oxidizing atmosphere, it is possible to recover damage caused on the gate insulating film due to ion implantation of impurities or the like.

After the step (a) and before the step (b), a step of forming a protective insulating film on the substrate so as to cover the floating gate electrode is further included. In addition, it is possible to prevent the impurity ions from penetrating the end of the floating gate electrode and damaging the gate insulating film.

After step (b) and before step (d), an insulating film is deposited on the substrate and then anisotropically etched to form sidewall spacers on the side surfaces of the floating gate electrode. By further including the step of performing, it is possible to avoid problems caused by the control gate electrode formed thereafter straddling the Si substrate.

After the step (b) and before the step (d), an insulating film is deposited on the substrate and then subjected to a planarization process to form an interlayer insulating film filling the periphery of the floating gate electrode. By further including the step of performing, it is possible to avoid a problem caused by the control gate electrode formed thereafter straddling the Si substrate.

In the step (d), by forming a metal oxide film as the inter-electrode insulating film, generally, a gate insulating film suitable for miniaturization using a metal oxide film having a higher dielectric constant than a silicon oxide film. A film can be formed.

In the step (e), the control gate electrode is formed from a conductor film including at least one metal film, so that a memory cell transistor having excellent electrical characteristics using the low-resistance control gate electrode can be obtained. Can be formed.

According to a first nonvolatile semiconductor memory device of the present invention, there is provided a substrate having a semiconductor region, a floating gate electrode provided on the semiconductor region via a gate insulating film, and the floating gate of the semiconductor region. Source / drain diffusion layers provided in regions located on both sides of the electrode, sidewall spacers provided on side surfaces of the floating gate electrode, and the entire upper surface of the floating gate electrode and at least a part of the sidewall; And a control gate electrode capacitively coupled to the floating gate electrode, and an inter-electrode insulating film interposed between the floating gate electrode and the control gate electrode.

Thus, as described above, a high-performance memory cell transistor having an inter-electrode insulating film made of a metal oxide, a polymetal film, and a control gate electrode made of a single-layer metal film is arranged. A nonvolatile semiconductor memory device as described above can be easily obtained.

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a substrate having a semiconductor region; a floating gate electrode provided on the semiconductor region via a gate insulating film; A source / drain diffusion layer provided in a region located on both sides of the electrode; an interlayer insulating film burying the periphery of the floating gate electrode; and an entire upper surface of the floating gate electrode and at least a part of the interlayer insulating film. A control gate electrode capacitively coupled to the floating gate electrode, and an inter-electrode insulating film interposed between the floating gate electrode and the control gate electrode.

With the first or second nonvolatile semiconductor memory device, as described above, an inter-electrode insulating film made of a metal oxide, a polymetal film, and a control gate formed of a single-layered metal film. A nonvolatile semiconductor memory device in which high-performance memory cell transistors having electrodes are arranged can be easily obtained. In addition, when it is desired to dispose the memory unit and the CMOS device on a common substrate, a memory and a MIS transistor, which have been miniaturized and improved in performance, are arranged in a peripheral circuit unit.
A memory cell transistor suitable for a CMOS embedded semiconductor device can be obtained.

The inter-electrode insulating film is made of a metal oxide.
Preferably, Al _Two O_Three Membrane, Ta_Two O
_Five Membrane, CeO_Two Membrane, ZrO_Two Film, MgO film and ferroelectric
More preferably, it comprises at least one of the membranes
Good.

Preferably, the control gate electrode is formed of a conductor film including at least one metal film.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
(E) is a cross-sectional view showing a step of manufacturing the memory cell transistor of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

First, in the step shown in FIG. 1A, a 9 nm-thick silicon oxide film 12x is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation, and then a phosphorus-doped thickness of about 150 nm is formed. Is formed, and the first polysilicon film is patterned to form a floating gate electrode 13 having a gate length of about 0.4 μm. At this time, the silicon oxide film 12x may be patterned at the same time.

Next, in the step shown in FIG.
Using the gate electrode 13 as a mask, phosphorus ions
(P +) at an acceleration energy of 20 keV and a dose of 2 ×
10 ^Fifteencm^-2And the floating gate in the Si substrate 11 is implanted.
In the regions located on both sides of the gate electrode 13, an N-type source
An entry layer 18x and a drain injection layer 19x are formed.

Next, in the step shown in FIG. 1C, annealing is carried out at 850 ° C. for 60 minutes in a nitrogen atmosphere, so that the N-type source implantation layer 1 formed on the Si substrate 11 is formed.
By activating and diffusing phosphorus between 8x and the drain injection layer 19x, the N-type source diffusion layer 18 and the drain diffusion layer 1x are diffused.
9 are formed. Then, a thickness of about 150 nm is formed on the substrate.
After depositing the CVD silicon oxide film, a sidewall spacer 20 is formed by performing anisotropic dry etching while leaving the CVD silicon oxide film on the side surface of the floating gate electrode 13. At this time, the silicon oxide film 12
x is also patterned to form a gate insulating film 12 (tunnel oxide film).

Next, in a step shown in FIG. 1D, an alumina (A) which is a metal oxide film having a thickness of about 70 nm is formed on the substrate.
l ₂ O ₃ ) A film 14 is deposited. At this time, when the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, the alumina film 14 serving as the gate insulating film of the MIS transistor is formed on the substrate also in the peripheral circuit portion.

Next, in the step shown in FIG. 1E, a laminated film (polymetal film) of a phosphorus-doped second polysilicon film and a tungsten film is deposited on the substrate, and then the laminated film is patterned. Thereby, the control gate electrode 1 is sandwiched between the floating gate electrode 13 and the alumina film 14.
5 is formed. A portion of the alumina film 14 sandwiched between the floating gate electrode 13 and the control gate electrode 15 functions as an inter-electrode insulating film 14a.
The other part functions as the protective film 14b. At this time,
The MIS transistor in the peripheral circuit portion is shared with a common Si substrate 11.
When it is formed on the upper surface, the laminated film, which is a polymetal film, is also patterned in the peripheral circuit portion to form a gate electrode.
The portion sandwiched by the functions as a gate insulating film (tunnel oxide film).

According to the manufacturing method of this embodiment, FIG.
In the step shown in (b), the impurities implanted in the Si substrate 11 are activated.
Thereafter, there is no need to perform a high-temperature heat treatment, and the deterioration of the alumina film or the polymetal film can be suppressed. That is, it is not necessary to perform a high-temperature heat treatment after the lamination of the alumina film 14 as the metal oxide film and the polymetal film constituting the control gate electrode. The temperature for depositing the polysilicon film is about 500 ° C., and the temperature for depositing the tungsten film is about 400 ° C. Therefore, depending on this temperature, the characteristics of the metal oxide film may deteriorate. Absent.

When the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, FIG.
After the step shown in (1), a step of activating the implanted impurities is performed in order to form the source / drain diffusion layers of the MIS transistor in the peripheral circuit section. At this time, the memory section is covered with an interlayer insulating film. Thus, it is possible to avoid deterioration of the characteristics of the metal film and the metal oxide film, so that no problem occurs.

As a result, a metal oxide film such as an alumina film having a higher dielectric constant than a silicon oxide film or a silicon nitride film can be used as the inter-electrode insulating film 14a of the memory cell transistor. The capacitance coupling ratio between the memory cell and the control gate electrode 15 is improved, and the area occupied by the memory cell can be reduced. Further, since a low-resistance conductive film such as a polymetal film can be used as a material for forming the control gate electrode 15, the control gate electrode 1
5 is significantly reduced in resistance, and device characteristics such as operation speed can be improved. Further, the common Si substrate 11
When an MIS transistor such as a peripheral circuit portion is formed thereon, the MIS transistor of the peripheral circuit portion having a gate electrode formed of a common laminated film (polymetal film) with the control gate electrode 15 also has a high dielectric constant. By providing a gate insulating film and a low-resistance gate electrode, MI
High performance and miniaturization of the S transistor can be realized.

Further, by forming a sidewall spacer 20 on the side surface of the floating gate electrode 13 before forming the control gate electrode 15, the control gate electrode 15 covers the upper surface of the floating gate electrode 13, and It becomes easy to perform patterning so as not to straddle 11. When the control gate electrode 15 straddles the Si substrate 11, a high electric field is applied from the control gate electrode 15 to the Si substrate 11, which may adversely affect the operation of the memory cell transistor. Thereby, this inconvenience can be reliably avoided. However, even if the control gate electrode 15 straddles the Si substrate 11, no problem occurs depending on the method of applying the voltage to the control gate electrode 15.

In this embodiment, the case where the alumina film is used as the inter-electrode insulating film 14a has been described, but the inter-electrode insulating film 14a can be made of another insulating material. For example, Ta ₂ O ₅ film, Ce
A metal oxide film (high dielectric constant film) such as an O ₂ film, a ZrO ₂ film, and an MgO film can be used. It is also possible to use a ferroelectric film.

Further, in the present embodiment, the control gate electrode 15 is constituted by a laminated film (polymetal film) of a polysilicon film and a metal film. However, the control gate electrode 15 may be constituted by a single-layer metal film. Good. As a metal film in polymetal or a single-layer metal film,
There are a tungsten film, a cobalt film, an aluminum film, a titanium film, a tantalum film, a copper film, and the like, and any of them may be used.

(Second Embodiment) FIGS. 2A to 2G
FIG. 7 is a cross-sectional view illustrating a manufacturing process of the memory cell transistor of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

First, in the step shown in FIG. 2A, a 9 nm-thick silicon oxide film 12x is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation, and then a phosphorus-doped thickness of about 150 nm is formed. Is formed, and the first polysilicon film is patterned to form a floating gate electrode 13 having a gate length of about 0.4 μm.

Next, in the step shown in FIG. 2B, a CVD silicon oxide film 21x is deposited on the substrate,
The side and top surfaces of the floating gate electrode 13 are covered with the silicon oxide film 21x.

Next, in the step shown in FIG.
Using the gate electrode 13 as a mask, phosphorus ions
(P +) with an acceleration energy of 40 keV and a dose of 2 ×
10 ^Fifteencm^-2And the floating gate in the Si substrate 11 is implanted.
In the regions located on both sides of the gate electrode 13, an N-type source
An entry layer 18x and a drain injection layer 19x are formed. this
At this time, the CVD silicon oxide film 21x is used as an injection protection film.
Function. That is, the edge of the lower end of the floating gate electrode 13
Near the gate, the implanted ions penetrate the floating gate electrode 13.
Damage the gate insulating film (tunnel film)
It is for suppressing. Further, the floating gate electrode 13 is formed.
The formed polysilicon film may cause channeling.
And the implanted ions penetrate the entire floating gate electrode 13.
Damage to the gate insulating film (tunnel film)
There is a CVD silicon oxide film 21x which is an injection protection film.
Can suppress this.

Next, in the step shown in FIG. 2D, the Si substrate 11 is subjected to a heat treatment at 850 ° C. for 45 minutes in an oxygen atmosphere.
The source and drain implanted layers 18x and 19x are activated and diffused to form the source and drain diffusion layers 18 and 19, and the floating gate electrode 13 of the silicon oxide film 12x is formed. Damage due to ion implantation into a portion immediately below (a portion serving as a gate insulating film) is recovered, and reliability as an insulating film is improved. At this time, a silicon oxide film formed by oxidizing the region near the upper surface and the side surface of the floating gate electrode 13 and increasing the thickness of the silicon oxide film 12x on the surface of the Si substrate 11 on the side of the floating gate electrode 13 16
forming x. By this process, a gate bird's beak is formed below the edge of the lower end of the floating gate electrode 13, and a portion of the silicon oxide film 12x, which is covered by the floating gate electrode 13 and whose thickness does not change, is not changed. (Tunnel oxide film). By annealing at 850 ° C. for 60 minutes in a nitrogen atmosphere instead of heat treatment in an oxygen atmosphere,
The activation and diffusion of phosphorus in the source injection layer 18x and the drain injection layer 19x formed on the Si substrate 11 may be performed.

Next, in the step shown in FIG. 2E, a CVD silicon oxide film having a thickness of about 150 nm is deposited on the substrate, and then anisotropic dry etching is performed to form a film on the side surface of the floating gate electrode 13. CVD silicon oxide film 21
The sidewall spacers 20 are formed leaving x. At this time, of the CVD silicon oxide film 21x and the silicon oxide film 16x, the portion on the floating gate electrode 13 and the portion not covered with the remaining CVD silicon oxide film serving as the sidewall spacer 20 are also removed. An L-shaped side wall 21 serving as a base of the spacer 20 and the covering oxide film 16 are formed. The silicon oxide film 12x is also patterned to form the gate insulating film 12.

Next, in a step shown in FIG. 2F, alumina (A) which is a metal oxide film having a thickness of about 70 nm is formed on the substrate.
l ₂ O ₃ ) A film 14 is deposited. At this time, when the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, an alumina film 14 serving as a gate insulating film of the MIS transistor is formed on the substrate.

Next, in the step shown in FIG. 2 (g), a laminated film (polymetal film) of a phosphorus-doped second polysilicon film and a tungsten film is deposited on the substrate, and then the laminated film is patterned. Thereby, the control gate electrode 1 is sandwiched between the floating gate electrode 13 and the alumina film 14.
5 is formed. A portion of the alumina film 14 sandwiched between the floating gate electrode 13 and the control gate electrode 15 functions as an inter-electrode insulating film 14a.
The other part functions as the protective film 14b. At this time,
The MIS transistor in the peripheral circuit portion is shared with a common Si substrate 11.
When it is formed on the upper surface, the laminated film, which is a polymetal film, is also patterned in the peripheral circuit portion to form a gate electrode.
The portion sandwiched between the above functions as a gate insulating film.

According to the manufacturing method of this embodiment, FIG.
Since the impurity implanted in the Si substrate 11 is activated in the step shown in FIG. 2D, it is not necessary to perform a high-temperature heat treatment thereafter as far as the memory section is concerned, as in the first embodiment. Therefore, the alumina film 14 which is a metal oxide film
And the deterioration of the polymetal film can be suppressed.

As a result, a metal oxide film such as alumina having a higher dielectric constant than a silicon oxide film or a silicon nitride film can be used as the inter-electrode insulating film 14a of the memory cell transistor. In the same manner as described above, the area occupied by the memory cells can be reduced and the device characteristics such as the operation speed can be improved. In addition, when the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, the MIS transistor It is possible to realize high performance and miniaturization. Also, in the present embodiment, the sidewall spacers 20 are formed on the side surfaces of the floating gate electrode 13 before the control gate electrode 15 is formed, so that the control gate electrode 15 is formed similarly to the first embodiment. Therefore, the application of a high electric field to the Si substrate 11 can be reliably avoided. However, even if the control gate electrode 15 straddles the Si substrate 11, no problem occurs depending on the method of applying the voltage to the control gate electrode 15.

In particular, in this embodiment, FIG.
In the process shown in FIG. 2, since the ion implantation is performed in a state where the CVD silicon oxide film 21x as the implantation protection film is formed, the penetration of the ions at the end of the floating gate electrode 13 and the ion by the channeling to the entire floating gate electrode 13 are performed. There is an advantage that it is possible to suppress the deterioration of the insulating characteristics of the gate insulating film 12 due to the penetration. Further, since the heat treatment is performed in the step shown in FIG. 2D, the damage of the gate insulating film 12 can be recovered.
Furthermore, by performing this heat treatment in an oxidizing atmosphere,
Since the gate bird's beak is formed below the edge at the lower end of the floating gate electrode 13, there is also an advantage that the breakdown voltage between the floating gate electrode 13 and the source / drain diffusion layers 18 and 19 can be secured.

In the case where the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, FIG.
After the step shown in (1), a step of activating the implanted impurities is performed in order to form the source / drain diffusion layers of the MIS transistor of the peripheral circuit. At this time, if the memory section is covered with an interlayer insulating film, , Metal film,
Since the deterioration of the characteristics of the metal oxide film can be avoided,
No failure occurs.

Also, in this embodiment, as in the first embodiment, a Ta ₂ O ₅ film, a CeO ₂ film, a ZrO ₂ film,
It is also possible to use a high dielectric constant film such as an MgO film or a ferroelectric film.

Also, in the present embodiment, similarly to the first embodiment, the control gate electrode 15 may be formed of a single-layer metal film.

(Third Embodiment) FIGS. 3A to 3I
FIG. 14 is a cross-sectional view illustrating a manufacturing process of the memory cell transistor of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

First, in the step shown in FIG. 3A, a 9 nm-thick silicon oxide film 12x is formed on a Si substrate 11 made of P-type silicon by pyro-oxidation, and then a phosphorus-doped thickness of about 200 nm is formed. Is formed, and the first polysilicon film is patterned to form a floating gate electrode 13 having a gate length of about 0.4 μm.

Next, in the step shown in FIG. 3B, a CVD silicon oxide film 21x is deposited on the substrate,
The side and top surfaces of the floating gate electrode 13 are covered with the silicon oxide film 21x.

Next, in the step shown in FIG.
Using the gate electrode 13 as a mask, phosphorus ions
(P +) with an acceleration energy of 40 keV and a dose of 2 ×
10 ^Fifteencm^-2And the floating gate in the Si substrate 11 is implanted.
In the regions located on both sides of the gate electrode 13, an N-type source
An entry layer 18x and a drain injection layer 19x are formed. this
At this time, the CVD silicon oxide film 21x is used as an injection protection film.
Function. That is, the edge of the lower end of the floating gate electrode 13
Near the gate, the implanted ions penetrate the floating gate electrode 13.
Damage the gate insulating film (tunnel oxide film)
This is to suppress the occurrence of the problem. In addition, the floating gate electrode 13
Polysilicon film may cause channeling
Implanted ions penetrate the entire floating gate electrode 13
Damage the gate insulating film (tunnel oxide film)
In some cases, CVD silicon oxide
This can be suppressed by the film 21x.

Next, in the step shown in FIG. 3D, the Si substrate 11 is subjected to a heat treatment at 850 ° C. for 45 minutes in an oxygen atmosphere.
Source injection layer 18x and drain injection layer 1 formed in
Activate and diffuse 9x phosphorus to form source diffusion layer 18
And a drain diffusion layer 19, and recovers damage due to ion implantation into a portion of the silicon oxide film 12x just below the floating gate electrode 13 (a portion serving as a gate insulating film) to improve the reliability as an insulating film. Let it.
At this time, the region near the upper surface and the side surface of the floating gate electrode 13 is oxidized and the floating gate electrode 1 on the Si substrate 11 is oxidized.
The silicon oxide film 12x on the surface of the portion located on the side of 3
Is formed to increase the thickness of the silicon oxide film 16x. In addition, a gate bird's beak is formed below the lower edge of the floating gate electrode 13 by this process.
However, the floating gate electrode 1 of the silicon oxide film 12x
The portion which is covered by 3 and whose thickness does not change is a gate insulating film 12 (tunnel oxide film). In addition, instead of the heat treatment in an oxygen atmosphere, 850 ° C.
Annealing for 60 minutes allows the Si substrate 1
The activation and diffusion of phosphorus in the source injection layer 18x and the drain injection layer 19x formed in Step 1 may be performed.

Next, in the step shown in FIG. 3E, after depositing a silicon oxide film having a thickness of about 200 nm on the substrate,
In the step shown in FIG. 3F, the upper surface of the substrate is flattened by performing CMP (chemical mechanical polishing) until the thickness of the floating gate electrode 13 becomes 150 nm. Thus, an interlayer insulating film 22 is formed around the floating gate electrode. Note that, instead of the CMP, the planarization may be performed by an etch-back method using a photoresist film.

Next, in a step shown in FIG. 3G, an alumina (A) which is a metal oxide film having a thickness of about 70 nm is formed on the substrate.
l ₂ O ₃ ) A film 14 is deposited. At this time, when the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, an alumina film 14 serving as a gate insulating film of the MIS transistor is formed on the substrate.

Next, in a step shown in FIG. 3H, a polymetal film 15x, which is a laminated film of a phosphorus-doped second polysilicon film and a tungsten film, is deposited on the substrate. By patterning the laminated film in the step shown in FIG. 1, a control gate electrode 15 is formed on the floating gate electrode 13 with the alumina film 14 interposed therebetween. The portion of the alumina film 14 sandwiched between the floating gate electrode 13 and the control gate electrode 15 is the inter-electrode insulating film 1.
4a, and the other part of the alumina film 14 functions as a protective film 14b. At this time, the MIS of the peripheral circuit section
When the transistor is formed on the common Si substrate 11, the gate electrode is formed by patterning the laminated film which is a polymetal film also in the peripheral circuit portion, and is sandwiched between the gate electrode and the Si substrate 11 in the alumina film. The portion to be functioned as a gate insulating film.

According to the manufacturing method of this embodiment, FIG.
In the step shown in (d), the impurities implanted in the Si substrate 11 are activated.
Thereafter, there is no need to perform a high-temperature heat treatment. That is, it is not necessary to perform a high-temperature heat treatment after laminating the alumina film 14 or the polymetal film which is a metal oxide film. For example, the temperature for depositing a polysilicon film is about 500 ° C., and the temperature for depositing a tungsten film is 400 ° C.
This is because the temperature is on the order of degrees Celsius, and the characteristics of the metal film and the metal oxide film do not deteriorate at such a temperature.

As a result, a metal oxide film such as alumina having a higher dielectric constant than a silicon oxide film or a silicon nitride film can be used as the inter-electrode insulating film 14a of the memory cell transistor. In the same manner as described above, the area occupied by the memory cells can be reduced and the device characteristics such as the operation speed can be improved. In addition, when the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, the MIS transistor It is possible to realize high performance and miniaturization.

Before the control gate electrode 15 is formed, the periphery of the floating gate electrode 13 is filled with an interlayer insulating film 22 so that the control gate electrode 15 covers the upper surface of the floating gate electrode 13 and the Si substrate 11 Therefore, it is possible to reliably prevent a high electric field from acting on the Si substrate 11 from the control gate electrode 15 as described above.

In the present embodiment, FIG.
In the step shown in (1), the ion implantation is performed in a state where the CVD silicon oxide film 21x as the implantation protection film is formed, so that the penetration of ions at the end of the floating gate electrode 13 and the There is an advantage that deterioration of the insulating characteristics of the gate insulating film 12 due to penetration of ions by channeling to the entire floating gate electrode 13 can be suppressed. Further, since the heat treatment is performed in the step shown in FIG. 3D, the damage of the gate insulating film 12 can be recovered. Furthermore, by performing this heat treatment in an oxidizing atmosphere, a gate bird's beak is formed below the lower edge of the floating gate electrode 13, so that
Floating gate electrode 13 and source / drain diffusion layers 18, 1
There is also an advantage that the pressure resistance between the first and second embodiments can be ensured.

In the case where the MIS transistor of the peripheral circuit portion is formed on the common Si substrate 11, FIG.
After the step shown in (1), a step of activating the implanted impurities is performed in order to form the source / drain diffusion layers of the MIS transistor of the peripheral circuit. At this time, the memory portion is covered with an interlayer insulating film. Therefore, deterioration of the characteristics of the metal film and the metal oxide film can be avoided.

Also in this embodiment, as in the first embodiment, a Ta ₂ O ₅ film, a CeO ₂ film, a ZrO ₂ film,
It is also possible to use a high dielectric constant film such as an MgO film or a ferroelectric film.

Also, in the present embodiment, the control gate electrode 15 may be formed of a single-layer metal film, as in the first embodiment.

[0069]

According to the nonvolatile semiconductor memory device or the method of manufacturing the same of the present invention, an inter-electrode insulating film and a control gate electrode are provided after activation of a source / drain diffusion layer of a memory cell transistor having a floating gate structure. As a result, a nonvolatile semiconductor memory device in which high-performance memory cell transistors are arranged can be easily obtained. A memory / CMOS hybrid semiconductor device in which a memory unit having a high-performance memory cell transistor and a CMOS device such as a peripheral circuit unit having a miniaturized and high-performance MIS transistor are mounted on a common substrate Can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing process of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 Si substrate 12 gate insulating film 12 x silicon oxide film 13 floating gate electrode 14 alumina film 14 a interelectrode insulating film 14 b protective film 15 control gate electrode 15 x polymetal film 16 covering oxide film 16 x silicon oxide film 18 source diffusion layer 18 x source injection layer 19 Drain diffusion layer 19x Drain injection layer 20 Side wall spacer 21 L-shaped side wall 21x CVD silicon oxide film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (12)

[Claims] A step of forming a floating gate electrode on a semiconductor region of a substrate via a gate insulating film; and (a) implanting impurity ions into regions of the semiconductor region located on both sides of the floating gate electrode. (B) forming a source / drain injection layer, and after the step (b), performing a heat treatment for activating the impurities introduced into the source / drain injection layer,
A step (c) of forming a source / drain diffusion layer; a step (d) of forming an interelectrode insulating film covering at least an upper surface of the floating gate electrode after the step (c); (E) forming a control gate electrode facing the floating gate electrode with the interposition therebetween. 2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step (c), the heat treatment is performed in an oxidizing atmosphere. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein after the step (a) and before the step (b),
A method for manufacturing a nonvolatile semiconductor memory device, further comprising a step of forming a protective insulating film so as to cover the floating gate electrode. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an insulating film is formed on the substrate after the step (b) and before the step (d). Forming a sidewall spacer on a side surface of the floating gate electrode by performing anisotropic etching after depositing the non-volatile semiconductor memory device. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein an insulating film is formed on the substrate after the step (b) and before the step (d). A method of manufacturing a nonvolatile semiconductor memory device, further comprising a step of forming an interlayer insulating film filling the periphery of the floating gate electrode by performing a flattening process after depositing the semiconductor device. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step (d), a metal oxide film is formed as the inter-electrode insulating film. A method for manufacturing a nonvolatile semiconductor memory device, characterized by: 7. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step (e), the control gate electrode is formed of a conductive film including at least one metal film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 8. A substrate having a semiconductor region, a floating gate electrode provided on the semiconductor region via a gate insulating film, and provided in regions of the semiconductor region located on both sides of the floating gate electrode. A source / drain diffusion layer, a sidewall spacer provided on a side surface of the floating gate electrode, and a straddle provided over the entire upper surface of the floating gate electrode and at least a part of the sidewall spacer; A non-volatile semiconductor memory device comprising: a control gate electrode capacitively coupled to the semiconductor device; and an inter-electrode insulating film interposed between the floating gate electrode and the control gate electrode. 9. A substrate having a semiconductor region, a floating gate electrode provided on the semiconductor region via a gate insulating film, and a floating gate electrode provided in a region of the semiconductor region located on both sides of the floating gate electrode. A source / drain diffusion layer, an interlayer insulating film that fills the periphery of the floating gate electrode, and is provided across the entire upper surface of the floating gate electrode and at least a part of the interlayer insulating film, and is capacitively coupled to the floating gate electrode. A non-volatile semiconductor memory device comprising: a control gate electrode to be formed; and an inter-electrode insulating film interposed between the floating gate electrode and the control gate electrode. 10. The nonvolatile semiconductor memory device according to claim 8, wherein said inter-electrode insulating film is made of a metal oxide. 11. The nonvolatile semiconductor memory device according to claim 10, wherein said inter-electrode insulating film is formed of an Al ₂ O ₃ film, a Ta ₂ O ₅ film,
A nonvolatile semiconductor memory device comprising at least one of an eO ₂ film, a ZrO ₂ film, a MgO film, and a ferroelectric film. 12. The nonvolatile semiconductor memory device according to claim 8, wherein said control gate electrode is formed of a conductor film including at least one metal film. Nonvolatile semiconductor memory device.