JP2001202285A - Microprocessor, and its program instruction and data storing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the increase of a software/hardware scale by improving the flexibility of the using form of the memory system of a Harvard architecture type microprocessor. SOLUTION: A memory part 10 is provided with RAMs 13a to 13d of 1 KB storing and holding a program or data, bus switching devices 11a to 11d for selectively connecting the RAMs 13a to 13d to one of a bus 2 for program fetch and a bus 3 for data access respectively in response to each supply of bus selection signals BSa to BSd, and a bus switching register 14 for outputting the signals BSa to BSd corresponding to a bus switching value set from a CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and a method for storing program instructions and data, and more particularly to a microprocessor using a Harvard architecture and a method for storing program instructions and data.

[0002]

2. Description of the Related Art Generally, a microprocessor uses one of two types of well-known architectures, that is, a von Neumann architecture and a Harvard architecture, for interfacing with a central processing unit (hereinafter, CPU) and a memory system. The memory that interfaces to the CPU is:
It may be integrated on the same chip as the CPU or external to the CPU chip. In the von Neumann architecture, the CPU is connected to a single memory system that holds both program instructions and data by one bus interface. Therefore, at any time, only one program instruction code or one data is transferred to the CPU, and neither is transferred at the same time.

On the other hand, the Harvard architecture has a dedicated bus interface for each of the two memories so that the program instructions and data held in separate (ie, two) memories can be simultaneously accessed. . Therefore, the processing speed of the CPU can be improved by simultaneously accessing the program instruction and the data. In other words, the microprocessor using the Harvard architecture can execute the same processing as that performed by the microprocessor using the von Neumann architecture in a smaller number of operation (such as bus access) cycles, and can improve the processing speed compared to the latter.

[0004] Here, a memory holding program instructions is called a program memory, and a memory holding data is called a data memory. As these memories, any of a nonvolatile memory such as a read-only memory (hereinafter referred to as ROM) or a memory which can be read and written at any time (random access memory: hereinafter referred to as RAM) is used depending on the contents of a program or data. For convenience, in the following description, a RAM will be used as a program memory and a data memory, and these will be referred to as a program RAM and a RAM.
And a data RAM.

In a conventional Harvard architecture microprocessor, the capacities of a program RAM and a data RAM are predetermined, and when these are used for other purposes, the speed is reduced. Further, when a cache memory is used, a memory for holding a comparison address is required, and the memory capacity per unit area has been reduced.

FIG. 8 is a block diagram showing an example of a first conventional microprocessor using the Harvard architecture.
Referring to FIG. 1, a conventional microprocessor 100 shown in FIG. 1 employs a Harvard architecture and employs a program fetch bus 102 and a data access bus 103.
And a program RAM which is connected to a program fetch bus 102 and which basically holds programs and can store data in a surplus area.
105, a data RAM 106 connected to the data access bus 103 and capable of storing data and storing programs in a surplus area, and an internal bus 10 of the CPU 101.
A bus controller 107 connected to the general-purpose bus 4 for performing data transfer with the general-purpose bus 8 and controlling the general-purpose bus 8
And a CP connected to a general-purpose bus 8 provided outside the chip.
The external memory 9 stores programs and data to be executed by the U101.

In the above configuration, the CPU 101 can perform a program fetch from the program RAM 105 at high speed, but access to data stored in a surplus area of the program RAM 105 is slow for a reason described later. Further, the CPU 101 can operate the data RAM 106 at high speed.
However, the program fetch for the program stored in the surplus area of the data RAM 106 is slow for the same reason as described above.

However, the first conventional microprocessor has the following problems.

The first problem is that the data access speed is reduced when the surplus area of the program RAM is used as the data RAM, and the program fetch speed is reduced when the surplus area of the data RAM is used as the program RAM. That is.

The reason for this is that when the CPU 101 accesses data in a surplus area of the program RAM, the CPU 101 connects the program fetch bus 102 and the data access bus 103 inside the CPU 101 in addition to the program fetch bus 102. When accessing the program RAM 105 via a bus bridge (not shown) and fetching a program in a surplus area of the data RAM, the data RAM 10 is accessed via the bus bridge in addition to the data access bus 103.
6 for program fetch.

A second problem is that, when the microprocessor requires the highest processing speed, the memory cannot be used effectively.

The reason for this is that, in order to obtain the highest processing speed, it is necessary to arrange the program in the program RAM 105 and the data in the data RAM 106, respectively, because of the first problem. This is because even if there is a surplus in the area, it cannot be used for the other purpose.

FIG. 9 shows an example of a required memory capacity of a program RAM and a data RAM when a plurality of programs A and B having different program sizes and data sizes are switched and executed. Capacity is 2KB, data RAM10
The capacity of 6 requires 3 KB each.

However, while the program A is being executed, the data RAM 106 uses the entire capacity thereof, but the program RAM 105 has a surplus of 1 KB.
On the other hand, while the program B is being executed, the program R
The AM 105 uses the entire capacity, but the data R
The AM 106 has a surplus of 2 KB.

Japanese Patent Application Laid-Open No. 8-63354 discloses a solution to the problems of the first conventional microprocessor as described above, and an improvement in the flexibility of use of a microprocessor using a Harvard architecture in a memory system. 1) The conventional second microprocessor described in 1)
An arbitration unit for arbitration and control of the right to use the bus is provided between the program fetch unit and the data read / write unit of the CPU and the two buses respectively interfacing the two memories constituting the memory system. In accordance with the operation situation, a control process for determining which bus should be used for a given instruction fetch or data read and write request is executed.

However, the conventional arbitration unit of the second microprocessor includes two bus controllers dedicated to two buses and a process control device (CPU) dedicated to the process control, and is a large-scale software / hardware. It is something.

[0017]

When the CPU accesses data in a surplus area of the program RAM, the first conventional microprocessor described above includes a bus bridge for connecting buses in addition to a bus for program fetch. When accessing the program RAM via the data and fetching the program in the surplus area of the data RAM,
Since the program fetch is performed from the data RAM via the bus bridge in addition to the data access bus, the data access speed is reduced when a surplus area of the program RAM is used as the data RAM.
When the surplus area of M is used as the program RAM, there is a disadvantage that the program fetch speed is reduced.

Due to the above-mentioned drawbacks, in order to obtain the highest performance of the processing speed, the program must be executed by the program RA.
In M, it is essential to arrange data in the data RAM, and even if each memory area has a surplus, it cannot be used for the other purpose. There was a disadvantage that it could not be used.

The second conventional microprocessor which solves the above-mentioned drawbacks and improves the flexibility of the use form of the microprocessor using the Harvard architecture in the memory system is a arbiter for arbitration of the right to use the bus, which is an important component thereof. An arbitration unit for control includes two bus controllers dedicated to two buses and a process control device (CPU) dedicated to the process control, and has a drawback that the software / hardware becomes large-scale.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks, to improve the flexibility of use of a Harvard architecture in a memory system of a microprocessor, and to minimize an increase in software / hardware scale and its microprocessor. An object of the present invention is to provide a method for storing program instructions and data.

[0021]

A microprocessor according to the present invention controls a program fetch bus, a data access bus, and an internal bus independently and simultaneously of program instructions and data separately stored in a memory unit. In a microprocessor including a CPU adopting a Harvard architecture that enables simultaneous access to a program instruction and the data, the memory unit includes N (N is an integer of 3 or more), each of which has a predetermined capacity for storing and holding a program or data. A RAM and RAM switching means for selectively connecting each of the N RAMs individually to one of the program fetch bus and the data access bus, wherein the RAM switching means is connected to the program fetch bus. The RAM is connected to the program instruction by the data access bus. The square of the RAM is characterized in that the optimum setting the volume ratio of the memory for storing each of the program instructions and data by storing the data, respectively.

A bus switching register connected to the internal bus for outputting N bus selection signals corresponding to a bus switching value set by the CPU via the internal bus; N bus switches connected to the program fetch bus and the data access bus, respectively, for selecting one of the program fetch bus and the data access bus according to each level of the bus selection signal; The memory may include N memory buses for connecting each of the bus switches and each of the RAMs.

A microcomputer connected to the internal bus, for transferring data between the internal bus and the general-purpose bus, and controlling the general-purpose bus; An external memory connected to a bus and external to the chip and storing the program instructions and data to be executed by the CPU may be provided.

The method of storing program instructions and data of the microprocessor according to the present invention is a method of storing and holding a program or data, each having a fixed capacity of N (N is an integer of 3 or more).
A program fetch bus, a data access bus and an internal bus independently and simultaneously controlling program instructions and data separately stored in a memory unit having a plurality of RAMs, thereby enabling the program instructions and the data to be simultaneously accessed. In a method of storing program instructions and data in the memory unit when switching and executing a plurality of programs having different program sizes and data sizes of a microprocessor including a CPU that employs a Harvard architecture, the N RAMs include: The program fetch bus is connected to a number of the RAMs satisfying a memory capacity corresponding to a program size of each of the plurality of programs sequentially according to an execution order of the plurality of programs, and the number of the RAMs is set as a program storage memory. Program storage memo A data access bus is connected to a RAM other than the RAM set as the data storage memory and the data storage memory is set, thereby optimally setting a capacity ratio of the memory for storing the program instruction and the data. is there.

Further, the plurality of programs are a first program and a second program having different program sizes and data sizes, and the data access bus is connected to all of the N RAMs to store the data. Connecting the program fetch bus to a first number of the RAMs so as to satisfy a first step which is an initial setting process for setting for storage and a memory capacity corresponding to a program size of the first program; A second step of setting the first program to be stored, a third step of executing the first program, and after the completion of the first program, access to all of the N RAMs for the data access. A fourth step of connecting a bus to set the data to be stored, and a method corresponding to a program size of the second program. A fifth step of connecting the program fetch bus to the second number of the RAMs so as to satisfy the storage capacity and setting the second program to be stored, and a sixth step of executing the second program May be provided.

Further, the plurality of programs are a first program which is different in program size and data size and is always held in the memory unit, and a second program and a third program which are loaded as needed. N
A first step which is an initial setting process for connecting the data access bus to all of the RAMs and setting the data to be stored, and satisfying a memory capacity corresponding to a program size of the first program. The program fetch bus is connected to a first number of the RAMs to store the first program, and a second number is set so as to satisfy a memory capacity corresponding to a program size of the second program.
A second step of connecting the program fetch bus to the number of the RAMs and setting each to store the second program; a third step of executing the first program; A fourth step of executing the second program after the end of the program, and the N RAMs after the end of the second program.
A fifth step of connecting the data access bus to all of the above and setting the data to be stored, and a first number of the RAMs satisfying a memory capacity corresponding to a program size of the first program. Connecting the program fetch bus to the third number of the RAMs to connect the program fetch bus, store the first program, and satisfy a memory capacity corresponding to a program size of the third program; A sixth step of setting each to store a third program, a seventh step of executing the first program, and an eighth step of executing the third program after the end of the first program Steps may be included.

[0027]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The microprocessor according to the present embodiment, when switching and executing a plurality of programs including a program having a large program size and a small data size and a program having a small program size and a large data size, for example, A program instruction code (hereinafter, simply referred to as a program) and data of a program are loaded into a plurality of limited-capacity readable / writable memories (random access memory: hereinafter, referred to as a RAM), and the program size and data size of a program to be executed are adjusted. By selecting whether to connect the RAM to the program fetch bus or the data access bus, the program R can be adjusted according to the operation state of the program.
The present invention is characterized in that the capacity ratio between the AM and the data RAM is changed, thereby effectively utilizing a limited capacity memory without impairing the high speed of the Harvard architecture.

Next, referring to FIG. 1 which shows a block diagram of an embodiment of the present invention, the microprocessor of this embodiment shown in FIG. 1 employs a Harvard architecture and employs a program fetch bus 2 and a data access bus. 3
CPU 1 which has an internal bus 4 and can control each of these buses independently and simultaneously; the above-mentioned program fetch bus 2 which can perform a high-speed program fetch from a memory unit; Of the data access bus 3, which can perform high-speed data transfer, the internal bus 4, which is a bus for connecting built-in peripheral blocks, and the internal bus 4 connected to the internal bus 4 and a general-purpose bus 8 described later. A bus controller 7 for transferring data between and controlling the general-purpose bus 8, a general-purpose bus 8 outside the chip, and an external memory 9 connected to the general-purpose bus 8 and storing program instructions and data to be executed by the CPU 1. And a memory unit 10 having a plurality of RAMs for storing and holding programs or data, in this embodiment, four RAMs as described later. Provided.

The memory unit 10 has a fixed capacity, for example, a 1 KB RAM for storing and holding a program or data.
13a to 13d, a bus switching register 14 connected to the internal bus 4 and outputting bus selection signals BSa to BSd corresponding to a bus switching value set from the CPU 1 via the internal bus 4, and a bus for program fetch, respectively. 2 and a bus select signal BSa connected to the data access bus 3
Bus selectors 11a to 11d for selecting one of the program fetch bus 2 and the data access bus 3 in accordance with each level of.
1d and memory buses 12A to 12d respectively connecting the RAMs 13a to 13d.

The external memory 9 has a CPU
1 and programs to be loaded and used in the RAMs 13a to 13d.

Among the components of the present embodiment, the bus switching units 11a to 11d of the memory unit 10 and the bus switching register 1
4 is well known by those skilled in the art, and has no direct relation to the content of the invention, so that the description of its internal configuration is omitted.

Next, referring to FIG. 1 and FIG. 2 which is a flowchart showing the processing of the first embodiment of this embodiment, a method of storing program instructions and data of a microprocessor which is the operation of this embodiment will be described. Then, first, in the present embodiment, two programs A and B having the same program size and data size as the conventional one are switched and executed, and these programs A and B are loaded into the RAMs 13a to 13d of the memory unit 10. To use. Referring also to FIG. 3, which schematically shows the memory capacity required when executing the program of this embodiment, in this example, the program A has a program size of 1 KB, a data size of 3 KB, and a program B. Has a program size of 2 KB and a data size of 1 KB.

First, the CPU 1 executes a program stored in the external memory 9 after power is turned on. When the program operation starts, the CPU 1 and the bus switch register 14 are initialized (step S1). The initial setting values set in this process are stored in the RAMs 13 a to 13 of the memory unit 10.
All of d are set for data storage (table T1).

Next, the program A is loaded from the external memory 9 to the RAM 13a (step S2), the bus switching register 14 is set, and the RAM 13a is connected to the program fetch bus 2 (step S3). The setting contents by this processing are such that the RAMs 13a and 13b are used for storing programs and the RAMs 13c and 13d are used for storing data (table T2).

In this state, since the program A loaded in the RAM 13a becomes executable, the program branches to the start address of the program A and executes the program A (step S4).

After completing the execution of the program A, the CPU 1
The process proceeds to step S5. Here, program B
, The bus switching register 14 is set, and R
The AMs 13a to 13d are connected to the data access bus 3 (Step S5). The setting contents by this processing are RA
All of M13a to M13d are used for storing data (table T3).

Further, the RAM 13a,
13b, the program B is loaded (step S6), the bus switching register 14 is set, and the RAMs 13a and 13b are connected to the program fetch bus 2 (step S6).
7). The setting contents as a result of this processing are stored in the RAMs 13a to 13a.
Let c be for storing programs and the RAM 13d for storing data (table T4).

In this state, since the program B loaded in the RAMs 13a and 13b becomes executable, the program branches to the head address of the program B and executes the program B (step S8).

In the operation of this embodiment, a timing chart shows signal waveforms focusing on the state of the bus selection signal of the memory section 10 and the state of the memory bus (only the bus selection signal BSa and the memory bus 12a are shown here for convenience of explanation). Referring to FIG. 4, first, after power is turned on, bus selection signals BSa to BSd are set to L level by CPU 1 and memory buses 12a of corresponding RAMs 13a to 13d are set.
To 12d are connected to the data access bus 3.

In this state, the CPU 1 stores the program A in the RA
M13a stores program A data in RAMs 13b-1
3d, the bus selection signal BSa is set to the H level after the end of the loading, and the memory bus 12a is connected to the program fetch bus 2 to execute the program A. In this state, the memory buses 12b to 12d of the RAMs 13b to 13d are connected to the data access bus 3, and the CPU 1 performs data access to the RAMs 13b to 13d necessary for executing the program A.

After the program A ends and returns to the main program, the bus selection signals BSa to BSd are set to L level by the CPU 1 and the memory buses 12a to 12d of the RAMs 13a to 13d are connected to the data access bus 3. In this state, the CPU 1 stores the program B in the RAM 13
a and 13b are loaded with data for the program B into the RAM 13c, respectively.
Sa and BSb are set to the H level, and the memory buses 12a,
12b is connected to the program fetch bus 2 to execute the program B. In this state, the RAM 13c memory bus 12c is connected to the data access bus 3, and
The CPU 1 accesses data necessary for executing the program B to the RAM 13c.

Next, a second example of this embodiment will be described.

In this embodiment, three programs C, D and E having different program sizes and data sizes are switched and executed.
Are stored in the RAMs 13a to 13d so that they can be executed at all times, and one of the other programs D and E is stored in the RAMs 13a to 13d together with the program C so that they can be switched immediately and executed as needed. That is, any set of the programs C and D and the programs C and E is always loaded and used in the RAMs 13a to 13d.

Referring also to FIG. 5, which schematically shows the memory capacity required when executing the program of the present embodiment, in this example, the programs C and D each have a program size of 1 KB and a data size of 1 KB. Is 2KB in total
It is. Program E has a program size of 2
The KB and the data size are 1 KB together with the program C. Therefore, the required memory capacity is 4 KB in total.

Next, FIGS. 1 and 5 and the second embodiment of the present invention will be described.
A method of storing program instructions and data of a microprocessor, which is an operation of the present embodiment, will be described with reference to FIG.
After turning on the power, the PU 1 executes a program stored in the external memory 9. When the program operation starts, CP
The U1 and the bus switching register 14 and the system are initialized (step S21). The initial setting value set in this process sets all of the RAMs 13a to 13d of the memory unit 10 for data storage (table T21).

Next, the program C is loaded from the external memory 9 to the RAM 13a (step S22), and the R
Load the program D into the AM 13b (step S2
3), the bus switching register 14 is set and the RAM 13a,
13b is connected to the program fetch bus 2 (step S24). The setting contents by this processing are stored in the RAM 13
a, 13b for storing programs, RAM 13c, 13d
For storing data (table T22).

In this state, since the programs C and D loaded in the RAMs 13a and 13b become executable, the program branches to the head address of the program C and executes the program C (step S25). Further, after the execution of the program C is completed, the program branches to the head address of the program D and executes the program D (step S26).

After completing the execution of the program D, the CPU 1
The process proceeds to step S27. Here, in order to load the program E, the bus switching register 14 of the memory unit 10 is set, and the RAMs 13a, 13b, 13c, and 13d are set.
Is connected to the data access bus 3 (step S2).
7). The setting contents by this processing are stored in the RAMs 13a to 13a.
All of d are used for storing data (table T23).

Further, the RAM 13b,
13c to load the program E (step S28),
By setting the bus switching register 14, the RAM 13a, 13
b, 13c are connected to the program fetch bus 2 (step S29). The result of this process is
M13a to 13c are used for storing programs, and the RAM 13d is used for storing data (table T24).

In this state, the RAMs 13a, 13b, 13c
Since the programs C and E loaded in the program C become executable, the program branches to the start address of the program C and executes the program C (step S30). Further program C
Is executed, the program branches to the start address of the program E,
The program E is executed (Step S31).

FIG. 7 is a timing chart showing signal waveforms focusing on the states of the bus selection signal and the memory bus (only the bus selection signal BSa and the memory bus 12a are shown here for convenience of explanation) in the operation of the present embodiment. Then, first, after the power is turned on, the bus selection signals BSa to BSd
Is set to L level by the CPU 1 and the corresponding RAM
Each of the memory buses 12a to 12d of the RAMs 13a to 13d is connected to the data access bus 3.

In this state, the CPU 1 loads the programs C and D into the RAMs 13a and 13b respectively, sets the bus selection signals BSa and BSb to H level after the loading is completed, and sets the memory buses 12a and 12b to the program fetch bus. 2 and the program C is executed. In this state, the memory buses 12c, 1 of the RAMs 13c, 13d
2d is connected to the data access bus 3, and CP
U1 accesses the RAMs 13c and 13d with data necessary for executing the program C.

After the execution of the program C is completed, the program D is executed. At this time, the CPU 1
Data access necessary for execution of the program D is performed on 13d.

After the program D is completed and the program returns to the main program, the bus selection signals BSa to BSd of the memory section 10
Are set to L level by the CPU 1 and the RAMs 13a to 13a
The 13d memory buses 12a to 12d are connected to the data access bus 3. In this state, the CPU 1 loads the program E into the RAMs 13b and 13c, sets the bus selection signal BSa to H level after this loading is completed, connects the memory bus 12a to the program fetch bus 2, and executes the program C. In this state, the memory bus 12d of the RAM 13d is connected to the data access bus 3, and the CPU 1 accesses the RAM 13d with data necessary for executing the program C.

After the execution of the program C, the bus selection signals BSb and BSc are set to the H level, and the memory buses 12b and 12c are connected to the program fetch bus 2 to execute the program E. The CPU 1 has a RAM 13d
Performs data access necessary for execution of the program E.

As described above, in the microprocessor of the present invention, the CPU adopts the Harvard architecture, uses a plurality of fixed-capacity RAMs as the program memory and the data memory, and sets the bus switching register according to the program. Thereby, any of the plurality of RAMs can be set as a program memory or a data memory. In this way, since the program memory capacity and the data memory capacity can be managed by software, the optimal capacity ratio can be set for each program,
In addition, the feature of the Harvard architecture that a program can be executed at high speed can be maintained.

That is, a first effect of the present invention is that a microprocessor that loads programs of various program sizes and data sizes into a limited-capacity RAM by software and executes the programs according to the contents of the programs. Since the capacity ratio between the RAM and the data RAM can be varied, a limited capacity memory can be used effectively.

The reason is that each of the plurality of RAMs can be connected to either the program fetch bus or the data access bus, and if the program size is small and the required memory capacity is small, the program size can be reduced. A surplus RAM other than the number of RAMs corresponding to the capacity is used for data. Conversely, if the required memory capacity of data is small, the number of RAMs corresponding to the data size is used.
This is because a surplus RAM other than the above can be used for the program.

The second effect is that while obtaining the first effect,
That is, the execution speed of the program does not decrease.

The reason is that by switching the bus connected to the RAM, the program can be executed only via the program fetch bus, and the data can be accessed only via the data access bus. This is because it becomes possible.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, although the case where the number of RAMs is four has been described, the number of RAMs is not limited.

The case where the capacity of each RAM is 1 KB has been described, but the capacity of each RAM is not limited.

The program executed by the CPU 1 immediately after turning on the power may be stored in a memory connected to another bus.

Further, the program size and the data size need not be limited to those shown in the embodiments, and can be freely set without departing from the gist of the present invention.

[0066]

As described above, according to the microprocessor of the present invention and its method of storing program instructions and data, the memory section comprises N RAMs each having a fixed capacity for storing and holding a program or data; RAM
, Each of which is selectively connected to one of a program fetch bus and a data access bus individually.
Switching means, each of the N RAMs can be connected to either the program fetch bus or the data access bus. If the program size is small and the required memory capacity is small, then The remaining RAM other than the number of RAMs corresponding to the capacity is used for data, and conversely, if the required memory capacity of data is small,
A surplus RAM other than the number of RAMs corresponding to the capacity of the data size can be used for the program.
Since the capacity ratio of M can be changed, there is an effect that a memory having a limited capacity can be used effectively.

By switching the bus connected to the RAM, the program can be executed only via the program fetch bus, and the data can be accessed only via the data access bus. As a result, there is an effect that high performance can be exhibited without lowering the execution speed of the program.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a microprocessor according to the present invention.

FIG. 2 is a flowchart illustrating an example of the operation of the first example in the microprocessor of the present embodiment;

FIG. 3 is an explanatory diagram schematically showing a memory capacity required when executing a program according to the embodiment.

FIG. 4 is a time chart illustrating an example of the operation of the present embodiment.

FIG. 5 is an explanatory diagram schematically showing a memory capacity required for executing a program of a second example in the microprocessor of the present embodiment.

FIG. 6 is a flowchart illustrating an example of the operation of the present embodiment.

FIG. 7 is a time chart showing an example of the operation of the present embodiment.

FIG. 8 is a block diagram illustrating an example of a conventional first microprocessor.

FIG. 9 shows a program RA in a case where a plurality of programs having different sizes of a program and data are switched and executed.
FIG. 3 is an explanatory diagram showing an example of a required memory capacity of M and a data RAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 101 CPU 2, 102 Bus for program fetch 3, 103 Bus for data access 4, 104 Internal bus 7, 107 Bus controller 8 General-purpose bus 9 External memory 10 Memory unit 11a-11d Bus switcher 12A-12d Memory bus 13a- 13d RAM 14 switching register 20, 100 microprocessor 105 program RAM 106 data RAM

Claims (6)

[Claims] 1. A program fetch bus, a data access bus, and an internal bus for program instructions and data separately stored in a memory unit are simultaneously and independently controlled so that the program instructions and the data can be accessed simultaneously. In a microprocessor including a CPU employing a Harvard architecture, the memory unit includes N (N is an integer of 3 or more) RAMs each storing a program or data and having a fixed capacity.
And RAM switching means for selectively connecting each of the N RAMs individually to one of the program fetch bus and the data access bus. The program instruction is stored in the RAM in which the program instruction is connected to the data access bus, and the data is stored in the RAM, so that the capacity ratio of the memory for storing the program instruction and the data is optimally set. Microprocessor. 2. A bus switching register connected to the internal bus, the RAM switching means outputting N bus selection signals corresponding to a bus switching value set from the CPU via the internal bus; N bus switches connected to the program fetch bus and the data access bus, respectively, for selecting one of the program fetch bus and the data access bus according to each level of the bus selection signal; 2. The microprocessor according to claim 1, further comprising N memory buses respectively connecting each of said bus switches and each of said RAMs. 3. A general-purpose bus external to the chip, a bus controller connected to the internal bus for performing data transfer between the internal bus and the general-purpose bus and controlling the general-purpose bus, and connected to the general-purpose bus. 2. The microprocessor according to claim 1, further comprising: an external memory external to a chip that stores the program instructions executed by the CPU and data. 4. Program instructions and data separately stored in a memory unit having N (N is an integer of 3 or more) RAMs each having a fixed capacity for storing and holding a program or data are stored in a memory section for program fetch and data access. A plurality of programs having different program sizes and data sizes of a microprocessor including a CPU employing a Harvard architecture that controls the bus and the internal bus independently and simultaneously to allow simultaneous access to the program instruction and the data are executed. In the method of storing program instructions and data in the memory unit, the memory capacity corresponding to the program size of each of the plurality of programs is sequentially determined according to the execution order of the plurality of programs among the N RAMs. Satisfying number of R
By connecting the program fetch bus to the AM and setting it as a program storage memory, and connecting a data access bus to a RAM other than the RAM set as the program storage memory and setting it as a data storage memory, A method for storing a program instruction and data of a microprocessor, wherein the ratio of the capacity of each memory for storing the instruction and the data is set optimally. 5. The program according to claim 1, wherein the plurality of programs are a first program and a second program having different program sizes and data sizes, and the data access bus is connected to all of the N RAMs. A first step of an initial setting process for setting for storage, and connecting the program fetch bus to the first number of RAMs so as to satisfy a memory capacity corresponding to a program size of the first program. A second step of setting the first program to be stored; a third step of executing the first program; and after the first program has ended, the data access to all of the N RAMs is performed. A fourth step of connecting a bus and setting the data to be stored; and a memo corresponding to the program size of the second program. A fifth step of connecting the program fetch bus to the second number of RAMs so as to satisfy a capacity and setting the second program to be stored, and a sixth step of executing the second program. 5. The method according to claim 4, further comprising: storing a program instruction and data in the microprocessor. 6. The plurality of programs are a first program which is different in program size and data size and is always stored in the memory unit, and a second program and a third program which are loaded as needed. A first step which is an initial setting process for connecting the data access bus to all of the N RAMs and setting the data to be stored, and satisfying a memory capacity corresponding to a program size of the first program The program fetch bus is connected to a first number of the RAMs to store the first program, and a second number of the RAs are stored so as to satisfy a memory capacity corresponding to a program size of the second program.
A second step of connecting the program fetch bus to M to store the second program, a third step of executing the first program, and after the first program ends A fourth step of executing the second program, and after completion of the second program, connecting the data access bus to all of the N RAMs and setting for storing the data. 5) connecting the program fetch bus to a first number of the RAMs so as to satisfy a memory capacity corresponding to a program size of the first program, storing the first program, and A third number of the RAs is set to satisfy a memory capacity corresponding to a program size of a program.
A sixth step of connecting the program fetch bus to M to store the third program, a seventh step of executing the first program, and after the first program ends The method according to claim 4, further comprising an eighth step of executing the third program.