JP2001203343A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control variations of characteristics in a saturation region of a photodiode. SOLUTION: A solid state imaging device is composed of a first conductivity type semiconductor substrate 1, a second conductivity type well layer 15 on the first conductivity type semiconductor substrate 1, a first semiconductor layer 14 of the first conductivity type at an upper part of the second conductivity type well layer 15, in which a photoelectric conversion element is constituted by the first semiconductor layer 14 and the second conductivity type well layer 15, a second semiconductor layer of the first conductivity type at an upper part of the second conductivity type well layer 15 for constituting a vertical charge transfer path 5, and a first potential barrier layer 14 formed between the second conductivity type well layer 15 and the first conductivity type substrate 1 and having an almost flat barrier height in a depth direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a wide dynamic range, and more particularly, to a variation in photoelectric conversion characteristics in a saturation region of a photodiode included in a pixel in the solid-state imaging device (hereinafter referred to as "saturation unevenness between pixels"). "
Called. The present invention relates to a solid-state imaging device with reduced ()).

[0002]

2. Description of the Related Art FIG. 9 is a schematic plan view of a solid-state imaging device (area sensor) using a CCD system. The solid-state imaging device A includes a plurality of pixels 103 arranged in a row and a column on a two-dimensional plane of the surface of the semiconductor substrate 101.

[0003] The pixel 103 includes a photoelectric conversion element (photodiode) 103a. A plurality of vertical charge transfer paths 105 extend in the vertical direction adjacent to the plurality of photoelectric conversion elements 103a arranged in the column direction in the row direction. A transfer gate 103b is provided between the photoelectric conversion element 103a and the vertical charge transfer path 105.

At one end of the plurality of vertical charge transfer paths 105,
A common horizontal charge transfer path 107 is provided. An output amplifier 111 is provided at one end of the horizontal charge transfer path 107.

FIG. 10 is a sectional view taken along the line XX of FIG. 9 and a potential along the line Xa-Xa of the solid-state imaging device shown in the sectional view.

The solid-state imaging device A includes a p-type semiconductor substrate 101 (n-type semiconductor substrate) doped with n-type impurities.
A p-well layer 115 doped with a type impurity is formed. A pixel isolation layer 117 doped with a high concentration of p-type impurity is formed in the p-well layer 115.

A vertical charge transfer path 105 doped with an n-type impurity between pixel separation layers 117 adjacent in the horizontal direction, and a high-concentration n formed near the vertical charge transfer path 105
The type semiconductor layer 112 is formed. n-type semiconductor layer 112
And p-well layer 115 form photodiode 103a having a pn junction. n-type semiconductor layer 112
A transfer gate 103b is defined between the transfer gate 103b and the n-type semiconductor layer for the vertical charge transfer path 105.

A thin oxide film 121 is formed on p well layer 115. A vertical charge transfer electrode 103c using polycrystalline silicon is formed on the oxide film 121 and on the transfer gate 103b and the n-type semiconductor layer forming the vertical charge transfer path 105.

A light-shielding film 125 having an opening in the photodiode 103a is formed thereon. When the light-shielding film 125 is formed using a conductive material, the light-shielding film 125 is provided after forming the insulating film 124 on the vertical charge transfer electrode 103c.

After forming a flattening film H thereon, a color filter CF and a microlens ML are formed.

In the above-described solid-state imaging device A, the charges accumulated in the photodiode 103a are transferred to the vertical charge transfer path 105 through the transfer gate 103b.

The charges are transferred in the vertical charge transfer path 105 in the vertical direction, and are transferred to the horizontal charge transfer path 107. The charges transferred to the horizontal charge transfer path 107 are output to the output amplifier 111.
Transferred in the direction. A signal voltage corresponding to the charge is amplified by the output amplifier 111 and output to the outside.

[0013]

When strong light enters a photodiode (photoelectric conversion element), signal charges overflow and surplus charges enter surrounding pixels. A so-called blooming phenomenon occurs in which a portion that is not exposed to light swells brightly. If the excess charge leaks into the CCD vertical charge transfer path during transfer of the charge, it spreads in the vertical direction and becomes vertical stripes, deteriorating the image quality.

In order to avoid the above-mentioned phenomenon, a conventional solid-state imaging device using a CCD has a horizontal overflow drain adjacent to a photodiode in a horizontal direction.

By applying a voltage to the horizontal overflow drain, excess charges accumulated in the photodiode are drawn out and discarded.

By the way, when the horizontal overflow drain is provided, the occupation area of the photosensitive portion including the photodiode must be reduced by that much. Recently, a vertical overflow drain structure has been used in accordance with the trend of increasing the number of pixels in a solid-state imaging device.

In the vertical overflow drain structure shown in FIG. 10, excess charges in the photodiode or the vertical charge transfer path are drawn out in the vertical direction (substrate side). In the vertical overflow drain structure, the n-type semiconductor layer 112
Alternatively, a structure similar to that of an n ⁺ pn vertical bipolar transistor is formed along the vertical charge transfer path 105, the p-well layer 115, and the n-type semiconductor substrate 101.

When strong light enters the photodiode 103a having the pn junction formed by the p-well layer 115 and the n-type semiconductor layer 112, the potential of the n-type semiconductor layer 112 rises, and the potential difference of the n ⁺ p junction Becomes smaller. To extract excess charge in the photodiode or the vertical charge transfer path, a reverse biased substrate voltage Vsub is applied between the p-well layer 115 and the n-type semiconductor substrate 101.

P-well layer 115 and n-type semiconductor substrate 101
N-type semiconductor by applying a reverse bias voltage between
The potential of the body substrate 101 decreases, and the p-well layer 11
5 is depleted. Unnecessary excess charge is
N forming a transistor ⁺(The n-type semiconductor layer 111 or
Denotes a vertical charge transfer path 105) -p (p-well layer 115)-
n-type semiconductor through the path of n (n-type semiconductor substrate 101)
It is pulled out to the substrate 101 side.

With the vertical overflow drain structure described above, surplus charges can be drawn out to the substrate side before entering other pixels or transfer electrodes, and the photosensitive portion can be effectively used while suppressing blooming.

However, it has not been possible to control the variation of the photoelectric conversion characteristics in the saturation region of the photodiode of the solid-state imaging device. Therefore, the method has to be used on the premise that there is saturation unevenness between pixels.

FIG. 11 shows the photoelectric conversion characteristics of a plurality of photodiodes formed in the solid-state imaging device A having the above structure.

The horizontal axis indicates the amount of light incident on the photodiode, and the vertical axis indicates the output signal voltage output from the photodiode.

Characteristic lines A1, A2, and A3 indicate the characteristics of three different photodiodes in the same solid-state imaging device.

The photoelectric conversion characteristics of the photodiode are roughly classified into a linear region R1 where the amount of incident light is relatively small and a saturated region R2 where the amount of incident light is large. In the linear region R1, the amount of incident light is substantially proportional to the output signal voltage. The saturation region R2 is a region where the output signal voltage does not increase so much even when the amount of incident light increases and saturates.

In the linear region R1, the characteristics A1, A2 and A3 of each photodiode are almost the same. Saturation region R
2, the characteristics A1, A2, and A3 of each photodiode are significantly different. When the saturated region R2 is used, the characteristics vary among the photodiodes, so that the saturated region R2 is not used.

In a general photodiode, the linear region R1 is a region where the amount of incident light is, for example, 2,000 candela / m ² or less. The saturated region R2 has an incident light amount of, for example, 2,000 candela / m ² to 20,000.
It is an area up to candela / m ² . If only the linear region R1 is used, the dynamic range naturally becomes narrow.

An object of the present invention is to make it possible to use not only a linear region of a photodiode but also a saturation region.
An object of the present invention is to provide a solid-state imaging device having a wide dynamic range.

[0029]

According to one aspect of the present invention, a semiconductor substrate of a first conductivity type and a barrier height formed on the semiconductor substrate of the first conductivity type and having a substantially flat barrier height in a depth direction are provided. A first potential barrier layer, a second conductivity type well layer formed on the first potential barrier layer, and aligned in a column direction and a row direction in a region near a surface in the second conductivity type well layer. Are arranged in a matrix, and the second
A first first conductivity type semiconductor layer forming a photoelectric conversion element together with a conductivity type well layer and a row of the first first conductivity type semiconductor layer aligned in the column direction in the second conductivity type well layer. And a second first conductivity type semiconductor layer forming a vertical charge transfer path for transferring charges accumulated in the photoelectric conversion element.

According to another aspect of the present invention, a first conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate formed on the first conductivity type semiconductor substrate,
A first potential barrier layer having a substantially flat barrier height in a depth direction; a second conductivity type well layer formed on the first potential barrier layer;
A first first-conductivity-type semiconductor layer, which is arranged in a row and a row in a row near the surface in a region near the surface of the first-conductivity-type well layer and forms a photoelectric conversion element together with the second-conductivity-type well layer; A vertical charge transfer path formed in the second conductivity type well layer and adjacent to the first first conductivity type semiconductor layer aligned in the column direction in the row direction and transferring the charge stored in the photoelectric conversion element. And a second first conductivity type semiconductor layer forming the second conductivity type well layer, the impurity concentration of the second conductivity type well layer in the imaging unit including the photoelectric conversion element and the vertical charge transfer path, and the second conductivity type semiconductor layer in a peripheral portion thereof. A solid-state imaging device having a different conductivity type impurity concentration from a well layer is provided.

According to still another aspect of the present invention, a first conductive type semiconductor substrate and a first potential formed on the first conductive type semiconductor substrate and having a substantially flat barrier height in a depth direction. A barrier layer, a well layer of a second conductivity type formed on the first potential barrier layer, and a two-dimensional plane aligned in one direction on a two-dimensional plane in a region near a surface in the well layer of the second conductivity type A plurality of first first elements forming a photoelectric conversion element row together with a plurality of the second conductivity type well layers;
A charge transfer device that is formed in the second conductivity type well layer and is horizontally adjacent to the first first conductivity type semiconductor layer in the second conductivity type well layer and transfers the charge accumulated in the photoelectric conversion element; A solid-state imaging device including a second first conductivity type semiconductor layer forming a path.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The causes of variations in photoelectric conversion characteristics between photodiodes in the saturation region R2 will be considered below.

The inventor of the present application has paid attention to the following three points as causes of the above-mentioned variation.

A) Variation of barrier in pixel separation layer Pixel separation layer 117 formed of a p-type semiconductor (FIG. 1)
If the first barrier formed by (0) is present, electrons accumulated in the n-type semiconductor layer 112 of the photodiode 103a may move to another region beyond the first barrier. When the height of the first barrier varies between the photodiodes 103a, variation occurs in the photoelectric conversion characteristics in the saturation region R2.

By increasing the concentration of the pixel separation layer 117, the barrier height of the first barrier can be made sufficiently high. With such a method, fluctuations in the height of the first barrier can be prevented. It is considered that it is possible to suppress the variation of the photoelectric conversion characteristics between the photodiodes 103a due to the variation.

B) Variation of Barrier in Transfer Gate The height of the second barrier formed by the transfer gate 103b (FIGS. 9 and 10) is
It can be changed by the voltage applied to 03c.

Specifically, when accumulating charges in the photodiode 103a (during exposure), it is necessary to apply a high negative voltage to the vertical charge transfer electrode to sufficiently increase the height of the second barrier. Will be possible. It is considered that such a method can suppress variations in photoelectric conversion characteristics among the photodiodes due to a change in the height of the second barrier.

C) Variation of Barrier in P-Well Barrier The height of the third barrier formed by the p-well layer 115 (FIG. 10) is determined by the concentration of the p-type impurity in the p-well layer.

FIG. 10 shows the potential from the semiconductor substrate 101 to the n-type semiconductor layer 112 when the region of the photodiode 103a is cut in the vertical direction, together with a cross-sectional view.

The n-type semiconductor substrate 101 has a substrate potential Vsub by an electrode (not shown) formed on the back surface of the substrate, for example.
Is set to

The potential for electrons increases in the p-well layer 115 and decreases in the n-type semiconductor layer 112. N-type semiconductor substrate 101 and p-well layer 11
5, and a depletion layer is formed at the interface between the p-well layer 115 and the n-type semiconductor layer 112. The potential height has a peak value Va in the p-well layer.

The p-type impurity concentration in p-well layer 115 cannot be so high. Because p
This is because it is necessary to form the n-type semiconductor layer 112 in order to form the photodiode 103a in the well layer 115.

The barrier height Va greatly depends on the p-type impurity concentration. It depends on the p-type impurity concentration itself and the width of the depletion layer at both of the above-mentioned interfaces associated therewith.

As the p-type impurity concentration itself decreases, the barrier height Va decreases. Further, as the p-type impurity concentration becomes lower, the width of the depletion layer extending into p-well layer 115 becomes larger. The width of the potential ramp increases, and the width of the region with a constant potential at the top of the barrier decreases.
The change in the potential of the n-type semiconductor layer 112 also makes it easy for the potential at the top of the barrier to change.

Therefore, even if there is even a slight variation in the p-type impurity concentration in each photodiode region, the photoelectric conversion characteristics in the saturation region R2 are significantly different.

Further, by implanting p-type impurity ions near the surface of the semiconductor substrate 101 by ion implantation, the p-type impurity concentration is relatively increased near the interface with the n-type semiconductor layer 112 to be formed later. A method of forming the p-well layer 115 is also conceivable. However,
When the p-well layer is formed by ion implantation, the concentration of the p-type impurity has a Gaussian distribution in the depth direction.

Therefore, the height Va of the potential barrier existing in the p-well layer is more likely to vary.

Based on the above considerations, the inventor considered providing a structure for securing a stable potential barrier height Va in the p-well layer.

The solid-state imaging device according to the present embodiment will be described with reference to FIGS.

FIG. 1 shows a solid-state imaging device B using a CCD system.
1 shows a schematic plan view of FIG.

The solid-state imaging device B is a so-called area sensor, and includes a plurality of pixels 3 arranged in a row and a column on a two-dimensional plane of the surface of the semiconductor substrate 1.

The pixel 3 includes a photoelectric conversion element (photodiode) 3a. A plurality of photoelectric conversion elements 3a arranged in a column direction
, A plurality of vertical charge transfer paths 5 extend in the vertical direction. A transfer gate 3b is provided between the photoelectric conversion element 3a and the vertical charge transfer path 5.

At one end of the vertical charge transfer path 5, a horizontal charge transfer path 7 is provided. An output amplifier 11 is provided at one end of the horizontal charge transfer path 7.

In this specification, the solid-state imaging device in which “pixels (photoelectric conversion elements) are arranged in a row direction and a column direction on a two-dimensional plane” means only a simple square matrix arrangement. However, the arrangement also includes a houndstooth arrangement. For example, a first pixel row including a plurality of pixels arranged in a vertical direction at a first pixel pitch, and a shift of half a pixel of the first pixel pitch in the vertical direction with respect to the first pixel row. So-called pixel shift structure including a plurality of pixels arranged in a row and including a second pixel row horizontally adjacent to the first pixel row at a second pixel pitch. It is assumed that the solid-state imaging device also has pixels arranged in rows and columns.

A plurality of pixels (photoelectric conversion elements) having a substantially square shape, two opposite sides extending in the vertical direction, and the other two opposite sides extending in the horizontal direction are formed on a two-dimensional plane. Although the structure described above has been described as an example, it has a substantially square or rhombic shape, two opposing vertices are arranged along an imaginary line extending vertically, and two other opposing vertices are arranged. A structure in which a plurality of pixels (photoelectric conversion elements) in which vertices are arranged along a virtual line extending in the horizontal direction are arranged on a two-dimensional plane, and polygonal pixels including a regular hexagon and a regular octagon (photoelectric conversion elements) May be used on a two-dimensional plane.

FIG. 2 shows a cross-sectional view taken along the line II-II of FIG. 1 and the potential of the solid-state imaging device B shown in the cross-sectional view taken along the line IIa-IIa.

The solid-state imaging device B comprises a semiconductor substrate (n-type semiconductor substrate) 1 doped with an n-type impurity, a p-type semiconductor layer 14 doped with a p-type impurity, and
A p-well layer 15 doped with a type impurity is formed. The impurity concentration of the p-type semiconductor layer 14 is higher than the impurity concentration of the p-well layer 15.

The impurity concentration of the n-type semiconductor substrate 1 is, for example, 1 × 10 ¹⁵ cm ⁻³ .

The impurity concentration of the p-well layer 15 is 10 ¹⁶ c
m ⁻³ , for example, 5 × 10 ¹⁶ cm ⁻³ . The thickness of the p-well layer 15 is, for example, 2 μm.

The impurity concentration of the p-type semiconductor layer 14 is about four times higher than the impurity concentration of the p-well layer 15, and is generally on the order of 10 ¹⁷ cm ⁻³ , for example, 2 × 10 ¹⁷ cm ^−3. It is. The thickness is, for example, 2 μm.

The p-type semiconductor layer 14 is preferably formed with a substantially uniform concentration in the depth direction (thickness direction). In order to form a uniform concentration in the depth direction (thickness direction), it is preferable to epitaxially grow the p-type semiconductor layer 14.

As another method for forming a uniform concentration in the depth direction (thickness direction), there is a multiple ion implantation method.
In the multiple ion implantation method, a p-well layer 15 is first formed, and a p-type impurity (for example, N) is deposited at different acceleration energies so that a substantially uniform p-type impurity layer can be formed in the depth direction. Ions are implanted several times. The concentration profile of the impurity formed by the ion implantation generally shows a substantially Gaussian distribution in the depth (thickness) direction. By using the above multiple ion implantation method, it is possible to form the p-type impurity layer 14 having a substantially uniform concentration distribution along the depth direction.

In the p-well layer 15, a pixel isolation layer 17 doped with a high concentration of p-type impurity is formed.

The pixel separation layers 17, 17 adjacent in the horizontal direction
A vertical charge transfer path 5 doped with an n-type impurity and a high-concentration n-type semiconductor layer 12 formed close to the vertical charge transfer path 5 are formed therebetween. A photodiode 3a having a pn junction is formed by the n-type semiconductor layer 12 and the p-well layer 15. In other words, the vertical charge transfer path 5
And pixel isolation regions are formed outside the n-type semiconductor layer 12. The p-type impurity concentration of the pixel separation layer 17 is, for example, 5 × 10 ¹⁸ cm ⁻³ . The potential barrier height formed between the pixel separation layer 17 and the n-type semiconductor layer 12 is about 1.1 when Si is used as a semiconductor material.
It is about 2 eV.

The n-type semiconductor layer 12 and the n for the vertical charge transfer path 5
A transfer gate 3b is defined between the transfer gate and the mold semiconductor layer.

A thin oxide film 21 is formed on p well layer 15. A vertical charge transfer electrode 3c using polycrystalline silicon is formed on the oxide film 21 and on the transfer gate 3b and the n-type semiconductor layer forming the vertical charge transfer path 5.

On top of this, a light-shielding film 25 having an opening in the photodiode 3a region is formed via an interlayer insulating film 24. After forming the flattening film H thereon, the color filters CF and the microlenses ML are formed.

According to the above structure, a barrier layer (p-type impurity layer 14) having a substantially uniform potential profile along the depth direction is formed between n-type semiconductor substrate 1 and p-well layer 15. You.

FIG. 3 shows a case where Si is used as a material.
4 shows a process for manufacturing the above structure.

In a first step S1, an n-type Si substrate is prepared. The surface of the n-type Si substrate is, for example, HF-H
The treatment is performed using a mixed solution of NO ₃ . The strained layer and the natural oxide film on the surface are removed.

In the second step S2, an n-type Si substrate is placed in an epitaxial growth chamber made of, for example, silica glass. The surface treatment of the n-type Si substrate is performed at 1200 ° C. using a mixed gas of H ₂ gas and HCl gas. The natural oxide film and metal contamination on the surface are removed.

In the third step S3, the p-type semiconductor layer 14 is epitaxially grown. Various methods are known as an epitaxial growth method for a single crystal Si layer.

For example, a thermal decomposition method of monosilane (SiH ₄ ) based on the following reaction formula (1) can be used.

SiH ₄ (g) → Si (c) + 2H ₂ (g) (1) The above reaction is performed, for example, at 1000 ° C. The crystal growth rate is, for example, 0.8 μm / min. The growth rate can be controlled by changing the growth temperature.

As the p-type impurity, for example, B is used. In the reaction based on the above formula (1), B is doped using, for example, diborane (B ₂ H ₆ ).

In the fourth step S4, the p-well layer 15 is epitaxially grown. The same method as that used in step S4 can be used for the epitaxial growth method of the single-crystal Si layer. However, the doping amount of B is reduced. The thickness of the p-well layer 15 is, for example, about 2
μm.

In the fifth step S5, the high concentration p
A pixel isolation region 17 made of a mold semiconductor layer is formed.

The pixel isolation layer 17 made of a high-concentration p-type semiconductor layer is formed by implanting B ions with an acceleration energy of 2 MeV and a dose of 1 × 10 ¹⁶ cm ⁻² .

The pixel separation layer 17 penetrates the p-well layer 15 and is formed at least to a depth that reaches the surface of the p-type semiconductor layer 14.

In practice, the acceleration energy is set to 200 ke
Ion implantation with V and 500 keV is performed in another step. In effect, multiple ion implantation is performed by changing the acceleration energy. A layer that is substantially constant in the depth direction and has a high p-type impurity concentration can be formed from the substrate surface to the p-type semiconductor layer.

The pixel separation layer 17 may be formed by forming a groove reaching at least the surface of the p-type semiconductor layer 14 in the p-well layer 15 and then filling the groove with an insulating film. good.

In step S6, an n-type semiconductor layer is formed by an ion implantation method.

N-type semiconductor layer 12 for photodiode
Is formed, for example, by implanting P ions under the conditions of an acceleration energy of 200 keV and a dose of 5 × 10 ¹⁴ cm ⁻² .

The n-type semiconductor layer 5 for the vertical charge transfer path is formed by, for example, implanting P ions under the conditions of an acceleration energy of 500 keV and a dose of 1 × 10 ¹⁴ cm ⁻² .

After ion implantation, for example, 600 ° C. to 1000
Anneal to activate the implanted ions at a temperature between ° C.

In step S7, oxide film 21 is formed on the surface of p well layer 15. The oxide film 21 is, for example,
It is formed at 1000 ° C. by a thermal oxidation method.

In step S8, a polycrystalline silicon layer for the vertical charge transfer electrode and the horizontal charge transfer electrode (only the polycrystalline silicon layer 3c for the vertical charge transfer electrode is shown in FIG. 2). , Process.

An insulating film is also formed between the first polycrystalline silicon layer (1 poly) and the second polycrystalline silicon layer (2 poly) by a thermal oxidation method or the like.

In step S9, an interlayer insulating film 24 is formed. As the interlayer insulating film 24, for example, an oxide film or a nitride film formed by a sputtering method is used. The thickness of the interlayer insulating film 24 is, for example, 1 μm.

In step S10, the light shielding film 25 is formed of, for example, Al. The light-shielding film 25 has an opening formed in the light receiving portion of the photodiode.

A color filter CF, a micro lens ML, and the like are formed above the opening of the light shielding film 25.

In the above-described solid-state imaging device B, the electric charge accumulated in the photodiode 3a is transferred to the vertical charge transfer path 5 through the transfer gate 3b.

The charges are transferred in the vertical charge transfer path 5 in the vertical direction, and are transferred to the horizontal charge transfer path 7. The charges transferred to the horizontal charge transfer path 7 are transferred to the output amplifier 11. The signal voltage due to the charges is amplified by the output amplifier 11 and output to the outside.

FIG. 2 also shows the potential along the line IIa-IIa from the semiconductor substrate 1 to the n-type semiconductor layer 12 when the region of the photodiode 3a is cut in the vertical direction.

The n-type semiconductor substrate 1 has a low resistivity and is set to the substrate potential Vsub by, for example, an electrode (not shown) formed on the back surface of the substrate.

The potential shape in the depth direction increases in the p-type semiconductor layer 14, and a potential barrier (potential barrier height VB) having a substantially flat potential shape in the depth direction (thickness direction) is formed. .
The “substantially flat potential shape” includes not only a completely flat potential shape but also a case where there is a slight potential gradient. Also, there is a case where there is a slight change in the potential height, such as a case where a potential barrier is formed by a so-called multiple ion implantation method in which ion implantation is performed several times or more by changing acceleration energy. In short, the p-well layer 15
Even if there is some variation in the impurity concentration in the inside, it is sufficient if the impurity concentration is flat so as to hardly affect the saturation voltage.

The potential (V) in the p well 15
a) is lower than the height VB of the p-type semiconductor layer 15. The potential in the n-type semiconductor layer 12 is p
The potential becomes lower than the potential (Va) in the well 15. A depletion layer is formed near the interface between the n-type semiconductor substrate 1 and the p-type semiconductor layer 14, near the interface between the p-type semiconductor layer 14 and the p-well 15, and near the interface between the p-well 15 and the n-type semiconductor layer 12. .

The region that has the highest potential between the n-type semiconductor layer 12 and the n-type semiconductor substrate 1, that is, the p-type, has the greatest effect on the amount of charge stored in the n-type semiconductor layer 12. This is a region where the semiconductor layer 14 exists.

Since the impurity concentration itself in the p-type semiconductor layer 14 is high, the barrier height VB increases. According to the above doping concentration example, the potential Va is about 1.0
2 eV and potential VB are about 1.06 eV.
The highest potential height compared to the structure shown in FIG.
It increases by about 0.04 eV.

In addition, in the p-type semiconductor layer 14,
The height VB of the potential barrier is substantially uniform in the thickness direction. Further, the width of the depletion layer at the interface between the p-type semiconductor layer 14 and the p-well layer 15 is reduced. Barrier height V
Since the region where B is uniform in the depth direction is wide and the depletion layer is narrow, the potential hardly fluctuates with respect to the height VB of the potential barrier.

Therefore, in each photodiode region, even if there is a slight variation in the p-type impurity concentration in the p-well layer 15, that is, the potential Va of the p-well layer, it is accumulated in the n-type semiconductor layer 12. With respect to the charge amount, the potential Vb of the p-type semiconductor layer 14 becomes dominant.

The impurity concentration of the pixel isolation layer 17 is higher than the impurity concentration of the p-type semiconductor layer 14.

The barrier height (first barrier) between the n-type semiconductor layer 12 and the p-well layer 15 is also sufficiently high.
Therefore, it is possible to suppress the variation in the photoelectric conversion characteristics between the photodiodes 3a due to the variation in the height of the first barrier.

In addition, a high negative voltage is applied to the vertical charge transfer electrode 3c when charges are accumulated in the photodiode 3a (during exposure). The height of the barrier (second barrier) formed by the transfer gate 3b also becomes sufficiently high. Therefore, it is possible to suppress the variation in the photoelectric conversion characteristics between the photodiodes 3a due to the variation in the height of the second barrier.

FIG. 4 shows the photoelectric conversion characteristics A1, A2, and A3 of the photodiode 3a formed in the solid-state imaging device.
A3 is shown.

In the saturation region R2 as well as in the linear region R1, there is almost no variation in the photoelectric conversion characteristics between the photodiodes.

Therefore, a uniform output signal voltage can be obtained between the photodiodes over a wide incident light amount from the linear region R1 to the saturation region R2, and the dynamic range can be expanded.

In addition, separately from the p-well layer, a high concentration of p
By inserting the type semiconductor layer, the height of the potential barrier can be increased as compared with the conventional structure.

Therefore, the width of the linear region R1 itself can be increased when compared with the light receiving area of the same photodiode.

As described above, in the solid-state imaging device according to the first embodiment, the photoelectric conversion characteristics in the saturation region R2 as well as in the linear region are almost constant among the photodiodes. Therefore, if the above-mentioned solid-state imaging device is used, it is possible to use not only a linear region but also a saturation region. The dynamic range of the solid-state imaging device can be expanded.

In addition, a smear phenomenon caused by light mixing caused by factors such as imperfect light shielding at the boundary between the photodiode and the vertical charge transfer path and light mixing from the side due to multiple reflection, and It is possible to separate the fluctuation phenomenon of the accumulated charge amount caused by the fluctuation of the barrier height of the p-well layer when extracting the electric charges. The degree of the smear phenomenon can be accurately grasped.

Next, a first modification of the solid-state imaging device according to the first embodiment will be described with reference to FIG.

FIG. 5 shows a solid-state imaging device C and a potential profile of the solid-state imaging device C along a section taken along line Va-Va.

In the solid-state imaging device C shown in FIG.
The same reference numerals are given to the same components as those of the solid-state imaging device B shown in FIG.

In the solid-state imaging device C shown in FIG. 5, a p-type semiconductor layer 14 formed between the n-type semiconductor substrate 1 and the p-well layer 15 is formed on the n-type semiconductor substrate 1 side. The solid-state imaging device B shown in FIG. 2 differs from the solid-state imaging device B shown in FIG. Other components and their respective parameters (type of p-type or n-type impurity,
The impurity concentration, layer thickness, etc.) may be the same as in the embodiment shown in FIG.

The first p-type semiconductor layer 14a has a p-type impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a thickness of 1 μm.
The p-type impurity concentration of the second p-type semiconductor layer 14b is 5 × 1
0 ¹⁸ cm ^-3 and a thickness of 1 μm. The p-type impurity concentration in the p-type semiconductor layer 14 is substantially uniform in each of the first p-type semiconductor layer 14a and the second p-type semiconductor layer 14b.

The first p-type semiconductor layer 14a and the second p-type semiconductor layer 14b are preferably formed by the above-described epitaxial growth method. A multiple ion implantation method in which ion implantation is performed several times or more while changing the acceleration energy may be used.

FIG. 5 also shows the potential along the line Va-Vb from the semiconductor substrate 1 to the n-type semiconductor layer 12 when the region of the photodiode 3a is cut in the vertical direction.

The n-type semiconductor substrate 1 is set at the substrate potential Vsub.

The potential shape in the depth direction is the first p
In the mold semiconductor layer 14a, the potential profile becomes higher and a substantially uniform potential profile (potential: VB1) is formed in the depth direction (thickness direction). Second p-type semiconductor layer 14
In b, the height of the potential becomes even higher,
A substantially uniform potential profile (potential: VB2) is formed in the depth direction (thickness direction).

The potential (V) in the p well 15
a) is a potential height (V) in the p-type semiconductor layer 14;
B1, VB2). The potential in the n-type semiconductor layer 12 is lower than the potential (Va) in the p-well 15.

N-type semiconductor substrate 1, first and second p-type semiconductor layers 14a and 14b, p-well 15, n-type semiconductor layer 1
A depletion layer is formed near the interface between the two layers.

In the solid-state imaging device C shown in FIG. 5, the electric charge accumulated in the n-type semiconductor layer 12 has the greatest influence between the n-type semiconductor layer 12 and the n-type semiconductor substrate 1. This is a region having a high potential, that is, a potential of the second p-type semiconductor region 14b.

Since the impurity concentration itself in the second p-type semiconductor region 14b is high, the barrier height VB2 increases.
According to the above doping concentration example, the potential Va
Is about 1.02 eV and the potential VB1 is about 1.04
eV and potential VB2 are about 1.06 eV.
The height is about 0.04 eV higher than the barrier height Va in the conventional structure (FIG. 10).

Further, the first and second p-type semiconductor layers 14
a, 14b, the height V of the potential barrier
B1 and VB2 are substantially uniform in the thickness direction. The width of the depletion layer at the interface between second p-type semiconductor region 14b and p-well layer 15 is also reduced. Since the region where the barrier height VB2 is uniform in the depth direction is wide and the depletion layer is narrow, the height VB2 of the potential barrier is hardly affected by potential fluctuation.

When a high negative voltage is applied to the vertical charge transfer electrode 3c when charges are accumulated in the photodiode 3a (during exposure), the height of the barrier (second barrier) formed by the transfer gate 3b is increased. Will be high enough.

In addition, the impurity concentration of the pixel separation layer 17 is
The impurity concentration is higher than the impurity concentration of the second p-type impurity layer 14b.

Accordingly, it is possible to suppress the variation in the photoelectric conversion characteristics between the photodiodes 3a due to the above-described variation in the barrier height from the first to the third.

Further, when forming the second p-type semiconductor layer 14b having a high p-type impurity concentration, the first p-type impurity having a lower p-type impurity concentration than the second p-type semiconductor layer 14b is formed.
Since the type semiconductor layer 14a is formed between the second p-type semiconductor layer 14b and the n-type semiconductor substrate 1, the n-type semiconductor substrate of the p-type impurity existing in the second p-type semiconductor layer 14b 1 can be reduced.

As described above, in the solid-state imaging devices B and C according to the first embodiment and the modifications thereof, the photoelectric conversion characteristics of the photodiodes in the saturation region R2 are different from those in the same solid-state imaging device. Become almost constant between.

Therefore, if the solid-state imaging device B or C is used, not only the linear region but also the saturation region can be used, and the dynamic range of the solid-state imaging device can be expanded.

In the modification of the solid-state imaging device according to the first embodiment, the first (p-type) semiconductor layer 14a,
Although the structure in which the second (p-type) semiconductor layer 14b and the (p) well layer 15 are all p-type conductive semiconductor layers has been described, the present invention is not limited to this structure.

For example, the p-well layer 15 may be an n-type semiconductor layer doped with an n-type impurity. Further, only the second semiconductor layer 14b may be p-type, and the first semiconductor layer 14a and the well layer 15 may be n-type. In short, a layer serving as a potential barrier for charged particles accumulated in the photodiode exists between the semiconductor substrate and the photodiode, and this potential is relatively high.
In addition, it is only necessary that the potential profile be substantially uniform.

Further, in the solid-state imaging device B according to the first embodiment and the solid-state imaging device C according to the modified example thereof,
2 μm was exemplified as the thickness of the p-type semiconductor layer 14. The thickness of the p-type semiconductor layer 14 may be smaller than 2 μm. However, a high positive voltage, for example, 1 with respect to the n-type semiconductor substrate 1
Even when a voltage of about 0 V is applied, it is desirable that a region having a substantially uniform potential profile remains at least about 0.1 μm to 0.2 μm.
The electrons excessively accumulated in the photodiode move through the potential barrier layer by diffusion. If the region having a substantially uniform potential profile is too thick, the time required to extract electrons increases. Therefore, the thickness of the region having a substantially uniform potential profile should not be too thick in the operating state.

Next, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 6 is a plan view corresponding to FIG. 1 in the first embodiment, and FIG. 7 is a VII-VII of FIG.
It is sectional drawing which follows a line.

As shown in FIG. 6, a solid-state imaging device D according to the second embodiment has a plurality of pixels 53 arranged in a row and a column on a two-dimensional plane of the surface of a semiconductor substrate 51. including. The pixel 53 includes a photoelectric conversion element (photodiode) 53a. The vertical charge transfer paths 65 extend in the vertical direction, respectively, near the plurality of photoelectric conversion element columns 53a arranged in the column direction. A transfer gate 5 is provided between the photoelectric conversion element 53a and the vertical charge transfer path 65.
3b is provided.

At one end of the vertical charge transfer path 65, a horizontal charge transfer path 67 is provided. An output amplifier 68 is provided at one end of the horizontal charge transfer path 67.

FIG. 7 is a sectional view taken along the line VII-VII of FIG.

As shown in FIG. 7, the solid-state imaging device D has n
A semiconductor substrate (n-type semiconductor substrate) 51 doped with a p-type impurity, a p-type semiconductor layer 54 doped with a p-type impurity formed thereon, and a p-well layer 55 similarly doped with a p-type impurity. including. Hereinafter, the structure of the solid-state imaging device D will be described in detail with reference to FIG.

The solid-state imaging device D has a line L1 (FIGS. 6 and 7).
Can be considered as a boundary line, divided into an imaging unit X and a peripheral part Y. In the imaging unit X, the pixels 53 including the photoelectric conversion elements 53a, the vertical charge transfer paths 65, and the like are formed.
In the peripheral portion Y, a horizontal charge transfer path 67, an output amplifier 71, and the like are formed.

A first p-well layer 55a is formed in the imaging section X, and a second p-well layer 55b is formed in the peripheral section Y. The impurity concentration of the first p-well layer 55a is lower than the impurity concentration of the second p-well layer 55b.

The reason for increasing the impurity concentration of the p-well layer 55b in the peripheral portion Y is that a photodiode is not formed in the peripheral portion, so that a depletion layer having a predetermined thickness required for photoelectric conversion needs to be formed. And if the p-type impurity concentration below the horizontal charge transfer path 67 is increased, the horizontal charge transfer path 67
This is because it is possible to prevent a so-called electron punch-through phenomenon, in which electric charges (electrons) transferred inside pass through the p-well layer and pass through the n-type semiconductor substrate 51.

As in the case of the solid-state imaging device according to the first embodiment, the impurity concentration of the p-type semiconductor layer
Is higher than the impurity concentration of the p-well layer (first p-well) 55a. The p-type semiconductor layer 54 is preferably formed with a substantially uniform concentration in the depth direction (thickness direction).

A vertical charge transfer path 65 doped with an n-type impurity is formed in the first p-well layer 55a. A horizontal charge transfer path 67 doped with an n-type impurity is formed in the second p-well layer 67a. Between the vertical charge transfer path 65 and the horizontal charge transfer path 67, there is formed a charge transfer section 66 doped with an n-type impurity and transferring the charge from the vertical charge transfer path 65 to the horizontal charge transfer path 67. The vertical charge transfer path 65 is provided via the insulating film 61.
A vertical charge transfer electrode 65a is formed on the upper part, a charge transfer electrode 66a is formed on the charge transfer part 66, and a horizontal charge transfer electrode 67a is formed on the horizontal charge transfer path 67.

A pixel isolation layer doped with a high concentration of p-type impurity is formed in a field region in the first p-well layer 55a.

At least a part (electrode lead-out area) Z of the area excluding the imaging part X and the peripheral part Y is provided with a high-density n.
Type semiconductor layers 71 and 73 are formed. The high-concentration n-type semiconductor layers 71 and 73 are formed from the surface to at least the surface of the n-type semiconductor substrate 51. The high-concentration n-type semiconductor layers 71 and 73 can form an electrical connection to the n-type semiconductor substrate 51, and can apply a substrate bias from the front side.

Next, the solid-state imaging device D having the above structure
A method of manufacturing the device will be described. The basic manufacturing process is the same as the manufacturing process described in the first embodiment. The same steps as those in the method for manufacturing the solid-state imaging device according to the first embodiment will be briefly described, and the different steps will be described in more detail.

First, an n-type semiconductor substrate 51 is prepared. n
The impurity concentration of the type semiconductor substrate 51 is, for example, 1 × 10 ¹⁵ c
m ^-3 .

A p-type semiconductor layer 54 is grown on an n-type semiconductor substrate 51 by using an epitaxial growth method. The impurity concentration of the p-type semiconductor layer 54 is of the order of 10 ¹⁶ cm ⁻³ , for example, 5 × 10 ¹⁶ cm ⁻³ . The thickness is, for example, 2 μm.

Preferably, the impurity concentration of p-type semiconductor layer 54 is substantially equal in the depth direction. In order to form a uniform concentration in the depth direction (thickness direction), a method of epitaxially growing the p-type semiconductor layer 54 is preferable.

As another method for forming a uniform concentration in the depth direction (thickness direction), a so-called multiple ion implantation method can be used. The concentration profile of the impurity formed by the ion implantation generally shows a Gaussian distribution in the depth (thickness) direction. When ion implantation is performed several times with different acceleration energies, it is possible to form the p-type impurity layer 54 having a substantially uniform concentration distribution in the depth direction.

Next, a p-well layer 55 is formed on the p-type semiconductor layer. The concentration of the p-type impurity in p-well layer 55 is 10
^{It is on the order of 17} cm ^-3 , for example, 2 × 10 ¹⁷ cm ^-3 .
The thickness of the p-well layer 15 is, for example, 2 μm.

A pattern having an opening in the peripheral portion Y is formed by, for example, an oxide film. Using the pattern formed by the oxide film as a mask, the p-well layer 55 in the peripheral portion Y is removed by etching. The first p-well layer 55a remains in the imaging unit X.

At this point, ion implantation of an n-type impurity is performed. Since the p-well layer 55 in the peripheral portion Y has been etched, ions may be implanted so that the peak of the n-type impurity concentration comes near the exposed surface. The n-type semiconductor region 71 can be formed with good controllability in the depth direction.

Using the oxide film pattern used for etching as a mask, a second p-well layer 55b is formed on p-type semiconductor layer 54 in peripheral portion Y by a selective growth method. The second p
The impurity concentration of the well layer 55a is
It is higher than the impurity concentration of b.

The p-type impurity concentration of second p-well layer 55b is 2 × 10 ¹⁷ cm ⁻³ . Second p-well layer 55b
Has a thickness of 2 μm.

Next, a pixel isolation region composed of a high-concentration p-type semiconductor layer is formed by, for example, an ion implantation method. The pixel separation layer penetrates the p-well layer 55 and is formed at least to a depth that reaches the surface of the p-type semiconductor layer 54. The p-type impurity concentration in the pixel separation layer is, for example, 5 × 10 ¹⁸ cm ^−3.
It is.

The pixel separation layer may be formed by forming a groove reaching at least the surface of the p-type semiconductor layer 54 in the p-well layer 55 and then filling the groove with an insulating film. .

Next, an n-type semiconductor layer is formed by an ion implantation method.

The n-type semiconductor layer for the photodiode 53a is formed, for example, by implanting P ions under the conditions of an acceleration energy of 1 MeV and a dose of 5 × 10 ¹⁴ cm ⁻² .

The n-type semiconductor layer for the vertical charge transfer path 65
For example, P ions are formed by ion implantation under the conditions of an acceleration energy of 500 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

By implanting P or As ions at a high energy and a high concentration into the region above the n-type semiconductor layer 71 already formed in the electrode lead region Z, a high-concentration n-type semiconductor layer is formed. 73 can be formed.

After the ion implantation, for example, from 600 ° C. to 100
Annealing is performed at a temperature between 0 ° C. to activate the implanted ions.

An oxide film 61 is formed on p well layer 55. The thickness of the oxide film is, for example, 1 μm.

The vertical charge transfer electrode 65a, the charge transfer electrode 6
6a and a polycrystalline silicon layer for the horizontal charge transfer electrode 67a are deposited and processed. When the charge transfer electrodes 65a, 66a, and 67a are formed by the first polycrystalline silicon layer (1 poly) and the second polycrystalline silicon layer (2 poly), the first An insulating film is formed between the first and second polycrystalline silicon layers.

On the polycrystalline silicon layer, an interlayer insulating film is formed. As the interlayer insulating film, for example, an oxide film or a nitride film formed by a sputtering method is used. The thickness of the interlayer insulating film is, for example, 1 μm.

Next, a light-shielding film is formed of, for example, Al. The light-shielding film has an opening formed in the light receiving portion of the photodiode.

A color filter, a micro lens, and the like are formed above the opening of the light shielding film.

In the solid-state imaging devices according to the first and second embodiments, the p-type semiconductor layer is not limited to Si. For example, Si having a wider band gap than Si
C may be used.

Further, the solid-state imaging device in which the conductivity type of the semiconductor substrate is n-type and the conductivity type of the well layer is p-type has been described. It is also possible to apply the present invention to a solid-state imaging device having the n-type conductivity.

Next, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to FIG.

The solid-state imaging device E shown in FIG. 8 is a line sensor.

As shown in FIG. 8, the line sensor E
One charge transfer path 75 having the same structure as the horizontal charge transfer path of the area sensor, a photoelectric conversion element (photodiode) 73a formed close to the charge transfer path 75,
It has a transfer gate 73b formed between the charge transfer path 75 and the photodiode 73a.

The charge transfer path 75 has a structure in which well layers (W) and barrier layers (B) are alternately arranged. The photodiode 73a is in communication with the well region (W) of the charge transfer path via the transfer gate 73b. The well layer (W) and the barrier layer (B) are n-type semiconductor layers formed in the p-well layer. The n-type semiconductor layer forming the well layer has a higher n-type impurity concentration than the n-type semiconductor layer forming the barrier layer.

Between one well layer W connected to one photodiode 73a and another photodiode 73a adjacent to it, one barrier layer (B), another well layer (W), another barrier layer The three layers of the layer (B) are alternately arranged.

The cross-sectional structure (cross section taken along line VIII-VIII) of the line sensor forming the photodiode 73a, the transfer gate 73b, and the charge transfer path 75 is the cross-sectional structure of the solid-state imaging devices B and C according to the first embodiment (FIG. 2, see FIG. 5). The vertical charge transfer path of FIGS. 2 and 5 has a structure substantially corresponding to that of FIG. 8 except that the n-type semiconductor layer forms a well layer and a barrier layer in the charge transfer path 75 of FIG. Have.

On the charge transfer path 75, a charge transfer electrode 77 is formed. A charge transfer electrode 77- is formed on the well layer (W) by using a first layer of polycrystalline silicon (polysilicon).
, 77-3,... Are formed.

On the well layer (W) and the barrier layer (B) adjacent to the well layer (W), the charge transfer electrodes 77-2, 77-4,
Are formed.

On the well layer (W), the first and second layers of polycrystalline silicon have a structure in which the layers overlap with an interlayer insulating film interposed therebetween. The first layer polycrystalline silicon and the second layer polycrystalline silicon are electrically connected by metal wiring,
The signal voltage φ1 can be applied. The adjacent first and second layers of polycrystalline silicon are also electrically connected by metal wiring, so that a signal voltage φ2 can be applied.

When the p-type impurity is ion-implanted at the time when the first polycrystalline silicon layer is formed on the well layer (W), the barrier layer in the charge transfer path is formed as the first polycrystalline silicon layer. The layer can be formed in a self-aligned manner as a mask for ion implantation.

The first layer of polysilicon (W) is formed on the well layer (W) of the charge transfer path 75 connected to the one photodiode 77a and the barrier layer (B) adjacent to the well layer (W). A charge transfer electrode is formed of polysilicon, and a second layer of polycrystalline is formed on the well layer (W) and the barrier layer (B) formed adjacent to the well layer (W) and the barrier layer (B). The charge transfer electrode may be formed of silicon (polysilicon).

In this case, signal voltage φ1 is applied to the charge transfer electrode formed of the first-layer polysilicon, and signal voltage φ2 is applied to the charge transfer electrode formed of the second-layer polysilicon. What should I do?

The charges transferred from the plurality of photodiodes 73a are transferred on the charge transfer path 75 by a two-phase driving method.
The data is transferred to the output amplifier 81. The signal voltage is amplified by the output amplifier 81 and read out.

FIG. 8 is a sectional view taken along line VIII-VIII of FIG.
Or it is a structure similar to FIG.

Therefore, not only in the linear region R1, but also in the saturation region R2, each photodiode 73
The photoelectric conversion characteristics of a, 73a,... hardly vary.

Therefore, a uniform output signal voltage can be obtained between the photodiodes over a wide incident light amount from the linear region R1 to the saturation region R2, and the dynamic range of the line sensor can be widened.

In the solid-state imaging devices according to the first to third embodiments, the potential profile between the n-type semiconductor device and the p-well layer is substantially constant.
The type semiconductor layer is inserted.

Further, instead of the above-mentioned p-type semiconductor layer, a semiconductor layer made of, for example, SiC may be used. Si 3
The energy band gap (Eg) at 00K is
About 1.12 eV, compared to 300K of SiC
Has a wide energy band gap of about 3 eV. Therefore, when a layer made of SiC is used instead of the p-type semiconductor layer, the variation in the photoelectric conversion characteristics in the saturation region can be suppressed.

As described above, in the first to third embodiments, the CCD type solid-state imaging device has been described as an example. However, in other solid-state imaging devices, for example, CMOS sensors, the photoelectric conversion unit is also used. By inserting a semiconductor layer forming a barrier having a uniform potential profile between a p-well forming a (photodiode) and an n-type semiconductor substrate, a dynamic range in photoelectric conversion characteristics can be widened.

Although the present invention has been described in connection with the preferred embodiments, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0192]

According to the solid-state imaging device of the present invention, the variation in the photoelectric conversion characteristics of each photodiode in the saturation region is reduced.

Therefore, the dynamic range of the photodiode can be expanded.

[Brief description of the drawings]

FIG. 1 is a plan view of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 shows a cross-sectional view taken along the line II-II of FIG. 1 and potential energy along the line IIa-IIa in the cross-sectional view.

FIG. 3 is a flowchart illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 4 shows a photoelectric conversion characteristic of a photodiode in the solid-state imaging device according to the first embodiment of the present invention.

FIG. 5 is a modified example of the solid-state imaging device according to the first embodiment of the present invention, and shows a cross-sectional view taken along line II-II of FIG. 1 and a potential energy along a Va-Va line of this cross-sectional view. .

FIG. 6 is a plan view of a solid-state imaging device according to a second embodiment of the present invention.

7 is a sectional view taken along the line VII-VII in FIG.

FIG. 8 is a plan view of a line sensor according to a third embodiment of the present invention.

FIG. 9 is a plan view of a conventional solid-state imaging device.

10 is a sectional view taken along line XX of FIG.
-It is a potential profile along the Xa line.

FIG. 11 is a diagram illustrating photoelectric conversion characteristics in a conventional solid-state imaging device.

[Explanation of symbols]

A, B, C, D Solid-state imaging device (area sensor) E Solid-state imaging device (line sensor) H Flattening film ML Micro lens CF Color filter R1 Linear region R2 Saturation region X Imaging unit Y Peripheral part Z Electrode extraction region A1, A2, A3 Photoelectric conversion characteristics of photodiode 1, 51 Semiconductor substrate (n-type semiconductor substrate) 3, 53 Pixel 3a, 53a, 73a Photoelectric conversion element (photodiode) 3b, 51b, 73b Transfer gate 3c Vertical charge transfer electrode 5, 65 vertical charge transfer path 7, 67 horizontal charge transfer path 65a vertical charge transfer electrode 66a charge transfer electrode 67a horizontal charge transfer electrode 11, 68, 81 output amplifier 12 n-type semiconductor layer 14 p-type semiconductor layer 15 p-well layer 17 pixel separation Layer 21 Oxide film 24 Interlayer insulating film 25 Light shielding film 75 Charge transfer path 7 charge transfer electrodes

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AA06 AA10 AB01 BA10 BA14 CA03 DA03 DA23 DA32 DB06 EA01 EA08 EA15 FA02 FA06 FA08 FA13 FA26 FA35 FA45 GB11

Claims (15)

[Claims] A first conductive type semiconductor substrate; a first potential barrier layer formed on the first conductive type semiconductor substrate and having a substantially flat barrier height in a depth direction; Second layer formed on the barrier layer
A first conductive type well layer and a first conductive layer formed in a matrix near the surface in the second conductive type well layer and arranged in a column direction and a row direction to form a photoelectric conversion element together with the second conductive type well layer; A first conductivity type semiconductor layer, and a second conductivity type well layer, formed in the row direction close to the first first conductivity type semiconductor layer aligned in the column direction, in the second conductivity type well layer. A second first conductivity type semiconductor layer forming a vertical charge transfer path for transferring accumulated charges. 2. The solid-state imaging device according to claim 1, wherein the first potential barrier layer is a second conductivity type high impurity concentration layer. 3. A second potential barrier layer having a barrier height different from that of the first potential barrier layer is formed between the first potential barrier layer and the second conductivity type well layer. The solid-state imaging device according to claim 1. 4. The solid-state imaging device according to claim 3, wherein a barrier height of the second potential barrier layer is lower than a barrier height of the first potential barrier layer. 5. The solid-state imaging device according to claim 3, wherein the second potential barrier layer is a layer formed by epitaxial growth. 6. The solid-state imaging device according to claim 1, wherein said first potential barrier layer is a layer formed by epitaxial growth. 7. The photoelectric conversion device according to claim 1, further comprising: a second conductive type well layer formed outside of the photoelectric conversion element and the vertical charge transfer path corresponding to the photoelectric conversion element in the second conductivity type well layer.
7. The solid-state imaging device according to claim 1, wherein a pixel separation region reaching the upper surface of the potential barrier layer is formed. 8. The solid-state imaging device according to claim 7, wherein the pixel isolation region is formed of a high-concentration second conductivity type semiconductor layer. 9. The solid-state imaging device according to claim 7, wherein the pixel isolation region includes a groove formed in the second conductivity type well layer, and an insulator filled in the groove. 10. A potential height of the pixel isolation region and the first potential barrier layer is formed higher than a potential height of the second conductivity type well layer, and further, the first first conductivity type semiconductor layer is formed. A voltage application means provided on the second conductivity type well layer between the second conductivity type semiconductor layer and the second first conductivity type semiconductor layer. 9. The solid-state imaging device according to claim 8, further comprising a voltage application unit that controls the potential of the well layer to be higher than the potential height. 11. The potential height of the separation region is:
The solid-state imaging device according to claim 8, wherein the potential is higher than a potential height of the first potential barrier layer. 12. The second potential barrier layer,
The solid-state imaging device according to claim 3, comprising a semiconductor layer of a first conductivity type. 13. A first conductive type semiconductor substrate, a first potential barrier layer formed on the first conductive type semiconductor substrate and having a substantially flat barrier height in a depth direction, and the first potential Second layer formed on the barrier layer
A first conductive type well layer and a first conductive layer formed in a matrix near the surface in the second conductive type well layer and arranged in a column direction and a row direction to form a photoelectric conversion element together with the second conductive type well layer; And a first conductive type semiconductor layer formed in the second conductive type well layer and formed in the first conductive type semiconductor layer aligned in a column direction in a row direction and accumulated in the photoelectric conversion element. A second first conductivity type semiconductor layer forming a vertical charge transfer path for transferring the transferred charge, and an impurity of the second conductivity type well layer in an imaging unit including the photoelectric conversion element and the vertical charge transfer path. A solid-state imaging device in which the concentration is different from the impurity concentration of the second conductivity type well layer in a peripheral portion thereof. 14. The solid-state imaging device according to claim 13, wherein an impurity concentration in the peripheral portion is higher than an impurity concentration in the imaging section. 15. A first conductivity type semiconductor substrate, a first potential barrier layer formed on the first conductivity type semiconductor substrate and having a substantially flat barrier height in a depth direction, and the first potential Second layer formed on the barrier layer
A plurality of conductive type well layers and a plurality of second conductive type well layers, which are arranged in one direction on a two-dimensional plane in a region near a surface in the second conductive type well layers and form a plurality of the second conductive type well layers; The first first conductivity type semiconductor layer and the second conductivity type well layer are formed in the vicinity of the first first conductivity type semiconductor layer in the horizontal direction and accumulated in the photoelectric conversion element. A second first-conductivity-type semiconductor layer forming a charge transfer path for transferring charges.