JP2001228599A - Auxiliary pattern generation method and semiconductor mask layout pattern automatic generation method - Google Patents

Abstract

(57) Abstract: Provided are an auxiliary pattern generation method and an automatic generation method capable of reducing human errors in auxiliary pattern generation and shortening a photomask manufacturing TAT. A process of extracting a pattern having a specific width or less from a main pattern to be formed with an auxiliary pattern, and a base pattern of the auxiliary pattern by a graphic logic operation and dimensional correction based on the pattern extracted in the process. Forming the main pattern 1 as an auxiliary pattern exclusion area.
A step of forming a hammer head pattern on the protruding portion of the line shape, and a step of forming an auxiliary pattern exclusion region in a portion of the main pattern 1 that is smaller than a specific space width.
Generating the auxiliary pattern 5 by ANDing the original shape of the auxiliary pattern and the inversion of the auxiliary pattern exclusion area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout data generation technique for forming a pattern on a photomask in a semiconductor manufacturing process by using CAD, that is, a method for generating an auxiliary pattern in a semiconductor mask layout pattern and an automatic generation of the semiconductor mask layout pattern. It is about the method.

[0002]

2. Description of the Related Art In recent years, a photolithography technique has been used to form a fine pattern like a semiconductor element pattern on a silicon wafer in a semiconductor element manufacturing process.

[0003] Of these, a technique of optical proximity effect correction for a pattern (Optical Prox) has attracted particular attention.
Immediate Correction). This is a phenomenon that when exposed on a semiconductor substrate using a photomask, the shape of the transferred pattern is deformed due to the influence of other patterns around the pattern due to the characteristics of light, and the performance of the semiconductor element is reduced. Is a technique for forming a target pattern on a semiconductor substrate by correcting the two-dimensional pattern dimension on a photomask in advance.

As one of the techniques for correcting the optical proximity effect,
As shown in FIG. 4, there is a technique for forming a fine pattern called an auxiliary pattern 5 that is not resolved near a main pattern 1 on a photomask. This is to control the phase and intensity of light by adding the auxiliary pattern 5 and to improve the light intensity distribution of the main pattern 1 at the time of exposure to form a semiconductor element pattern having a desired shape on a semiconductor substrate.

[0005] The auxiliary pattern is smaller than a specific line width and
It is necessary to add to an isolated pattern having a specific space width, and in this case, the effectiveness is high.

[0006]

In the conventional semiconductor manufacturing, when the auxiliary pattern 5 is formed with respect to the main pattern 1, it is arranged by a manual operation using a pattern layout tool at a design stage.

However, there is a human error in generating the auxiliary pattern due to the manual operation, and the production of the photomask is difficult.
There is a disadvantage that the AT (Turn Around Time) becomes longer.

An object of the present invention is to provide an auxiliary pattern generation method and an automatic generation method of a semiconductor mask layout pattern which can reduce human error in generation of an auxiliary pattern and shorten a photomask manufacturing TAT. .

That is, the generation and arrangement of the auxiliary pattern, which has been performed manually, is automatically generated by CAD processing using graphic logic operation or dimensional correction, and a photomask taking into account the optical proximity effect is obtained.

[0010]

According to a first aspect of the present invention, there is provided a method for generating an auxiliary pattern, wherein a pattern size is controlled in the vicinity of the light-shielding pattern in a light-shielding pattern transferred onto a semiconductor substrate using a photomask. An auxiliary pattern generation method for generating an auxiliary pattern that is not resolved,
It is characterized in that an auxiliary pattern is automatically generated in the vicinity of a light-shielding pattern using a graphic logic operation and dimension correction.

According to the auxiliary pattern generation method of the present invention, for example, CAD data is applied to semiconductor element pattern data.
It is possible to add a supplementary pattern by performing a figure logic operation and pattern dimension correction in the processing, extracting a part to which an auxiliary pattern is added by combining the figure logic operation and the pattern dimension correction. As a result, compared to the manual generation of the auxiliary pattern using the pattern layout tool, the graphic logic operation and the pattern dimension correction are automatically generated in the CAD processing, thereby reducing the human error in the generation of the auxiliary pattern and correcting the optical proximity effect. By performing high-speed generation of a pattern on which a pattern is applied, the TAT for manufacturing a photomask can be reduced.

According to a second aspect of the present invention, there is provided a method of generating an auxiliary pattern.
2. The method according to claim 1, wherein the graphic logical operation and the dimensional correction are performed by CA.
This is performed on the D processing.

According to the auxiliary pattern generation method of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, there is provided a method of automatically generating a semiconductor mask layout pattern, wherein the auxiliary pattern according to the first aspect is added near a light-shielding pattern having a specific line width or less.

According to the third aspect of the present invention, the same effect as that of the first aspect can be obtained.

According to a fourth aspect of the present invention, there is provided a method for automatically generating a semiconductor mask layout pattern, wherein the auxiliary pattern according to the first aspect is added to a vicinity of an isolated pattern separated by a specific space width or more in a light shielding pattern. Things.

According to the fourth aspect of the present invention, the same effect as that of the first aspect can be obtained.

According to a fifth aspect of the present invention, there is provided a method for generating an auxiliary pattern.
A process of extracting a pattern having a specific width or less from a main pattern to be formed with an auxiliary pattern, and a process of forming an original shape of the auxiliary pattern by graphic logical operation and dimensional correction based on the pattern extracted in this process; A step of forming a hammerhead pattern in a line-shaped protrusion of the main pattern as a first auxiliary pattern exclusion area, a step of forming a second auxiliary pattern exclusion area in a portion of the main pattern having a specific space width or less, The method includes a step of generating an auxiliary pattern only from a portion where the original shape of the auxiliary pattern and the inversion of the first auxiliary pattern exclusion area and the inversion of the second auxiliary pattern exclusion area are mutually overlapped.

According to the auxiliary pattern generation method of the fifth aspect, the same effect as that of the first aspect is obtained.

According to a sixth aspect of the present invention, there is provided a method of automatically generating a semiconductor mask layout pattern, wherein an auxiliary pattern is added near a main pattern by superposing both the auxiliary pattern and the main pattern.

According to the method for automatically generating a semiconductor mask layout pattern according to the sixth aspect, the same effect as that of the first aspect can be obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The procedure of an embodiment of the present invention will be described below with reference to FIGS. According to the present embodiment, a procedure for adding an auxiliary pattern 5 as shown in FIG. 4 near the main pattern 1 in FIG. 1A, which is a part of the light shielding pattern of the design layout data, will be described. In this case, the line width is set to α (corresponding to claim 2), the specific space width is set to β (corresponding to claim 3), and the pattern width smaller than the line width α and the space width with other peripheral patterns are set to β. An auxiliary pattern is added to the above isolated pattern. 1 to 3 show the progress of the auxiliary pattern generation procedure.

From the main pattern 1 in FIG.
In order to extract the above-mentioned pattern, the pattern shown in FIG.
As shown in (b), a pattern having a line width α or less can be deleted. Next, the pattern having the line width α or more is returned to the original shape by dimensional correction for increasing the pattern of FIG. 1B by α / 2 (FIG. 1C). 1 (a) and FIG.
An AND with the inversion of the pattern of (c), that is, a pattern having a line width α or less is obtained only from the overlapping part (FIG. 1D). Here, the distance n from the main pattern 1 (n
It is assumed that an auxiliary pattern having a line width m is generated in <β).
A pattern (FIG. 2A) in which the pattern 4 in FIG. 1D is enlarged by (n + m) by dimension correction and a pattern (FIG. 2B) in which n is enlarged are generated in advance. The original pattern 2 of the auxiliary pattern 5 is obtained by ANDing the pattern of FIG. 2A and the inverse of the pattern of FIG. 2B (FIG. 2C). Since an auxiliary pattern is not required at the protruding portion of the line-shaped pattern, a hammer head (protrusion = n + m, extension) is provided at the protruding portion of the line shape in the pattern of FIG.
on = n + m, offset = 0) is formed (FIG. 2D). Since the area where the space width of the pattern is equal to or smaller than β is also an excluded area, a pattern (FIG. 3A) obtained by increasing the pattern of FIG. 1D by β / 2 is formed. fill in. Next, by performing dimensional correction to narrow the pattern of FIG. 3A by β / 2, a portion having a space of β or more is returned to the original shape (FIG. 3B). FIG. 3 (b)
1D and the inversion of the pattern of FIG. 1D to form an auxiliary pattern exclusion region having a space width of β or less (FIG. 3C). FIG. 2 which is the original form of the auxiliary pattern
(C), the inversion of the exclusion area in FIG.
FIG. 3C shows an AND of the exclusion area in FIG.
A necessary and sufficient auxiliary pattern 5 shown in (d) is obtained. In addition,
Numeral 6 denotes a hammer head pattern which is an exclusion area of the auxiliary pattern, and numeral 7 denotes a pattern in which the space width of the pattern of FIG.

Finally, an OR of the main pattern 1 (FIG. 1 (a)) and the auxiliary pattern 5 (FIG. 3 (d)), that is, a pattern on the photomask taking the optical proximity effect into consideration, by obtaining both by overlapping each other. A shape can be generated (FIG. 4).

[0025]

According to the auxiliary pattern generation method of the first aspect, for example, CA
By performing graphic logical operation and pattern dimension correction on the D processing, by combining graphic logical operation and pattern dimension correction, it is possible to extract a portion to which an auxiliary pattern is added, and to add an auxiliary pattern. As a result, compared to the manual generation of the auxiliary pattern using the pattern layout tool, the graphic logic operation and the pattern dimension correction are automatically generated in the CAD processing, thereby reducing the human error in the generation of the auxiliary pattern and correcting the optical proximity effect. By performing high-speed generation of a pattern on which a pattern is applied, the TAT for manufacturing a photomask can be reduced.

According to the auxiliary pattern generation method of the second aspect, the same effect as that of the first aspect is obtained.

According to the third aspect of the present invention, the same effect as that of the first aspect can be obtained.

According to the method of automatically generating a semiconductor mask layout pattern according to the fourth aspect, the same effect as that of the first aspect can be obtained.

According to the auxiliary pattern generation method of the fifth aspect, the same effect as that of the first aspect is obtained.

According to the method of automatically generating a semiconductor mask layout pattern according to the sixth aspect, the same effect as that of the first aspect can be obtained.

[Brief description of the drawings]

FIG. 1A is a diagram of an original main pattern on a photomask for which an auxiliary pattern is to be generated,
(B) is a pattern diagram obtained by narrowing the main pattern of (a) by α / 2, and (c) is a width α from the main pattern of (a).
FIG. 4D is a pattern diagram in which only the above patterns are extracted, and FIG. 4D is a pattern diagram in which only patterns having a width α or less are extracted from the main pattern in FIG.

2A is a pattern diagram that is an outer frame of an auxiliary pattern to be generated, FIG. 2B is a pattern diagram that is an inner frame of an auxiliary pattern to be generated, FIG. 2C is a pattern diagram that is an original shape of the auxiliary pattern, d) is a hammerhead pattern diagram that becomes an auxiliary pattern removal area.

3A is a pattern diagram obtained by increasing the pattern of FIG. 1D by β / 2, FIG. 3B is a pattern diagram in which a region having a space width β or less in FIG. 1D is filled, and FIG. Figure 1 (d)
3D is a pattern diagram of an auxiliary pattern exclusion region having a space width β or less, and FIG. 4D is a diagram of an auxiliary pattern necessary for optical proximity effect correction excluding the pattern of the exclusion region.

FIG. 4 is a pattern diagram after optical proximity effect correction in which a necessary auxiliary pattern is added to the main pattern of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Main pattern on photomask 2 Original pattern of auxiliary pattern 3 Hammer head pattern 4 Pattern used as a source of hammer head formation 5 Auxiliary pattern 6 Hammer head pattern 7 Pattern in which the space width of the pattern in FIG.

Claims (6)

[Claims] 1. An auxiliary pattern generating method for generating a non-resolution auxiliary pattern for controlling a pattern size in the vicinity of the light shielding pattern in the light shielding pattern transferred onto a semiconductor substrate using a photomask. And generating automatically the auxiliary pattern in the vicinity of the light-shielding pattern using a graphic logic operation and a dimension correction. 2. The auxiliary pattern generating method according to claim 1, wherein the graphic logical operation and the dimensional correction are performed on a CAD process. 3. A method for automatically generating a semiconductor mask layout pattern, wherein the auxiliary pattern according to claim 1 is added near a light-shielding pattern having a specific line width or less. 4. A method for automatically generating a semiconductor mask layout pattern, comprising: adding the auxiliary pattern according to claim 1 to the vicinity of an isolated pattern separated by a specific space width or more in a light-shielding pattern. 5. A process of extracting a pattern having a specific width or less from a main pattern to be formed with an auxiliary pattern, and based on the pattern extracted in this process, performing a graphic logic operation and dimensional correction to form an original of the auxiliary pattern. Forming, forming a hammerhead pattern on a line-shaped protrusion of the main pattern as a first auxiliary pattern exclusion area, and excluding a second auxiliary pattern in a portion of the main pattern having a specific space width or less. Forming an area, and generating the auxiliary pattern only by mutually overlapping portions of the original shape of the auxiliary pattern, the inversion of the first auxiliary pattern exclusion area, and the inversion of the second auxiliary pattern exclusion area. And an auxiliary pattern generation method including: 6. A method of automatically generating a semiconductor mask layout pattern in which both an auxiliary pattern and a main pattern according to claim 5 are overlapped and an auxiliary pattern is added near the main pattern.