JP2001228831A - Electro-optical device - Google Patents

Abstract

(57) Abstract: An electro-optical device that displays an image or the like based on an image signal that has been serial-parallel-converted into a plurality of phases is provided. I do. In a first display mode, a sampling start signal is supplied to a first bidirectional shift register,
A precharge start signal is supplied to the second bidirectional shift register 14, and in the case of the second display mode, a sampling start signal is supplied to the second bidirectional shift register and a precharge is supplied to the first bidirectional shift register. Supply a start signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electro-optical device, and more particularly to an electro-optical device capable of displaying an image by inverting left and right.

[0002]

2. Description of the Related Art In a liquid crystal device as an example of an electro-optical device incorporated in a liquid crystal projector or the like, there may be a case where an image whose right and left are inverted or an image whose top and bottom are inverted is required due to a projection optical system. Japanese Patent Laid-Open No. 7-20826 discloses a display device capable of switching the operation direction of a drive circuit section to perform left-right inverted display and up-down inverted display.
JP, JP-A-7-146462, JP-A-10-106
It is known from, for example, US Pat. Use a shift register that constitutes a drive circuit that can perform bidirectional operation,
By switching the scanning direction, switching between the standard image display and the inverted image display is performed.

Japanese Patent Application Laid-Open No. Hei 7-295520 discloses an electro-optic device in which an image signal is written to a pixel after precharging, thereby suppressing potential fluctuation of an image signal line caused by an increase in sampling rate. An apparatus is described.

FIG. 6 is a block diagram of an electro-optical device described in Japanese Patent Application Laid-Open No. 7-295520. The conventional electro-optical device 1000 shown in FIG.
An image display unit 1100 including column-shaped data lines Y, thin film transistors TFT and pixels LC arranged at their intersections, a scanning line driving circuit 1001,
A data line driving circuit 1002; an image signal line 1003 for supplying an image signal VID;
02 output from the sampling timing signal φH1
SSW1 to HSW for supplying an image signal VID to each data line Y based on .about..phi.HN.
N and precharge means 1004.

The gate of the thin film transistor TFT is connected to the scanning line X. The source of the thin film transistor TFT is connected to the data line Y. Thin film transistor TF
The drain of T is connected to the pixel electrode of the pixel LC.

The precharge means 1004 includes a precharge drive circuit 1005, a precharge signal line 1006 for supplying a precharge signal VPS, and precharge timing signals φP1 to φPN output from the precharge drive circuit 1005. And a precharge switch circuit PSW1 to PSWN for supplying a precharge signal VPS to each data line Y based on the above.

VCK is a vertical clock signal, VST is a vertical start signal, HCK is a horizontal clock signal, HST is a sampling start signal, PCK is a horizontal clock signal,
PST is a precharge start signal, and φV1 to φVM are scanning signals.

The scanning line driving circuit 1001 generates each scanning signal φ
Each scanning line X is line-sequentially scanned based on V1 to φVM, and 1
One row of pixels LC is selected every horizontal period. The data line driving circuit 1002 includes a sampling switch circuit HS
The image signal VI within one horizontal period via W1 to HSWN
D is sequentially sampled on each data line Y, and the selected 1
The image signal VID is written into the pixels LC of the row in a dot sequence. The precharge means 1004 sequentially supplies a predetermined precharge signal VPS to each data line Y via the precharge switch circuits PSW1 to PSWN prior to the sequential sampling of the image signal VID for each data line Y. .

A conventional electro-optical device 1000 shown in FIG.
Since the predetermined precharge signal VPS is sequentially supplied to each data line Y prior to the sequential sampling of the image signal VID for each data line Y, the charging and discharging of each data line Y due to sampling can be suppressed. Thus, potential fluctuation (noise) of the image signal line 1003 is reduced. Therefore, it is possible to prevent a noise pattern such as a vertical stripe from being generated in the display image.

In a configuration in which the image signal VID is supplied by one image signal line, the image signal VID is proportional to the number of pixels in one row.
Dot frequency increases. Therefore, a technique is known in which the image signal VID is subjected to serial-parallel conversion into a plurality of phases to reduce the dot frequency for each phase.

FIG. 7 is a block diagram of a conventional electro-optical device for displaying an image based on an image signal that has been serial-parallel converted into a plurality of phases. FIG. 7 shows the image signal VID.
Is converted into six phases by serial-parallel conversion.

A conventional electro-optical device 2000 shown in FIG.
Includes six-phase image signal lines 2001 to 2006. A first-phase image signal VI is connected to a first-phase image signal line 2001.
As D1, image signals to be supplied to the data lines Y1, Y7, Y13,... Are sequentially supplied at predetermined time intervals. A second phase image signal VID2 is connected to the second phase image signal line 2002.
Are supplied sequentially to the data lines Y2, Y8, Y14,... At predetermined time intervals. The image signals to be supplied to the data lines Y3, Y9, Y15,... Are sequentially supplied at predetermined time intervals to the third phase image signal line 2003 as the third phase image signal VID3. A fourth-phase image signal VID4 is connected to a fourth-phase image signal line 2004 as a fourth-phase image signal VID4.
The image signals supplied to the data lines Y4, Y10, Y16,... Are sequentially supplied at predetermined time intervals. The image signals to be supplied to the data lines Y5, Y11, Y17,... Are sequentially supplied at predetermined time intervals to the fifth phase image signal line 2004 as the fifth phase image signal VID5. Image signals to be supplied to the data lines Y6, Y12, Y18,... Are sequentially supplied at predetermined time intervals to the sixth-phase image signal line 2004 as the sixth-phase image signal VID6.

First sampling switch circuit HSW
1 is connected to the first image signal line 2001, and the first
The other end of the sampling switch circuit HSW1 is connected to the first data line Y1. Therefore, the first sampling switch circuit HSW1 supplies the first phase image signal VID1 to the first data line Y1 based on the first sampling timing signal φH1. One end of the second sampling switch circuit HSW2 is connected to the second image signal line 2002, and the other end of the second sampling switch circuit HSW2 is connected to the second data line Y2. Therefore, the second sampling switch circuit HSW2 generates the second sampling timing signal φH
2 to supply the second phase image signal VID2 to the second data line Y2. The third to sixth sampling switch circuits HSW3 to HSW6 convert the third to sixth phase image signals VID3 to VID6 into third to sixth image signals based on the third to sixth sampling timing signals φH3 to φH6. It is supplied to the data lines Y3 to Y6, respectively. In FIG. 7, the sampling switch circuits HSW7 to HSWN after the sixth sampling switch circuit HSW6 and the sixth
Although the illustration of the data lines Y7 to YN after the data line Y6 is omitted, the same connection configuration as described above is repeated with six data lines as one group.

The data line driving circuit 1002 is constituted by using a shift register or the like, and sequentially shifts the sampling start signal HST in synchronization with the horizontal clock signal PCK, thereby obtaining each sampling timing signal φ.
H1 to φH6 are sequentially output. As a result, the sampling switch circuits HSW1 to HSW6 are sequentially controlled to be conductive, and the image signals VID1 to VID6 are sequentially supplied to the data lines Y1 to Y6. Then, each data line Y
Image signals VID1 to VID6 supplied to 1 to Y6
Are supplied to the respective pixels LC via the respective thin film transistors TFT connected to the gate lines X1 to XM activated by the scanning signals φV1 to φVM. Thus, an image signal is written to each pixel LC.

[0015]

The conventional electro-optical device 1000 shown in FIG. 6 is constructed by using a bidirectional shift register or the like capable of bidirectionally shifting the data line driving circuit 1002 and the precharge driving circuit 1005. By doing so, the dot sequential scanning direction can be reversed. Thereby, the left and right of the display image can be reversed.

However, in the configuration in which the image signal VID is serial-parallel-converted into a plurality of phases as shown in FIG. 7, even if the scanning direction in the dot-sequential manner is reversed, the left and right of the displayed image cannot be reversed. In the conventional electro-optical device 2000 shown in FIG. 7, six data lines are taken as one group, and each data line in the group is associated with six-phase image signal lines 2001 to 2006. Therefore, when the dot-sequential scanning direction is reversed, the order of the image signals supplied to each data line in the group of six data lines is not reversed.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. In an electro-optical device for displaying an image or the like based on an image signal that has been serial-parallel converted into a plurality of phases, the displayed image can be horizontally shifted. It is an object of the present invention to provide an electro-optical device that can be inverted.

[0018]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention comprises a plurality of data lines to which image signals are supplied, a plurality of scanning lines to which scanning signals are supplied, and In an electro-optical device including a switching unit connected to a data line and each of the scanning lines, and a pixel electrode connected to the switching unit, a first and a second bidirectional shift register, a first and a second bidirectional shift register, A first sampling circuit for transmitting the state of the potential of the first wiring group to the data line based on the output timing of the first bidirectional shift register; and the second bidirectional shift register. Based on the output timing of the shift register,
A second sampling circuit for transmitting the state of the potential of the second wiring group to the data lines; and, in a first display mode, shifting the first and second bidirectional shift registers in a first direction. Supplying a sampling start signal to the first shift register, a precharge start signal to the second shift register, and supplying a potential serving as an image signal to the first wiring group; Is supplied with a precharge potential, and in the case of the second display mode,
The first and second bidirectional shift registers are shifted in a second direction, and a sampling start signal is supplied to the second shift register, and a precharge start signal is supplied to the first shift register. A switching circuit for controlling a supply of a potential serving as an image signal to the wiring group and a supply of a precharge potential to the first wiring group.

With such a configuration, the first
In the display mode, the writing of the image signal is controlled by the first bidirectional shift register and the first sampling circuit, and the application of the precharge potential is controlled by the second bidirectional shift register and the second sampling circuit. . In the second display mode, writing of an image signal is controlled by the second bidirectional shift register and the second sampling circuit, and application of a precharge potential is controlled by the first bidirectional shift register and the first sampling circuit. Is done.

The first sampling circuit is wired so as to supply, for example, first to sixth phase image signals to the first to sixth data lines, respectively. Therefore, by setting the shift direction of the first bidirectional shift register to the first direction, a plurality of image signals serial-parallel converted to a plurality of phases are forward-directed to each data line in the order of the phases. Are supplied sequentially. That is, the image signals of the first pixel to the last pixel of one scanning line are sequentially supplied, for example, from the left data line to the right data line. Thereby, the first display image is displayed.

The second sampling circuit is connected so as to supply, for example, image signals of the first to sixth phases to the sixth to first data lines, respectively. Therefore, by setting the shift direction of the second bidirectional shift register to the second direction, a plurality of image signals serial-parallel converted to a plurality of phases are transmitted to each data line in the order of the phases. Are sequentially supplied in the direction of. That is, for example, image signals of the first pixel to the last pixel of one scanning line are sequentially supplied from the right data line to the left data line. Thereby, for example, a left-right inverted image is displayed.

Further, in the electro-optical device according to the present invention, the first and second bidirectional shift registers are driven by a common clock signal, and the two shift registers are driven by a common clock. By doing
The number of required clocks can be reduced. Further, the shift direction of the first and second bidirectional shift registers is set by a common scanning direction selection signal. In this way, two bidirectional shift registers can be controlled by one scanning direction selection signal. Further, the switching circuit selectively supplies one of a sampling start signal and a precharge start signal to the first shift register based on the scanning direction selection signal, and supplies a sampling start signal and a precharge start signal to the second shift register. The other of the precharge start signals is selectively supplied, and the first
One of the image signal and the precharge potential is selectively supplied to the group of wirings, and the other of the display data and the precharge potential is selectively supplied to the second group of wirings. This makes it possible to switch the display data and the precharge potential to the wiring group with a simple configuration. Further, the electro-optical device of the present invention includes a plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, and switching means connected to each of the data lines and each of the scanning lines. An electro-optical device comprising: a pixel electrode connected to the switching unit;
A plurality of image signals subjected to serial-parallel conversion in the case of the first display mode;
And in the case of the second display mode, the image signal phase order in which the plurality of serial-parallel-converted image signals are supplied to the signal line group in a second order reverse to the first order. A switching circuit, and a bidirectional shift for sampling control, wherein a shift direction is set in a first direction in the case of the first display mode, and a shift direction is set in a second direction in the case of the second display mode. A register and a sampling circuit for transmitting a potential state of the signal line group to the data line based on an output timing of the sampling control bidirectional shift register. Further, the first bidirectional shift register is configured to sequentially transmit the potential of the first wiring group to the plurality of data lines.
The second bidirectional shift register is configured to supply an output signal to the first sampling circuit, and the second bidirectional shift register is configured to transmit the potential of the second wiring group to the plurality of data lines sequentially. It is characterized by being configured to supply an output signal to a sampling circuit. By doing so, it is possible to prevent the potentials of the plurality of data lines from changing at once. Further, the first bidirectional shift register is configured to supply an output signal to the first sampling circuit so that a potential of the first wiring group is simultaneously transmitted to a plurality of the data lines. Second
Is configured to supply an output signal to the second sampling circuit such that the potential of the second wiring group is simultaneously transmitted to a plurality of the data lines. With such a structure, the driving frequency of the shift register can be reduced.

With the above configuration, in the first display mode, a plurality of image signals serial-to-parallel converted to a plurality of phases are supplied to a plurality of image signal lines in a phase sequence, and a bidirectional shift for sampling control is performed. The shift direction of the register is defined as a first direction. The sampling circuit is the first
The plurality of image signals sequentially supplied to the plurality of image signal lines are sequentially supplied to the data lines based on the sampling timing signal shifted in the direction. That is, image signals from the first pixel to the last pixel of one scan line are sequentially supplied, for example, from the left data line to the right data line.
Thereby, the first display image is displayed.

In the second display mode, a plurality of image signals serial-to-parallel converted to a plurality of phases are supplied to a plurality of image signal lines in reverse phase order, and the shift of the bidirectional shift register for sampling control is performed. The direction is defined as a second direction. The sampling circuit sequentially supplies, to the data lines, a plurality of image signals which are supplied to the plurality of image signal lines in a reverse phase order, based on the sampling timing signal shifted in the second direction. That is, image signals from the first pixel to the last pixel of one scanning line are sequentially supplied, for example, from the right data line to the left data line. Thereby, for example, a left-right inverted image is displayed.

Further, in the first display mode, the shift direction is set to a first direction, and in the second display mode, the shift direction is set to a second direction.
A precharge control bidirectional shift register for sequentially outputting a precharge timing signal from each shift stage by shifting a precharge start signal in a designated shift direction, and a precharge control bidirectional shift register for precharging the data line based on the precharge timing signal. A precharge circuit for supplying a charge potential.

By adopting the above configuration, switching between the first display and the second display is possible, and prior to the sequential sampling of the image signal to each data line,
Each data line can be precharged.

[0027]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of the electro-optical device according to the first embodiment. In the present embodiment, the image signals VID1 to VI serial-parallel-converted into six phases are provided.
The electro-optical device 10 that displays an image based on D6 is shown. This embodiment mode shows an example in which an active matrix liquid crystal display device is used.

The electro-optical device 10 outputs a scanning direction selection signal D
It is possible to switch between a standard image display mode as a first display mode and a horizontally inverted image display mode as a second display mode based on IR. In the present embodiment, for example, when the scanning direction selection signal DIR is set to the H level, it operates in the standard image display mode to display the standard image,
When the scanning direction selection signal DIR is set to the L level, it operates in a left-right inverted image display mode, and displays an image left-right inverted.

The electro-optical device 10 includes an image display unit 11
, A scanning line drive circuit 12, a first bidirectional shift register 13, a second bidirectional shift register 14, a first sampling circuit 15, and a second sampling circuit 16.
And a switching circuit 17. Reference numeral 18 denotes a first wiring group. The first wiring group 18 includes six signal lines 18a to 18a.
18f. Reference numeral 19 denotes a second wiring group, and the second wiring group 19 includes six wirings 19a to 19f.

The symbol SPS is a sampling start signal,
The symbol PRS is a precharge start signal. Sign V
ID1 to VID6 are image signals that have been converted from serial to parallel into six phases, and reference symbol VPS is a precharge potential. Symbol DIR is a scanning direction selection signal, and symbol HCK is a horizontal clock signal. The code VST is a vertical start signal and the code V
CK is a vertical clock signal.

The image display unit 11 includes a plurality of data lines Y1 to YN arranged in a row (in FIG. 1, Y1 to Y6 are shown).
And a plurality of scanning lines X1 to XM arranged in a row, a plurality of pixels LC arranged in a grid, and a plurality of thin film transistors TR provided corresponding to each pixel LC. The drain of the thin film transistor TR is connected to the data line Y, the gate is connected to the scanning line X, and the source is connected to the pixel electrode of the pixel LC.

The image display section 11 has data lines Y1 to Y on a substrate (not shown) made of hard glass or the like.
N, each scanning line X1 to XM, each pixel LC, each thin film transistor TR, a capacitance line (not shown), and the like are provided as needed. Then, a substrate (not shown) on which a thin film transistor or the like is formed and a substrate (not shown) made of glass or the like provided with a counter electrode or the like are stacked and arranged at a predetermined interval, and a liquid crystal material is sealed and sealed between the substrates. ing.

The scanning line driving circuit 12 is constituted by using a shift register or the like. The scanning line driving circuit 12 generates and outputs the scanning signals φV1 to φVM by sequentially shifting the vertical start signal VST based on the vertical clock signal VCK. The scanning signals φV1 to φVM are supplied to the respective scanning lines X1 to XM. Thus, line-sequential scanning of each of the scanning lines X1 to XM is performed.

The first bidirectional shift register 13 has a horizontal clock signal input terminal CLKIN, a start signal input terminal DATAIN, and a scanning direction selection signal input terminal DIR.
IN. The first bidirectional shift register 13 includes:
When the scanning direction selection signal input terminal DIRIN is set to the H level, it operates as a forward shift register that shifts in the first direction. In the operation state of the forward shift register, when an H-level output signal is supplied to the start signal input terminal DATAIN, the H-level output signal is sequentially synchronized with the horizontal clock signal supplied to the horizontal clock signal input terminal CLKIN. (The direction from the first stage to the last stage of the shift register). Therefore, the output signals AH1 to AH6 of each shift stage sequentially become H level in the order of their numbers. In other words, AH1, AH
, AH3,..., AHN are generated in the order of the output signals.

The first bidirectional shift register 13 operates as a reverse shift register that shifts in the second direction when the scanning direction selection signal input terminal DIRIN is set to L level. In the operation state as the backward shift register, when an H level signal is supplied to the start signal input terminal DATAIN, the H level signal is synchronized with the horizontal clock signal supplied to the horizontal clock signal input terminal CLKIN in the reverse direction ( (The direction from the tail to the head of the shift register). Therefore, the output signals AH1 to AH6 of each shift stage are sequentially H
Level. In other words, AHM, ..., AH6
Signals shifted in the order of AH5, AH4, AH3, AH2, and AH1 are generated. In addition, AS1 to AS6, BS1 to
The horizontal clock signal may be configured to generate a signal shifted so that BS6 is selected at the same time. In this case, the timing chart shows that the signals BH1 to BH6 in FIG.
(Not shown) occur simultaneously. Also, signals AH1 to AH6 are generated at the same time, and AH7 to AH1 are generated at the next timing.
2 (not shown) occur simultaneously. The same applies when the reverse shift is selected. When such simultaneous selection is performed, there is an effect that the drive frequency of the shift register can be reduced.

The second bidirectional shift register 14 has a horizontal clock signal input terminal CLKIN, a start signal input terminal DATAIN, and a scanning direction selection signal input terminal DIR.
IN. This second bidirectional shift register 14
The configuration and operation of the first bidirectional shift register 13
Is the same as In the operation state as a forward shift register, output signals shifted in the order of BH1, BH2, BH3,..., BHN are generated.
Output signals shifted in the order of BH4, BH3, BH2, and BH1 are generated.

The first sampling circuit 15 has a plurality of switch circuits AS1 to ASM. FIG. 1 shows first to sixth switch circuits AS1 to AS6. Each of the switch circuits AS1 to AS6 is configured using a thin film transistor and a transmission gate. Each of the switch circuits AS1 to AS6 is turned on when the control terminal is set to the H level, and is turned off when the control terminal is set to the L level.

One terminal of the first switch circuit AS 1 is connected to the first wiring 18 a of the first wiring group 18,
The other terminal of the switch circuit AS1 is connected to the first data line Y
Connected to 1. Second to sixth switch circuits AS2 to AS
One terminal of S6 is connected to the second to sixth wirings 18b to 18f, respectively, and the second to sixth switch circuits AS2 to
The other terminal of AS6 is connected to the second to sixth data lines Y2 to Y6.
Respectively.

The first output signal AH1 of the first bidirectional shift register 13 is supplied to the control terminal of the first switch circuit AS1. Second to sixth switch circuits AS2
To AS6 are supplied with the second to sixth output signals AH2 to AH6 of the first bidirectional shift register 13, respectively.

The same connection as above is repeated for the seventh and subsequent switch circuits (not shown) as a set of six switch circuits.

The second sampling circuit 16 has a plurality of switch circuits BS1 to BSM. FIG. 1 shows first to sixth switch circuits BS1 to BS6. Each of the switch circuits BS1 to BS6 is configured using a thin film transistor and a transmission gate. Each of the switch circuits BS1 to BS6 is turned on when the control terminal is set to H level, and is turned off when the control terminal is set to L level.

One terminal of the first switch circuit BS1 is connected to the sixth wiring 19f of the second wiring group 19,
The other terminal of the switch circuit AS1 is connected to the first data line Y
Connected to 1. Second to sixth switch circuits BS2 to B
One terminal of S6 is connected to the fifth to first wires 19e to 19a, respectively, and the second to sixth switch circuits BS2 to
The other terminal of BS6 is connected to the second to sixth data lines Y2 to Y6
Respectively.

The first output signal AH of the second bidirectional shift register 13 is provided to the control terminal of the first switch circuit BS1.
1 is supplied. Second to sixth switch circuits AS2 to AS
The control terminal of S6 includes the first bidirectional shift register 13
The second to sixth output signals AH2 to AH6 are respectively supplied.

The same connection as described above is repeated for the seventh and subsequent switch circuits (not shown) as a set of six switch circuits.

The sampling start signal SPS, the precharge start signal PRS, and the image signals VID1 to VID1 of each phase
VID6 and precharge potential VPS are supplied to switching circuit 17.

The switching circuit 17 includes a plurality of switching circuits, and based on a scanning direction selection signal DIR supplied to a switching control signal input terminal 17a, a sampling start signal SPS, a precharge start signal PRS, and an image of each phase. The supply destination of the signals VID1 to VID6 and the precharge potential VPS is switched.

The switching circuit 17 includes an input terminal for a sampling start signal SPS, an input terminal for a precharge start signal PRS, and image signals VID1 to VID for each phase.
6, an input terminal group for the precharge potential VPS, an input terminal for the signal supplied to the start signal input terminal DATAIN of the first bidirectional shift register 13, and a second
Signal input terminal D of the bidirectional shift register 14
An output terminal of a signal supplied to ATAIN, an output terminal of a signal supplied to each of the wirings 18a to 18f of the first wiring group 18, and an output terminal of a signal supplied to each of the wirings 19a to 19f of the second wiring group 19 And

The switching circuit 17 provides a scanning direction selection signal D
When the IR is set to the H level (when the standard image display mode is set), each switch circuit in the switching circuit 17 is in a switching state indicated by an arrow in the drawing. Then, in the switching state, the sampling start signal SP
S is supplied to the start signal input terminal DATAIN of the first bidirectional shift register 13, and the precharge start signal PRS is supplied to the start signal input terminal DATAIN of the second bidirectional shift register 14, and the image signal VID1 of each phase is supplied. To VID6 are the first to sixth of the first wiring group 18.
And the precharge potential VPS is supplied to the first to sixth wirings 1 of the second wiring group 19.
9a to 19f.

The switching circuit 17 provides a scanning direction selection signal D
When the IR is set to the L level (when the inverted standard image display mode is set), each switch circuit in the switching circuit 17 is in the opposite state to the switching indicated by the arrow in the figure.
In the switching state, the sampling start signal SPS is supplied to the start signal input terminal DATAIN of the second bidirectional shift register 14, and the precharge start signal PRS is supplied to the start signal input terminal DATAIN of the first bidirectional shift register 13. Supplied to
The image signals VID1 to VID6 of each phase are supplied to the second wiring group 19
Are supplied to the first to sixth wirings 19a to 19f, respectively, and the precharge potential VPS is
To the sixth wirings 18a to 18f.

The scanning direction selection signal DIR is input to the scanning direction selection signal input terminals DI of the bidirectional shift registers 13 and 14.
Each is supplied to RIN. Horizontal clock signal HCK
Are supplied to the horizontal clock signal input terminals CLKIN of the bidirectional shift registers 13 and 14, respectively.

The image signals VID1 to VID6 of each phase are
Are serial-parallel converted so that the standard image is displayed in the standard image display mode. Specifically, it is as follows. The image signal VID1 of the first phase is
The image signals supplied to the data lines Y1, Y7, Y13,... Are sequentially supplied at predetermined time intervals. The second-phase image signal VID2 is supplied to the data lines Y2, Y8, Y14,.
Are sequentially supplied at predetermined time intervals. The image signal VID3 of the third phase is connected to the data line Y
The image signals supplied to 3, Y9, Y15,... Are sequentially supplied at predetermined time intervals. Fourth phase image signal V
ID4 is an image signal supplied to the data lines Y4, Y10, Y16,... Sequentially supplied at predetermined time intervals. The fifth phase image signal VID5 is connected to the data lines Y5 and Y1.
, Y17,... Are sequentially supplied at predetermined time intervals. Sixth-phase image signal VID6
Are supplied sequentially to the data lines Y6, Y12, Y18,... At predetermined time intervals.

The precharge start signal PRS is supplied during the horizontal blanking period, and the sampling start signal SPS is supplied.
Are supplied in synchronization with the beginning of the horizontal effective display period. It is preferable to provide a predetermined time difference between the precharge start signal PRS and the sampling start signal SPS. Thus, since an actual image signal is not selected during the precharge period, display abnormality does not occur. Specifically, the precharge start signal PRS
Is supplied first, and then a sampling start signal SPS is supplied in synchronization with the beginning of the horizontal effective display period.

The precharge potential VPS is a signal for precharging each pixel LC, and a DC voltage at which the transmittance of the liquid crystal becomes, for example, about 50% is used as the precharge potential VPS. The image signal V is applied to each pixel LC.
By supplying each pixel LC to a predetermined potential before supplying the voltages of ID1 to VID6, the image signal VI
Charges and discharges based on D1 to VID6 can be reduced. As a result, the image signals VID1 to VID
It is possible to prevent the voltage level of ID6 from fluctuating and prevent the quality of the displayed image from deteriorating.

Next, the operation of the electro-optical device 10 shown in FIG. 1 will be described. When displaying a standard image using the electro-optical device 10, the scanning direction selection signal DIR is set to the H level. Thus, the shift direction of each of the bidirectional shift registers 13 and 14 is set to the forward direction. When the scanning direction selection signal DIR is set to the H level, the image signals VID1 to VID6 of each phase are supplied to the respective wirings 18a to 18f of the first wiring group 18 via the switching circuit 17, and the first The sampling start signal SPS is supplied to the start signal input terminal DATAIN of the bidirectional shift register 13 via the switching circuit 17. Furthermore, the second
The pre-sharge potential VPS is supplied to each of the wirings 19a to 19f of the wiring group 19, and the pre-charge start signal PRS is supplied to the start signal input terminal DATAIN of the second bidirectional shift register 14.

FIG. 2 is a timing chart showing the operation of the electro-optical device shown in FIG. 1 in the standard image display mode.
2A shows the horizontal clock signal VCK, FIG. 2B shows the precharge start signal PRS, and FIG.
Output signals BH1-BH of the bidirectional shift register 14 of FIG.
6 is shown. FIG. 2D shows the sampling start signal SPS, and FIG. 2E shows the output signals AH1 to AH6 of the first bidirectional shift register 13. FIG.
(F) shows the state of each data line Y1 to Y6.

The second bidirectional shift register 14 applies the precharge start signal PRS supplied to the start signal input terminal DATAIN to the horizontal clock signal input terminal CL.
By sequentially shifting in the forward direction in synchronization with the horizontal clock signal HCK supplied to the KIN, the output signals BH1 to BH6 are sequentially output as shown in FIG.

The second sampling circuit 16 shown in FIG.
Are sequentially turned on based on the output signals BH1 to BH6 of the second bidirectional shift register 14. Thereby, the precharge signal VPS supplied to each of the wirings 19a to 19f of the second wiring group 19 is sequentially supplied to each of the data lines Y1 to Y6.

That is, FIGS. 2C and 2F
The precharge potential VPS is supplied to the data line Y1 based on the output signal BH1 of the second bidirectional shift register 14, as shown in FIG. Here, if the H-level scanning signal φV1 is supplied to the first scanning line X1 shown in FIG. 1, the data line Y is supplied via the thin film transistor TR.
The precharge potential VPS is supplied to the pixel LC specified by 1 and the scanning line X1, and the pixel LC is precharged. Similarly, as shown in FIGS. 2C and 2F, the precharge potential VPS is applied to each data line Y2 to Y6 based on each output signal BH2 to BH6 of the second bidirectional shift register 14.
Are sequentially supplied, and the corresponding pixels are sequentially precharged.

The first bidirectional shift register 13 converts the sampling start signal SPS supplied to the start signal input terminal DATAIN into the horizontal clock signal input terminal CL.
By sequentially shifting in the forward direction in synchronization with the horizontal clock signal HCK supplied to the KIN, the output signals AH1 to AH6 are sequentially output as shown in FIG.

The first sampling circuit 15 shown in FIG.
Among the switch circuits AS1 to AS6 are sequentially turned on based on the output signals AH1 to AH6 of the first bidirectional shift register 13. As a result, the image signals VID1 to VID6 of each phase supplied to the wirings 18a to 18f of the first wiring group 18 are sequentially supplied to the data lines Y1 to Y6.

That is, FIGS. 2E and 2F
As shown in (1), the first-phase image signal VID1 is supplied to the data line Y1 based on the output signal AH1 of the first bidirectional shift register 13. Here, if the H-level scanning signal φV1 is supplied to the first scanning line X1 shown in FIG. 1, the pixel LC specified by the data line Y1 and the scanning line X1 is supplied via the thin film transistor TR. The image signal VID1 of the first phase is supplied, and the image signal VID1 is supplied to the pixel.
Is written. 2 (e) and FIG.
As shown in (f), the first bidirectional shift register 13
Of each data line Y2 based on the output signals AH2 to AH6 of
To Y6 are sequentially supplied with the image signals VID2 to VID6, and the image signals VID2 to VID6 are written to the corresponding pixels.

In the standard image display mode in which the scanning direction selection signal DIR is set to the H level, the image signals VID1 to VID6 are sequentially supplied from the first data line Y1 to the last data line YN in one horizontal scanning period. Is done. That is, horizontal scanning is performed from the first data line Y1 to the final data line YN, and an image signal is written to each pixel in a dot-sequential manner. Thereby, a standard image can be displayed.

When a left-right inverted image is displayed using the electro-optical device 10, the scanning direction selection signal DIR is set to L.
Set to level. As a result, the shift directions of the bidirectional shift registers 13 and 14 are set in opposite directions. When the scanning direction selection signal DIR is set to L level, each of the wirings 19a to 19a of the second wiring group 19 is switched through the switching circuit 17.
9f are supplied with the image signals VID1 to VID6 of the respective phases, and the sampling start signal S is supplied to the start signal input terminal DATAIN of the second bidirectional shift register 14.
PS is supplied. Further, the precharge potential VPS is supplied to each of the wirings 18a to 18f of the first wiring group 18, and the precharge start signal P is supplied to the start signal input terminal DATAIN of the first bidirectional shift register 13.
An RS is provided.

FIG. 3 is a timing chart showing the operation of the electro-optical device shown in FIG. 1 in the reverse image display mode.
3A shows the horizontal clock signal HCK, FIG. 3B shows the precharge start signal PRS, and FIG.
Output signals AH1 to AH of the bidirectional shift register 14 of FIG.
6 is shown. FIG. 3D shows the sampling start signal SPS, and FIG. 3E shows the output signals BH1 to BH6 of the second bidirectional shift register 13. FIG.
(F) shows the state of each data line Y1 to Y6.

The first bidirectional shift register 13 converts the precharge start signal PRS supplied to the start signal input terminal DATAIN into the horizontal clock signal input terminal CL.
By sequentially shifting in the reverse direction in synchronization with the horizontal clock signal HCK supplied to the KIN, the output signals AH6 to AH1 are sequentially output as shown in FIG.

Although FIG. 3 shows that the output signal AH6 is output immediately in synchronization with the horizontal clock signal HCK when the precharge start signal PRS is supplied, actually, the first bidirectional shift is performed. Since the precharge start signal PRS is sequentially shifted from the tail stage to the head stage of the register 13, a predetermined time is required from when the precharge start signal PRS is supplied to when the output signal AH6 is generated.

The first sampling circuit 15 shown in FIG.
Are sequentially turned on based on the output signals AH6 to AH1 of the first bidirectional shift register 14. As a result, the precharge potential VPS supplied to the wirings 18a to 18f of the first wiring group 18 is sequentially supplied to the data lines Y6 to Y1.

That is, FIGS. 3C and 3F
The precharge signal VPS is supplied to the data line Y6 based on the output signal AH6 of the first bidirectional shift register 13 as shown in FIG. Here, if the H-level scanning signal φV1 is supplied to the first scanning line X1 shown in FIG. 1, the data line Y is supplied via the thin film transistor TR.
The precharge signal VPS is supplied to the pixel LC specified by the scanning line X1 and the pixel LC, and is precharged. Similarly, as shown in FIGS. 3C and 3F, the precharge potential VPS is applied to the data lines Y5 to Y1 based on the output signals AH5 to AH1 of the first bidirectional shift register 13.
Are sequentially supplied, and the corresponding pixels are sequentially precharged.

The second bidirectional shift register 14 converts the sampling start signal SPS supplied to the start signal input terminal DATAIN into the horizontal clock signal input terminal CL.
By sequentially shifting in the reverse direction in synchronization with the horizontal clock signal HCK supplied to the KIN, the output signals BH6 to BH1 are sequentially output as shown in FIG.

Although FIG. 3 shows that the output signal BH6 is output immediately in synchronization with the horizontal clock signal HCK when the sampling start signal SPS is supplied, actually, the second bidirectional shift register is provided. Since the sampling start signal SPS is sequentially shifted from the tail stage to the beginning stage of the fourteenth stage, a predetermined time is required from when the sampling start signal SPS is supplied to when the output signal BH6 is generated.

The second sampling circuit 16 shown in FIG.
Are sequentially turned on based on the output signals BH6 to BH1 of the second bidirectional shift register 16. As a result, the image signals VID1 to VID6 of each phase supplied to the wirings 19a to 19f of the second wiring group 19 are sequentially supplied to the data lines Y6 to Y1.

That is, FIGS. 3E and 3F
As shown in (1), the first-phase image signal VID1 is supplied to the data line Y6 based on the output signal BH6 of the second bidirectional shift register 14. Here, if the H-level scanning signal φV1 is supplied to the first scanning line X1 shown in FIG. 1, the data line Y6 and the pixel LC specified by the scanning line X1 are supplied via the thin film transistor TR. The image signal VID1 of the first phase is supplied, and the image signal VID1 is supplied to the pixel.
Is written. Similarly, FIG. 3 (e) and FIG.
As shown in (f), the second bidirectional shift register 14
Of each data line Y5 based on the output signals BH5 to BH1 of
To Y1 are sequentially supplied with the image signals VID2 to VID6, and the image signals VID2 to VID6 are written to the corresponding pixels.

In the left-right inverted image display mode in which the scanning direction selection signal DIR is set to the L level, the image signals VID1 to VID6 are sequentially supplied from the data line YN to the first data line Y1 during one horizontal scanning period. You. That is,
Horizontal scanning is performed in a direction opposite to the standard image display mode, and an image signal is written to each pixel in a dot-sequential manner. This allows
A horizontally inverted image can be displayed.

FIG. 4 is a block diagram of an electro-optical device according to the second embodiment. The electro-optical device 20 shown in FIG. 4 includes an image display unit 21, a scanning line driving circuit 22, a bidirectional shift register 23 for sampling control, a bidirectional shift register 24 for precharge control, a sampling circuit 25, It comprises a charge circuit 26, an image signal phase switching circuit 27, an image wiring group 28, and a precharge potential line 29. The image signal line group 28 includes six image signal lines 28a to 28f. The configurations of the image display unit 21 and the scanning line driving circuit 22 are the same as those of the image display unit 11 and the scanning line driving circuit 12 shown in FIG.

When the scanning direction selection signal DIR supplied to the scanning direction selection signal input terminal DIRIN is at H level (when the standard image display mode is designated), the sampling control bidirectional shift register 23 outputs a start signal. The sampling start signal SPS supplied to the input terminal DATAIN is shifted in the forward direction based on the horizontal clock signal HCK supplied to the horizontal clock signal input terminal CLKIN, and the outputs AH1 to AH6 of each shift stage are sequentially generated in that order. .

When the scanning direction selection signal DIR supplied to the scanning direction selection signal input terminal DIRIN is at L level (when the inverted image display mode is designated), the sampling control bidirectional shift register 23 outputs a start signal. The sampling start signal SPS supplied to the input terminal DATAIN is shifted in the reverse direction based on the horizontal clock signal HCK supplied to the horizontal clock signal input terminal CLKIN, and the outputs AH6 to AH1 of each shift stage are sequentially generated in that order. .

The precharge control bidirectional shift register 24 starts when the scanning direction selection signal DIR supplied to the scanning direction selection signal input terminal DIRIN is at the H level (when the standard image display mode is designated). The precharge start signal PRS supplied to the signal input terminal DATAIN is shifted in the forward direction based on the horizontal clock signal HCK supplied to the horizontal clock signal input terminal CLKIN, and outputs BH1 to BH6 to BHN of each shift stage.
Are sequentially generated in that order.

The precharge control bidirectional shift register 24 starts when the scanning direction selection signal DIR supplied to the scanning direction selection signal input terminal DIRIN is at L level (when the inverted image display mode is designated). The precharge start signal PRS supplied to the signal input terminal DATAIN is shifted in the reverse direction based on the horizontal clock signal HCK supplied to the horizontal clock signal input terminal CLKIN, and the outputs BHN to BH6 to BH1 of each shift stage are shifted.
Are sequentially generated in that order.

The sampling circuit 25 includes a plurality of switch circuits AS1 to AS6 to ASN. The first switch circuit AS1 transfers the image signal supplied to the first image signal line 28a to the first data line Y1 based on the first stage output signal AH1 of the sampling control bidirectional shift register 23. Supply. The second switch circuit AS2 has 2
Based on the output signal AH2 of the second stage, the second image signal line 2
The image signal supplied to 8b is supplied to the second data line Y2. Similarly, the third to sixth switch circuits AS3 to AS3
The AS 6 converts the image signals supplied to the third to sixth image signal lines 28c to 28f to the third to sixth data lines Y3 to Y6 based on the output signals AH3 to AH6 of the third to sixth stages.
Respectively. Although not shown, six switch circuits are also connected to the seventh switch circuit and thereafter.
Similar connections are repeatedly made as a set.

The precharge circuit 26 includes a plurality of switch circuits BS1 to BS6 to BSN. The first switch circuit BS1 outputs the precharge potential VP supplied to the precharge potential line 29 based on the first-stage output signal BH1 of the precharge control bidirectional shift register 24.
S is supplied to the first data line Y1. The second switch circuit BS2 supplies the precharge potential VPS to the second data line Y2 based on the output signal BH2 of the second stage.
Similarly, the third to sixth to Nth switch circuits BS3 to BS
6 to BSN are output signals BH3 to BH of the third to sixth to Nth stages, respectively.
The precharge signal VPS is supplied to the third to sixth to Nth data lines Y3 to Y6 to YN based on H6 to BHN.

The image signal phase order permutation circuit 27 includes an input terminal group for the image signals VID1 to VID6 of each phase, an output terminal group for supplying image signals to the image signal lines 28a to 28f, A plurality of switch circuits provided between the output terminal group.

The image signal phase sequence changing circuit 27 is provided with a scanning direction selection signal DIR supplied to a phase sequence designating signal input terminal 27a.
Is at the H level (when the standard image display mode is designated), the first-phase image signal VID1 is supplied to the first image signal line 28a, and the second-phase image signal VID2 is supplied to the second image signal line 28a.
, And similarly supply the third to sixth phase image signals VID3 to VID6 to the third to sixth image signal lines 28c to 28f, respectively.

The image signal phase sequence changing circuit 27 is provided with a scanning direction selection signal DIR supplied to a phase sequence designation signal input terminal 27a.
Is at the L level (when the inverted image display mode is designated), the first phase image signal VID1 is supplied to the sixth image signal line 28f, and the second phase image signal VID2 is supplied to the fifth image signal line 28f.
, And similarly supply the third to sixth phase image signals VID3 to VID6 to the fourth to first image signal lines 28d to 28a, respectively.

Next, the operation of the above configuration will be described.
In the standard image display mode in which the scanning direction selection signal DIR is set to the H level, the first to sixth image signal lines 28a to 28a
8f, the first to sixth phase image signals VID1 to VID6 are supplied in that order. Since the bidirectional shift register for sampling control 23 performs a shift operation in the forward direction, the output signals AH1 to AH6 of each shift stage are sequentially output in that order. The sampling circuit 25 converts the first to sixth phase image signals VID1 to VID6 into first to sixth data lines Y1 to Y6 based on the output signals AH1 to AH6 of each shift stage.
Sequentially. Therefore, an image signal is written to each pixel in a dot-sequential manner from the first data line Y1 to the data line YN. Therefore, a standard image can be displayed.

In the inverted image display mode in which the scanning direction selection signal DIR is set to L level, the image signal phase order permutation circuit 27 causes the first to sixth phase image signals VID1 to VID to be set.
The phase order of ID6 is interchanged and supplied to the first to sixth image signal lines 28a to 28f. Since the sampling control bidirectional shift register 23 performs a shift operation in the reverse direction, the output signals AH6 to AH1 of each shift stage are sequentially output in that order. The sampling circuit 25 sequentially supplies the sixth-phase to first-phase image signals VID6 to VID1 to the sixth to first data lines Y6 to Y1 based on the output signals AH6 to AH1 of each shift stage. Therefore, data line YN
, An image signal is written to each pixel in a dot-sequential manner toward the data line Y1.

Even if only the scanning direction of the data lines is reversed, it is not possible to obtain an image in which the right and left are inverted exactly. The electro-optical device 20 according to the second embodiment scans in the direction from the data line YN to the data line Y1 because the phase order of the image signals supplied to the image signal lines 28a to 28f is inverted in the inverted display mode. Then, each image signal can be written in the correct phase sequence. Thereby, a left-right inverted image can be displayed.

By supplying the precharge signal PRS prior to the sampling start signal SPS, an image signal can be written to each data line after each data line is precharged.

In FIGS. 1 and 4, a scanning direction selection signal DIR is supplied from an image display control unit or the like (not shown), and the mode is switched between the standard image display mode and the inverted image display mode according to the logic level of the scanning direction selection signal DIR. Although the configuration is shown, the scanning direction selection signal DI is supplied to the electro-optical devices 10 and 20.
A switch or the like for setting the logical level of R may be provided so that the display mode can be set on the electro-optical devices 10 and 20 side. (Configuration of electronic device) As an electronic device having such a configuration,
The projection type display device shown in FIG. 5 can be used.
FIG. 5 is a schematic configuration diagram illustrating a main part of the projection display device. In the figure, 1102 is a light source, 1108 is a dichroic mirror, 1106 is a reflection mirror, 1122 is an entrance lens, 1123 is a relay lens, 1124 is an exit lens,
Reference numerals 100R, 100G, and 100B denote liquid crystal light modulators including a liquid crystal device as the above-described electro-optical device, 1112 denotes a cross dichroic prism, and 1114 denotes a projection lens. The light source 1102 includes a lamp such as a metal halide and a reflector that reflects light from the lamp. The dichroic mirror 1108 that reflects blue light and green light
While transmitting the red light of the light fluxes from No. 2 and reflecting the blue light and the green light. The transmitted red light is reflected by the reflection mirror 1106, and the liquid crystal light modulator 10 for red light is transmitted.
It is incident on 0R. On the other hand, the dichroic mirror 110
Of the color light reflected by 8, the green light is reflected by the green light reflecting dichroic mirror 1108 and is incident on the liquid crystal light modulator for green light 100G. On the other hand, the blue light also passes through the second dichroic mirror 1108. For the blue light, the input lens 1122, the relay lens 1123, the output lens 11
24 is provided, and blue light is incident on the liquid crystal light modulator for blue light 100B via this. The three color lights modulated by each light modulator are cross dichroic prism 1112
Incident on. This prism is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The synthesized light is projected on a screen 1120 by a projection lens 1114 which is a projection optical system, and an image is enlarged and displayed. In addition to the projection display device, examples of the electronic device include a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, and the like. It goes without saying that the electro-optical device according to the present invention can be applied to equipment. The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or spirit of the invention which can be read from the claims and the entire specification, and the electric power accompanied by such a change can be obtained. An optical device is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electro-optical device according to a first embodiment.

FIG. 2 is a timing chart showing an operation of the electro-optical device shown in FIG. 1 in a standard image display mode.

FIG. 3 is a timing chart showing an operation of the electro-optical device shown in FIG. 1 in a reverse image display mode.

FIG. 4 is a block diagram of an electro-optical device according to a second embodiment.

FIG. 5 is a block diagram in which the electro-optical device of the present invention is used in a projection display device.

FIG. 6 is a block diagram of a conventional electro-optical device.

FIG. 7 is a block diagram of a conventional electro-optical device that performs image display based on a plurality of image signals subjected to serial-parallel conversion.

[Explanation of symbols]

 10, 20 Electro-optical device 11, 21 Image display unit 12, 22 Scan line drive circuit 13 First bidirectional shift register 14 Second bidirectional shift register 15 First sampling circuit 16 Second sampling circuit 17 Switching circuit 18 First Wiring Group 19 Second Wiring Group 23 Bidirectional Shift Register for Sampling Control 24 Bidirectional Shift Register for Precharge Control 25 Sampling Circuit 26 Precharge Circuit 27 Image Signal Phase Reordering Circuit 28 Image Signal Line Group 29 Pre Charge potential lines AS1 to AS6, BS1 to BS6 Switch circuit DIR Scan direction selection signal HCK Horizontal clock signal PRS Precharge start signal SPS Sampling start signal VID1 to VID6 Image signal VPS Precharge potential

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NC22 NC23 NC34 NC49 ND05 ND09 ND15 ND39 ND60 5C006 AB01 AC09 AC21 AF22 AF25 BB16 BC06 BC23 BF03 BF11 EC11 FA31 5C080 AA10 BB05 DD12 DD30 EE32 FF07 JJ06 JJ04 JJ04

Claims (9)

[Claims] A plurality of data lines to which an image signal is supplied; a plurality of scanning lines to which a scanning signal is supplied; switching means connected to each of the data lines and each of the scanning lines; An electro-optical device including a connected pixel electrode, comprising: a first and a second bidirectional shift register; a first and a second wiring group; and an output timing of the first bidirectional shift register. A first sampling circuit for transmitting the state of the potential of the first wiring group to the data line; and a potential of the second wiring group based on an output timing of the second bidirectional shift register. A second sampling circuit for transmitting a state to the data line; and, in a first display mode, shifting the first and second bidirectional shift registers in a first direction. Sampling start signal register, the second
A precharge start signal is supplied to the shift register, a potential serving as an image signal is supplied to the first wiring group, and a precharge potential is supplied to the second wiring group.
In the case of the second display mode, the first and second bidirectional shift registers are shifted in a second direction, and a sampling start signal and the first
A switching circuit that supplies a precharge start signal to the shift register, supplies a potential serving as an image signal to the second wiring group, and supplies a precharge potential to the first wiring group. An electro-optical device characterized by the above-mentioned. 2. The electro-optical device according to claim 1, wherein the first and second bidirectional shift registers are driven by a common clock signal. 3. The electro-optical device according to claim 1, wherein the shift directions of the first and second bidirectional shift registers are set by a common scanning direction selection signal. 4. The first bidirectional shift register is configured to supply an output signal to the first sampling circuit so that a potential of the first wiring group is sequentially transmitted to a plurality of the data lines. The second bidirectional shift register is configured to supply an output signal to the second sampling circuit so that a potential of the second wiring group is sequentially transmitted to a plurality of the data lines. An electro-optical device according to claim 1. 5. The first bidirectional shift register is configured to supply an output signal to the first sampling circuit such that a potential of the first wiring group is simultaneously transmitted to a plurality of the data lines. The second bidirectional shift register is configured so that the potential of the second wiring group is simultaneously transmitted to a plurality of the data lines.
4. The electro-optical device according to claim 1, wherein an output signal is supplied to the second sampling circuit. 6. The switching circuit selectively supplies one of a sampling start signal and a precharge start signal to the first shift register based on the scanning direction selection signal, and performs sampling to the second shift register. Selectively supplying the other of a start signal and a precharge start signal to the first wiring group based on the scanning direction selection signal;
6. The electro-optical device according to claim 5, wherein one of the image signal and the precharge potential is selectively supplied, and the other of the display data and the precharge potential is selectively supplied to the second wiring group. apparatus. 7. A plurality of data lines to which an image signal is supplied, a plurality of scanning lines to which a scanning signal is supplied, switching means connected to each data line and each scanning line, and In the electro-optical device including the connected pixel electrodes, a signal line group and a plurality of serial-parallel-converted image signals in a first display mode are supplied to the signal line group in a first order. In the case of the second display mode, the plurality of serial-parallel-converted image signals are transferred to the signal line group by the first display mode.
And an image signal phase order permutation circuit for supplying a second order reverse to the order of the first display mode, wherein a shift direction is set in a first direction in the first display mode, and a shift direction is set in the second display mode. A bidirectional shift register for sampling control in which a shift direction is set in two directions; and a sampling for transmitting the state of the potential of the signal line group to the data lines based on the output timing of the bidirectional shift register for sampling control. An electro-optical device comprising a circuit. 8. A shift direction is set to a first direction in the first display mode, and the shift direction is set to a second direction in the second display mode, and a precharge start signal is designated. A pre-charge control bidirectional shift register that sequentially outputs a pre-charge timing signal from each shift stage by shifting in a given shift direction; and a pre-charge that supplies a pre-charge potential to the data line based on the pre-charge timing signal. The electro-optical device according to claim 7, further comprising a charge circuit. 9. An electronic apparatus comprising the electro-optical device according to claim 1. Description: