JP2001236781A - Magnetic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the cell output voltage at the time of reading, and to improve the signal-to-noise ratio without increasing the power consumption at the time of reading, to achieve low power consumption and high speed. Realizes readability. Kind Code: A1 A magnetic memory device comprising a plurality of TMR elements in which a pinned layer having a fixed magnetization direction and a recording layer whose magnetization direction changes due to an external magnetic field are stacked to form a double or more tunnel junction. The memory cell 201, which is a unit for recording information, has two T cells having the same resistance value and magnetoresistance change rate.
MR elements 11 and 21 and TMR elements 11 and 21
One end in the stacking direction is connected to another data line DL, / DL, and the other end is connected to the same bit line BL via the same select transistor 31. Information recording is TMR
The information is read out so that the magnetization directions of the recording layers of the elements 11 and 21 are always kept antiparallel.
This is performed by detecting a difference in current flowing through L.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information reproducing technique using a ferromagnetic material, and more particularly to a magnetic memory device using a ferromagnetic tunnel junction.

[0002]

2. Description of the Related Art Magnetic random access memories (hereinafter referred to as M
RAM (abbreviated as RAM) is a general term for a solid-state memory that can rewrite, hold, and read recorded information at any time by using the magnetization direction of a ferromagnetic material as a record carrier for information. M
In a RAM, information is recorded in correspondence with binary information "1" and "0" whether the magnetization direction of a ferromagnetic material constituting a memory cell is parallel or antiparallel to a certain reference direction.

[0003] Writing of recorded information is performed by reversing the magnetization direction of the ferromagnetic material of each cell by a current magnetic field generated by applying a current to a write line arranged in a cross stripe shape. This is a non-volatile memory in which the power consumption during recording and holding is zero in principle, and the recording and holding are performed even when the power is turned off.

In reading recorded information, a phenomenon in which the electric resistance of a memory cell changes depending on the relative angle between the magnetization direction of a ferromagnetic material constituting the cell and a sense current or the relative angle of magnetization between a plurality of ferromagnetic layers. This is performed using the so-called magnetoresistance effect. In the read operation, the magnetization direction of the ferromagnetic material is changed by the current magnetic field in the same state as when writing, with the sense current flowing through the ferromagnetic material constituting each cell, and the change in the electrical resistance at that time is regarded as a voltage change. Detect and perform. By setting the magnitude of the magnetic field at this time smaller than the ferromagnetic coercive force, nondestructive reading can be realized.

When this type of MRAM is compared with a conventional semiconductor memory using a dielectric, its functions are as follows: (a) it is completely non-volatile and can be rewritten 10 ¹⁵ times or more. (B) Nondestructive reading is possible, and a refresh cycle is not required, so that a reading cycle can be shortened. (C) The resistance to radiation is higher than that of a charge storage type memory cell.

It has many advantages, such as: The integration degree per unit area of MRAM, writing and reading time are
It is expected that it can be almost the same as a DRAM. Therefore, taking advantage of the great feature of non-volatility, an external recording device for portable digital audio equipment and a wireless IC
It is expected to be applied to a card and further to a main memory for a mobile PC.

In an MRAM having a recording capacity of about 1 Mb which is currently being studied for practical use, a giant magnetoresistive effect (hereinafter, abbreviated as GMR effect) is used for reading cell record information. As an MRAM cell using an element exhibiting the GMR effect (hereinafter abbreviated as GMR element), a Pseudo Spin-Valve structure (for example, IEEE T
rans.Mag., 33, 3289 (1997). Using a three-layer film having antiferromagnetic interlayer coupling (for example, IEEE Trans.Com)
p, Pac. Manu. Tech. Pt. A, 17, 373 (1994). (See, for example, IEEE Trans. Mag., 33, 3295 (1997).), Which has a Spin-Va1ve structure using a hard magnetic material as a pinning layer.

[0008] The value of the GMR effect of a non-bonded NiFe / Cu / Co three-layer film, which is currently often used as a GMR element, is about 6 to 8%. For example, the above Pseud
In an MRAM cell using the oSpin-Valve structure, a resistance change rate of 5% or more is effectively realized by controlling the magnetization distribution when reading recorded information. However,
Generally, the sheet resistance of a GMR element is about several tens Ω / □. Therefore, even assuming a sheet resistance of 100Ω / □ and a resistance change rate of 5%, a cell read signal for a sense current of 10 mA is only 5 mV at most. Current,
In MOS type field effect transistors that have been put into practical use,
Value of the source-drain current I _s is proportional to the ratio of the channel width W and channel length L (WL), W = 3.3μ
m, the value of I _s at L = 1 [mu] m is approximately 0.1 mA.
Therefore, the value of the sense current of 10 mA used here is extremely excessive for a transistor formed with a processing size of a submicron rule.

In order to solve this problem, in an MRAM cell using a GMR element, a method of connecting a plurality of GMR elements in series to form a data line is used (for example, IE).
EE Trans.Comp.Pac.Manu.Tech.pt.A, 17,373 (1994).). However, when memory cells are connected in series,
There is a disadvantage that the power consumption efficiency at the time of reading is greatly reduced.

In order to solve these problems, instead of the GMR effect, a ferromagnetic tunnel effect (Tunnel Magneto-Resista
nce: hereinafter abbreviated as TMR effect). An element exhibiting the TMR effect (hereinafter referred to as TM
The R element is mainly composed of a three-layer film composed of a ferromagnetic layer 1 / an insulating layer / a ferromagnetic layer 2, and current flows through the insulating layer by tunneling. The tunnel resistance changes in proportion to the cosine of the relative angle between the magnetizations of the two ferromagnetic metal layers, and takes a maximum value when the magnetizations are antiparallel.

For example, NiFe / Co / Al ₂ O ₃ / C
In an o / NiFe tunnel junction, a resistance change rate exceeding 25% has been found in a low magnetic field of 500 e or less (see, for example, IEEE Trans. Mag., 33.3553 (1997).). T
The cell resistance of the MR element is typically determined by the junction area (μ
10 ² to 10 ⁶ Ω per m ² ). Therefore, suppose that the resistance value is 10 kΩ and the resistance change rate is 25 in a 1 μm ² cell.
%, A cell read signal of 25 mV can be obtained with a sense current of 10 μA.

In an MRAM cell array using TMR elements, a plurality of TMR elements are connected in parallel on a data line. The detailed structure is as follows: (1) A semiconductor element for selection is arranged in each TMR element. (2) A selection transistor is arranged for each data line. (3) A plurality of TMR elements are arranged in a matrix, and a selection transistor is arranged for each row data line and each column data line (for example, see J. App1. Phys., 81.3758 (1997)). Has been proposed. Among them, the method (1) has the most excellent characteristics in terms of cell output voltage and power consumption efficiency at the time of reading. However, in the MRAM cell array of the method (1), it is necessary to supply a current to the semiconductor element connected to the TMR element at the time of reading. As a semiconductor element,
In addition to MOS field-effect transistors, diode elements in which the gate and drain of the field-effect transistor are short-circuited,
Further, a diode element using a pn junction or a Schottky junction is used. Therefore, when the characteristics of the semiconductor elements vary, noise caused by the variations cannot be ignored.

For example, in the case of a MOS transistor, 0.
In the 25 μm rule, the voltage drop between the source and drain is 1
It reaches 00mV or more. That is, 10
If there is a% variation, this will result in noise of 10 mV or more. In addition to this, noise coupled to the data line, noise due to variation in the characteristics of the sense amplifier, etc.
The noise level is> 1 in consideration of noise generated in peripheral circuits.
It becomes 0 mV, and only a signal-to-noise ratio of about several dB can be obtained with the current cell output voltage of about 20 to 30 mV.

In order to improve the signal-to-noise ratio, a conventional M
In the RAM cell array, the output voltage V of a single selected memory cell is compared with a reference voltage V _REF, and the difference voltage V
A method of differentially amplifying _sig is often used. This is for the first purpose to remove noise generated in the data line pair connected to the memory cell, and secondly for the cell output voltage V due to the characteristic variation of the sense line driving or cell selecting semiconductor element.
The purpose is to remove the offset of. Reference voltage V
_As a circuit for generating _REF , a dummy cell is used in addition to a circuit using a semiconductor element. However, in this method, the selected memory cell and the reference voltage generation circuit are connected to separate cell selection semiconductor elements, respectively, and the cell output voltage V
It is not possible to completely remove the offset of

Furthermore, in the prior art, the reference voltage V _REF is
The cell output voltage V _F corresponding to the cell information “1”, “0”,
It is common to use an intermediate voltage of V _AF . For example, if the current sense, voltage detection, the sense current value I _s, the resistance value of the TMR element used in the cell R, the magnetoresistance change rate and MR, V _F, V _AF is as follows , V _F = R (1−MR / 2) × I _s (1) V _AF = R (1 + MR / 2) × I _s (2)

Assuming that the reference voltage is an intermediate voltage between V _F and V _AF , the difference voltage input to the sense amplifier is as follows.

V _sig = R × MR × I _s / 2 (3) The denominator 2 is because the reference voltage V _REF is set to the intermediate voltage. Voltage sensing, in the case of the current detection, the bias voltage V _bias, when the load resistance for current detection and R _L, likewise _{V F = V bias × R L} / R (1-MR / 2) ... (4) V _AF = _Vbias × _RL / [R (1 + MR / 2)] (5) _Vsig = _Vbias × _RL / R × MR / 2 (6) However, it was considered that MR ² << 1 in the process of deriving equation (6).

Therefore, in the prior art, only half of the magnetoresistance ratio of the TMR element can be used.

In order to solve these problems, for example, a ferromagnetic or antiferromagnetically coupled T
A method of using an MR element and simultaneously using a current magnetic field when reading information has been considered (for example, US Pat. No. 5,734,605).
No.). However, in this method, power consumption at the time of reading becomes large, and it is not suitable for application to a portable device.

A method is also disclosed in which a memory cell is formed by arranging a selection transistor in each of two TMR elements (for example, ISSCC 2000 Digest paper TA7.2).
reference). In this method, writing is performed with the magnetization directions of the recording layers of the two TMR elements always kept antiparallel. That is, complementary writing is used in which the magnetization arrangement of one of the elements is always antiparallel and the other is in a parallel state. In this method, the outputs from the two elements are differentially amplified to remove common-mode noise and improve S / N. However,
Because two selection transistors are used in one cell,
There is a problem that the cell area increases and the degree of integration decreases.

[0021]

As described above, the TMR
By applying the element to a memory cell, it is possible to simultaneously reduce the sense current at the time of reading and increase the cell output signal, and realize a higher density MRAM as compared with the MRAM using the GMR effect conventionally used. It is possible to provide. However, even when a TMR element is used for a memory cell, the cell output voltage is about several tens of mV, and noise due to variation in characteristics of a semiconductor element for driving a sense line or cell selection, and noise from data lines and peripheral circuits. Considering the magnitude of the above, a sufficient signal-to-noise ratio has not been obtained at present. In order to improve the signal-to-noise ratio, a method in which a current magnetic field is used together has been devised, but has a drawback that power consumption during reading increases.

The present invention has been made in consideration of the above circumstances, and has as its object to increase the cell output voltage at the time of reading and increase power consumption at the time of reading. It is an object of the present invention to provide a magnetic memory device which can improve the signal-to-noise ratio without any problem and has both low power consumption and high-speed readability.

[0023]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, according to the present invention, a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field are laminated to form a plurality of tunnel junctions each having a single or double or more tunnel junction. A memory cell, which is a unit for recording information, includes first and second tunnel junctions, and one end of the first tunnel junction in the stacking direction and the second tunnel junction are connected to each other. One end in the stacking direction is connected to another data line, and the other end in the stacking direction of the first tunnel junction and the other end in the stacking direction of the second tunnel junction are connected via the same cell selecting semiconductor element. It is characterized by being connected to a bit line.

According to the present invention, a plurality of tunnel junctions each having a single or double or more tunnel junction are formed by laminating a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field. A magnetic memory device comprising a plurality of magnetic memory cell arrays, wherein the magnetic memory cell array comprises a plurality of sub-cell arrays, each of which comprises first and second data lines arranged in parallel,
A plurality of word lines intersecting these data lines, a plurality of bit lines intersecting the data lines, and a plurality of magnetic memory cells, wherein the magnetic memory cells are first and second magnetic memory cells.
, One end of the first tunnel junction in the stacking direction is connected to the first data line, one end of the second tunnel junction in the stacking direction is connected to the second data line, The other end of the first tunnel junction in the stacking direction and the other end of the second tunnel junction in the stacking direction are connected to a bit line via the same cell selecting semiconductor element, and are connected to a magnetic memory cell in the same subcell array. Are connected to different bit lines.

Further, according to the present invention, a plurality of tunnel junctions having a single or double or more tunnel junction are formed by laminating a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field. A magnetic memory device comprising a plurality of magnetic memory cell arrays, wherein the magnetic memory cell array comprises a plurality of sub-cell arrays, each of which comprises first and second data lines arranged in parallel,
A plurality of word lines crossing these data lines, a bit line running parallel to the data lines, and a plurality of magnetic memory cells, wherein the magnetic memory cells include first and second magnetic memory cells.
, One end of the first tunnel junction in the stacking direction is connected to the first data line, one end of the second tunnel junction in the stacking direction is connected to the second data line, The other end of the first tunnel junction in the stacking direction and the other end of the second tunnel junction in the stacking direction are connected to a bit line via the same cell selecting semiconductor element, and are connected to a magnetic memory cell in the same subcell array. Are connected to the same bit line.

According to the present invention, a plurality of tunnel junctions each having a single or double or more tunnel junction formed by laminating a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction changes by an external magnetic field are provided. A magnetic memory device comprising a plurality of magnetic memory cell arrays, wherein the magnetic memory cell array comprises a plurality of sub-cell arrays, and each sub-cell array includes first and second sub-data lines arranged in parallel with each other. The magnetic memory cell includes a plurality of word lines crossing a sub data line, a sub bit line running parallel to the sub data line, and a plurality of magnetic memory cells, wherein the magnetic memory cell has first and second tunnel junctions. One end of the first tunnel junction in the stacking direction is connected to the first sub-data line, and one end of the second tunnel junction in the stacking direction is connected to the second sub-data line. The other end of the first tunnel junction in the stacking direction and the other end of the second tunnel junction in the stacking direction are connected to the same sub-bit line via the same cell selecting semiconductor element. The first and second sub-data lines are respectively connected to the first and second data lines via data line selection transistors, and the sub-bit lines are respectively connected to the bit lines via bit line selection transistors. Features.

Here, preferred embodiments of the present invention include the following.

(1) Writing on the recording layer is performed so that the resistance values and the magnetoresistance ratios of the first and second tunnel junctions are substantially equal and both magnetization directions are always antiparallel (complementary writing). ).

(2) One end of each of the first and second TMR elements is connected to a different first data line and second data line, and the other end is connected to a bit line via the same cell selecting semiconductor element. is being done.

(3) In the information reading, when a potential difference is applied between the first and second data lines and the bit lines,
What is done by comparing the magnitude of the amount of current flowing through the second data line. At this time, the first and second data lines are kept at the same potential.

(4) Information is read by comparing the magnitude of the voltage appearing on the bit line with respect to the reference potential when a potential difference is applied to the first and second data lines.

(5) A first write line is arranged at one end of the first TMR element in the stacking direction, and a second write line is arranged at one end of the second TMR element in the stacking direction. A third common element is provided at one end or the other end of the second TMR element in the stacking direction of the second TMR element.
And the direction of the current flowing through the first writing line and the direction of the current flowing through the second writing line are opposite to each other.

(6) The first TMR element and the second TMR element are arranged on the same plane, the first write line and the second write line are arranged in parallel on the same plane, and The write line and the first and second write lines are in different planes, and are arranged so as to intersect near the first and second TMR elements. One end of each of the first and second write lines is connected outside the memory cell array region.

(7) The first TMR element and the second TMR element are vertically arranged, the first write line and the second write line are vertically arranged in parallel, and the third write line And the first and second write lines are vertically arranged in parallel in different planes, and the third write line and the first and second write lines are in different planes, and the first and second write lines are located in different planes. 2 are arranged so as to cross each other in the vicinity of the TMR element. One end of each of the first and second write lines is connected outside the memory cell array region.

(8) The semiconductor element for cell selection is a MOS type field effect transistor, a gate of a field effect transistor.
A diode element having a short-circuit between drains, or a pn junction;
A junction diode element using a Schottky junction.

(9) The number of memory cells included in one subcell array is 1000 or less.

(Operation) In the magnetic memory device having the above configuration, the first method of reading stored information from a memory cell is to activate the cell selection semiconductor element to a low impedance state at the time of reading, and to perform the first and second operations. When a potential difference is applied between the data line and the bit line, the magnitudes of the currents flowing through the first and second data lines are compared. 1st, 2nd
Are controlled to have the same potential. As a result, a sense current determined by the potential difference and the resistance value of each TMR element flows through the first data line and the second data line. The resistance value of the TMR element differs depending on whether the relative angle of magnetization between the pinned layer and the storage layer of the TMR element is parallel or antiparallel.

In the magnetic memory device of the present invention, the two TMR elements constituting the cell have the same resistance value and the same magnetoresistance change rate, and the magnetization directions of the respective storage layers are antiparallel to each other. Accordingly, if the potential difference is V _bias , the resistance of the first TMR element is R (1−MR / 2), and the resistance of the second TMR element is R (1 + MR / 2), the first and second data are obtained. The values I ₁ and I ₂ of the sense current flowing in the line are as follows: I ₁ = V _bias / R (1−MR / 2) (7) I ₂ = V _bias / R (1 + MR / 2) (8) .

That is, the difference I _{sig of the} sense current is I _sig =
V / R × MR, and a large difference signal can be obtained as compared with the related art. Since the memory cell is a current-driven element, if the resistance of the cell-selecting semiconductor element connected in series with the TMR element varies during conduction, the resulting output signal varies. In the present invention, the first TMR
Since the element and the second TMR element share the same cell selection semiconductor element, it is possible to completely eliminate the variation caused by the characteristic variation of the semiconductor element. This is a great advantage over the prior art.

In a second read method, the cell selection semiconductor element is activated to a low impedance state at the time of reading, and appears on a bit line when a potential difference is applied between the first and second data lines. The magnitude of the voltage with respect to the reference potential is compared. The potential difference between the first and second data lines is V, the resistance value of the first TMR element is R (1-MR / 2),
Assuming that the resistance value of the second TMR element is R (1 + MR / 2), the potential difference between the second data line and the bit line is as follows: V = _Vbias / 2 × (1 + MR / 2) (9)

Therefore, when the reference voltage V _{REF is set} to V _REF = V _bias / 2 (10), the differential voltage becomes V _sig = V _bias / 2 × MR / 2 (11).

In the present reading method, since the reference voltage is used, the amount of change in the differential voltage is smaller than in the first reading method, but (1) it does not depend at all on the current value flowing through the TMR element. That is, even when the number of memory cells in the memory cell array changes and the impedance between DL and / DL changes, there is no effect on the output. (2) The bias voltage is divided by two TMR elements. The bias voltage dependence of the MR can be reduced. (3) Since almost no current flows through the bit line, the characteristic variation of the selection semiconductor element can be removed.
It has such a great advantage.

On the other hand, in the magnetic memory device of the present invention,
Writing of storage information to the memory cell is performed by supplying current to the first, second, and third write lines. At this time, if the value of the current magnetic field is set so as to exceed the reversal magnetic field of the TMR element only in the intersection region between the first and second write lines and the third write line, cell selection at the time of writing can be realized.

In the magnetic memory device of the present invention, the first TM
The direction of the current flowing through the first write line disposed in the R element and the direction of the current flowing through the second write line disposed in the second TMR element are opposite to each other. That is, in the magnetic memory device of the present invention, the magnetization directions of the storage layers of the first and second TMR elements constituting the memory cell in the write operation are always antiparallel. The distinction between the information “1” and “0” is made, for example, based on whether the relative angle of magnetization between the pinned layer and the storage layer of the element is parallel or antiparallel with respect to the first TMR element.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the embodiment.

The area surrounded by the broken line in FIG.
1, this memory cell 201 is composed of two TMR elements and a selection transistor. That is, the first-stage memory cell includes the TMR elements 11 and 21 and the selection transistor 31, the second-stage memory cell includes the TMR elements 12 and 22, and the selection transistor 32, and the third-stage memory cell includes the TMR. The fourth stage memory cell is composed of the TMR elements 14 and 24 and the selection transistor 34. In the figure, four memory cells are arranged in the data line direction described later, but it is needless to say that the number of the arranged memory cells can be appropriately changed.

In the first-stage memory cell 201, one end of each of the two TMR elements 11 is connected to the data line DL.
One end of the MR element 21 is connected to the data line / DL. The other ends of the TMR elements 11 and 21 are connected to the same bit line BL via the cell selection transistor 31. Similarly, in the second and subsequent memory cells, the TMR
One end of each element is connected to each of data lines DL and / DL, and the other end is connected to the same bit line BL via cell selection transistors (32 to 34).

The select transistors 31 to 34 have independent word lines WL1 to WL4, respectively.
As will be described later, the adjacent memory cell array shares the drain region of the select transistor and the bit line. The data lines DL and / DL are connected to a current detection type differential amplifier 401 via a selection transistor having a common word line DSL. A bias voltage clamp circuit 420 is connected to the bit line BL via a selection transistor connected to the word line BSL.

Next, the operation of this circuit will be described using the memory cell 201 as an example.

Now, the magnetic properties of the recording layer and the pinned layer of the TMR element 11 will be described.
The parallel arrangement is in the parallel state and the TMR element 21 is in the anti-parallel state.
Consider the case (recorded information "1"). In the initial state, WL
The potentials of 1, BSL and DSL are 0. Then DS
The potentials of L and BSL are V _DDAs a zero
Place, BL to V_biasAnd WL1 is set to V_DDage
To make the selection transistor 31 conductive. TMR element 11
Is R (1-MR / 2), the resistance of the TMR element 21 is
If the value is R (1 + MR / 2), it flows to DL and / DL
Value of the sense current I₁, I_TwoIs I₁= V_bias/ R (1-MR / 2) (12) I_Two= V_bias/ R (1 + MR / 2) (13)

That is, I ₁ > I ₂ , and the difference is I _sig
= V / R × M. When the recording information "0", that is, the magnetization arrangement of the TMR element 11 is in an antiparallel state and the TMR element 21 is in a parallel state, I ₁ and I ₂ are as follows. I ₁ = V _bias / R (1 + MR / 2) (14) I ₂ = V _bias / R (1−MR / 2) (15) That is, I ₁ <I ₂ , and the difference is the recording information “ Equivalent to 1 ". Therefore, information can be read by comparing the magnitudes of I ₁ and I _{2 with} the current detection type differential amplifier 401.

FIG. 2 shows data lines DL, // in this embodiment.
The change of the current values I ₁ and I ₂ flowing in the DL is shown as a time change. Here, the bias voltage V _bias is 40
At 0 mV, the resistance value of the TMR elements 11 and 21 is 40 kΩ in a parallel state at a predetermined bias and 60 kΩ in an antiparallel state.
The potential of WL1 was held at V _DD for a period of 5 ns to 10 ns. As described above, it can be seen that different sense currents flow in DL and / DL depending on the element resistance value. A slight time delay is caused by the stray capacitance of the data line.

FIG. 3 shows waveforms when recording information of a plurality of memory cells is continuously read. In the present embodiment, since the low impedance data lines DL and / DL are driven by current, the delay due to the data line stray capacitance is extremely small at 0.5 ns or less as shown in FIG. Such high-speed readability is a great advantage of the present invention.

In this embodiment, the elements other than the selected cell are:
It functions as a resistor for short-circuiting the data lines DL and / DL, and its resistance value is 2R regardless of stored information. For example, considering a case where N + 1 cells are connected to the data lines DL and / DL, the equivalent circuit is as shown in FIG. In this circuit, the data lines DL and / DL are short-circuited by a 2R / N resistor. When a sense current is flowing from the selected cell to data lines DL and / DL, data lines DL and / D
Due to the wiring resistance RD of L, a slight potential difference is generated between DL and / DL, and a current flows through the short-circuit resistance RD. As a result, the current acts to cancel the current difference between DL and / DL.

FIG. 5 shows the result of simulation using the equivalent circuit of FIG. Here, it was assumed that R = 250 kΩ. When the value of the short-circuit resistance R _dummy is 2.5 kΩ, that is, when the number of connected cells N = 100, the reduction of the current difference is within 10%, and there is no practical problem. When the number of connected cells is N = 1000, the reduction of the current difference exceeds 50%, and the advantage of the present invention that the output signal is doubled by complementary reading is lost.
Therefore, in this embodiment, the number of memory cells per cell block is preferably 100 or less, and at most 10 memory cells.
Must be 00 or less.

FIG. 6 is a diagram schematically showing the arrangement of TMR elements and write lines constituting the magnetic memory array of the present embodiment. In FIG. 6, 10-14 and 20-24
Is a TMR element, and 51 and 52 are write lines. Here, for easy understanding, structures other than the TMR element and the write line are omitted. A portion surrounded by a broken line in the drawing indicates one area of the memory cell 201 which is a unit of recording information. Although five memory cells are arranged along the direction in which the write lines 51 are arranged in the drawing, the number of arranged memory cells can be changed as appropriate.

The memory cell 201 includes two TMR elements (the first TMR element 11 and the second TMR element 21). In each element region, the write line 51 and the write line 52 are perpendicular to each other. Intersects. Each of the TMR elements 11 and 21 constitutes a single or double or more multiple tunnel junction as described later, and has a pinned layer having a fixed magnetization direction and a memory whose magnetization direction is changed by an external magnetic field. And a layer. In addition, the resistance value, the magnetoresistance change rate, and the magnitude of the reversal magnetic field of the recording layer are manufactured so as to be equal in both elements. Write line 51 is U
The TMR element 11 and the TMR element 21 are arranged so that the traveling directions of the currents are opposite to each other.

Writing of recording information to the memory cell 201 is performed using the write line 51 and the write line 52.
Now, suppose that the potential of one end 511 of the write line 51 is
When set higher than 2, a write current flows through the write line 51 as shown by the arrow in the figure. The direction of the write current is as follows:
1 is at the lower left of the page. Due to this write current, a current magnetic field is generated around the write line in the direction indicated by the broken arrow in the figure, and the direction is on the left side of the paper for the TMR element 21 and on the right side of the paper for the TMR element 11. is there. Therefore, the TMR element 11 and T
It is possible to realize writing of the recorded information such that the magnetization direction of the MR element 21 is always opposite.

The distinction between the information "1" and "0" is made, for example, by TM
It may be determined whether the relative angle between the magnetization of the recording layer of the R element 11 and the magnetization of the fixed layer is parallel or antiparallel. In addition, information “1”,
Rewriting of "0" is easily performed by reversing the direction of the write current flowing through the write line 51. In the write line 51, the one connected to the terminal 511 is referred to as a first write line 51a, and the one connected to the terminal 512 is referred to as a second write line 51a.
Write line 51b.

In order to select a cell at the time of writing, a write line 52 (third write line) is used in addition to the write line 51. That is, when a write current in the upper left direction on the drawing is supplied to the write line 52 as shown in FIG.
, A current magnetic field in the direction indicated by the broken arrow in the figure is generated. The direction of the current magnetic field from the write line 52 is the same in the TMR elements 11 and 21, and is perpendicular to the direction of the current magnetic field from the write line 51. Therefore, each value of the current magnetic field from the write line 51 is smaller than the reversal magnetic field of the TMR elements 11 and 21 and the value of the combined current magnetic field from the write lines 51 and 52 is larger than the reversal magnetic field. If the value of the write current flowing through the write lines 51 and 52 is set, cell selective writing can be realized.

When performing cell writing using a current magnetic field orthogonal to the above, it is preferable that the axis of easy magnetization of the recording layer of the TMR element be parallel to the direction of the current magnetic field from the write line 51. Further, the write lines 51 and 52 need not necessarily be orthogonal to each other in the vicinity of the TMR element.
Any angle may be used.

FIG. 7 shows a memory cell 201 corresponding to FIG.
2 shows the planar structure of FIG. The memory cell according to the present embodiment includes:
One structure has two TMR elements, and the TMR elements are formed in a semiconductor circuit portion in a multilayer structure of a memory cell manufactured on a Si substrate 70.

In FIG. 7, reference numeral 71 denotes a drain region of the cell selection transistor, 72 denotes a source region of the cell selection transistor, 41 and 42 denote data lines, 30 denotes a word line of the cell selection transistor, and 44 denotes a lower layer of the TMR elements 11 and 21. Is a contact between the cell node 44 and the drain region of the cell selection transistor. The source region 72 of the cell selection transistor is shared with a memory cell of an adjacent memory cell array, which is omitted in the drawing, and is connected to a bit line. Considering the element isolation region, the size of one memory cell is 20 to 2
5λ ² . Here, λ is a data line interval.

In this embodiment, since one transistor is shared by two TMR elements, the cell area can be reduced by half as compared with the differential amplification method in which two TMR elements each have a transistor.

FIG. 8 is a sectional view taken along the line AA ′ (a) and a sectional view taken along the line BB ′ (b) of the memory cell planar structure of FIG.
FIG. The semiconductor circuit portion formed on the Si substrate 70 and each metal layer are separated by an interlayer insulating film 60 such as SiO ₂ . The TMR elements 11 and 21 are
It is composed of a laminated film composed of the recording layer 101 / insulating layer 102 / fixed layer 103. The TMR elements 11 and 21 are formed on a common cell node 44. Cell node 4
Numeral 4 is formed to obtain electrical contact between the cell select transistor and the TMR elements 11 and 21, and a nonmagnetic conductive film such as W, Al, or Ta is used as the material.

In this embodiment, the write lines 51,
FIG. 9 shows a structure in which the data lines 41 and 42 are separated from each other.
It is also possible to give the function of the write line 51 to 2. In this case, the metal wiring layer corresponding to the write line 51 shown in FIG. 8 becomes unnecessary. In this case, it is necessary that the data lines 41 and 42 be short-circuited at one end during the write operation. This short-circuit mechanism can be easily configured by using a conventionally known circuit technique. Although the data lines 41 and 42 are connected to each other by a large number of TMR elements, the junction resistance of the TMR elements is sufficiently larger than the wiring resistance of the data lines. The magnitude of the write current flowing as a result can be ignored.

It is preferable to provide a barrier metal made of a conductive metal nitride such as TiN or TaN for preventing metal from interdiffusion below the cell node 44 and the contact portion of the TMR element. In order to control the crystallinity and crystal orientation of the pinned layer 103, A
A seed layer of u, Pt, Ta, Ti, Cr or the like may be provided.

The fixed layer 103 is made of a thin film of Fe, Co, Ni, or an alloy thereof. The magnetization direction of the pinned layer is
A reference direction for writing and reading information is determined.
Therefore, the reversal magnetic field is required to be sufficiently larger than the reversal magnetic field of the recording layer described later. For this purpose, for example, a laminated film of a metal antiferromagnetic material such as a Mn alloy and Fe, Co, Ni or their alloys, or Fe, Co, Ni or their alloys and Cu, Ru which are interlayer antiferromagnetically coupled.
It is preferable to use an alternately laminated film with a non-magnetic metal such as.

The insulating layer 102 is made of an Al oxide film, and is formed on the fixed layer 103 by directly sputtering alumina.
Specifically, after forming an Al film of 2 nm or less, the Al film is formed by oxidizing the Al film with oxygen plasma. Insulating layer 102
Is required to have good insulating properties with an extremely thin film thickness of 2 nm or less. As the material, other than the above-mentioned alumina sputtered film, for example, an Al plasma oxide film, a natural oxide film, or an AlN film directly formed can be used. Further, a structure in which metal fine particles are dispersed in an insulator, or a structure in which a metal ultrathin film of several nm is sandwiched is also possible. The use of an insulating film having such a composite structure can easily control the cell resistance value by the structural design, which is preferable in practice.

The recording layer 101 is formed of a thin film made of Fe, Co, Ni, or an alloy thereof. In order to reduce power consumption when writing information, it is desirable that the reversal magnetic field of the recording layer be as small as possible. A preferred magnitude of the switching field is 30 to 50 Oe. For the purpose of reducing the reversal magnetic field of the recording layer, for example, C with high spin polarization of the electric electrons is used.
It is a preferable embodiment to use a film in which an oFe alloy film and a NiFe alloy film having soft magnetic properties are stacked. Also, F
Alloys or compounds of e, Co, Ni and other elements may be used.

The upper layer of the recording layer 101 includes W, Al, Cu
Data lines 41 and 42 made of a non-magnetic conductive film such as TiN are arranged. A barrier metal made of a conductive metal nitride such as TiN or TaN for preventing mutual diffusion with the data lines 41 and 42 is provided at the contact portion. Provision is a preferred mode. As for the configuration and the manufacturing method other than the TMR element portion, a conventionally known semiconductor element manufacturing technique can be used, and the detailed description is omitted.

As described above, in this embodiment, two TMRs
One memory cell (for example, 201) is composed of elements (for example, 11 and 21), and the write lines 51 arranged in parallel are formed.
Since the memory cells are respectively arranged at the intersections of the write lines a and 51b and the write lines 52 orthogonal to the write lines 52a and 51b, the current can be passed through the write lines 51a and 51b and the write line 52 to select any memory cell. The writing can be performed in an efficient manner.

The directions of the currents flowing through the write lines 51a and 51b are opposite to each other, and the two TMR elements 11 and 12 constituting one memory cell 201 in the write operation.
Since the magnetization direction of the first storage layer 101 is always antiparallel, the TMR elements 11 and 21 are used when reading stored information.
By taking the difference between the respective outputs, a large difference voltage can be obtained as compared with the prior art. More specifically, the cell selection transistor 31 is turned on at the time of reading, and a current I ₁ flowing through DL and / DL when a potential difference is applied between the first and second data lines DL and / DL and the bit line BL. ,
By comparing the current detection type differential amplifier 401 a magnitude of I _2, it is possible to read stored information.

Therefore, according to the present embodiment, the cell output voltage at the time of reading can be increased, and the signal-to-noise ratio can be improved without increasing the power consumption at the time of reading. And high-speed readability. Further, since the TMR element 11 and the TMR element 21 share the same cell selection transistor 31, it is also possible to completely remove the offset of the cell output voltage due to the variation in transistor characteristics.

(Second Embodiment) FIG. 10 is a diagram schematically showing the arrangement of TMR elements and write lines constituting a magnetic memory cell array according to a second embodiment of the present invention.

In FIG. 10, 10-14 and 20-2
4 is a TMR element, and 51 and 52 are write lines. Here, structures other than the TMR element and the write line are omitted for easy understanding. A portion surrounded by a broken line in the drawing indicates a region of the memory cell 201 which is a unit of recording information.

The memory cell 201 includes two TMR elements 11 and 21. In each element region, a write line 51 and a write line 52 vertically intersect. The write line 51 has a U-shaped folded shape in the vertical direction, and includes the TMR element 11 and the TMR element 2.
1 is arranged so that the traveling direction of the current is opposite. In the present embodiment, unlike the first embodiment, T
The MR elements 11 and 21 and the write line 51 are arranged in the same plane perpendicular to the film surface.

That is, the write line 51 is composed of a first write line 51a and a second write line 51b arranged in parallel in the vertical direction, and one end of each of the write lines 51a and 51b is located outside the cell arrangement region. It is connected. TMR elements 10 to 14 are respectively arranged on the lower surface of the write line 51a, and TMR elements 20 to 24 are arranged on the upper surface of the write line 51b.
Are arranged, and the TMR elements 10 and 20, 11 and 21, 12 and 22, 13 and 23, 14 and 24 are vertically opposed to each other. Then, for example, the TMR element 1
A third write line 52 is arranged at an intermediate position between the first and second write lines 51a and 51b so as to be orthogonal to the write lines 51a and 51b. ing. Other configurations and functions are the same as those of the first embodiment, and a detailed description thereof will be omitted here.

FIG. 11 shows a memory cell 20 corresponding to FIG.
FIG. 12 schematically shows a cross section taken along the line AA ′ (a) and a cross section taken along the line BB ′ (b) of the memory cell corresponding to FIG.

In the present embodiment, unlike the first embodiment, common cell nodes 44 and 44 'are provided in the upper and lower two layers, the cell node 44 is connected to the lower end of the upper TMR element 11, and the lower TMR element Cell node 4 at the bottom of 21
4 'is connected. The data line 41 is connected to the upper layer of the recording layer 101 of the TMR element 11, and the data line 42 is connected to the upper layer of the recording layer 101 ′ of the TMR element 21.

As described above, in the present embodiment, unlike the first embodiment, the TMR elements 11 and 21 and the write line 51,
Further, the data lines 41 and 42 are arranged in the same plane perpendicular to the film surface. Other configurations and functions are the same as those of the first embodiment, and the same effects as those of the first embodiment can be obtained. In this embodiment, two TMR elements 11 and 21 are used.
Are arranged vertically, the area of one memory cell is smaller than that of the first embodiment,
λ ² .

(Third Embodiment) FIG. 13 is a diagram schematically showing the arrangement of TMR elements and write lines constituting a magnetic memory array according to a third embodiment of the present invention.

In FIG. 13, 10-14 and 20-2
4 is a TMR element, and 51 and 52 are write lines. Here, structures other than the TMR element and the write line are omitted for easy understanding. Unlike the second embodiment shown in FIG. 10, the third write line 52 passes under the second write line 52b, not between the first and second write lines 51a and 51b.

FIG. 14 is a diagram schematically showing a sectional configuration of a memory cell according to the third embodiment. In the present embodiment, unlike the first and second embodiments, the TMR element 11 is located above the common cell node 44, and the TMR element 2 is located below the common cell node 44.
1 is formed. The data line 41 is connected to the upper layer of the recording layer 101 of the TMR element 11, and the data line 42 is connected to the lower layer of the recording layer 101 ′ of the TMR element 21.

In the present embodiment, the cell node 44 is made of a ferromagnetic material, which is used for the TMR element 11 and the TMR element 2.
It is characterized by having the same function as one common fixed layer. That is, the TMR element 11 includes the recording layer 101 and the insulating layer 1.
02, from the cell node 44, the TMR element 21
01 ', the insulating layer 102', and the cell node 44.

By adopting such a configuration, the present embodiment has an advantage that the manufacture of the Bessel array is easier than that of the second embodiment, and that the characteristic variation between the TMR element 11 and the TMR element 21 is reduced. Have. In the cell node 44, only the portions constituting the TMR elements 11 and 21 need only be ferromagnetic, and other portions may be made of non-magnetic material.

According to the present embodiment, since the TMR element and the write wiring are stacked in the film surface direction, the cell area can be significantly reduced. When λ is the data line interval, the size of one memory cell is 10 to 15λ ² ,
It is possible to realize a cell area about half as compared with the embodiment.

(Fourth Embodiment) FIG. 15 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fourth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements have one end connected to independent data lines DL and / DL, respectively, and the other end connected to the same bit line BL via a cell selection transistor. The select transistors 31 to 34 have independent word lines WL1 to WL4, respectively, but the select transistors 31 and 32 and the select transistors 33 and 34 share a drain region. The data lines DL and / DL are connected to a current detection type differential amplifier 401 via a selection transistor having a word line DSL, and the bit line BL is connected to a bias voltage clamp circuit 420 via a selection transistor connected to a word line BSL. It is connected.

The present embodiment is characterized in that adjacent cells share the drain region of the select transistor and the bit line. As described above, by sharing bit lines between adjacent cells, there is an advantage that the number of bit lines can be reduced to half.

(Fifth Embodiment) FIG. 16 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fifth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, one end of the TMR element is connected to each of data lines DL and / DL, and the other end of each TMR element is connected to another bit line B via a cell selection transistor.
L1 and BL2. Select transistor 31
Although independent word lines WL1 to WL4 are arranged in the elements to 選 択 34, respectively, the select transistors 31 and 32 and the select transistors 33 and そ れ ぞ れ share a drain region. The data lines DL and / DL are connected to a current detection type differential amplifier 401 via a selection transistor having a common word line DSL.

Bit lines BL1, BL2 are connected to data lines DL,
/ DL, which are connected to bit lines CBL1 and CBL2 running in parallel. CBL1 and CBL2 are independent word lines BSL outside the memory cell array area.
1 and BSL2 are connected to a bias voltage clamp circuit 420 via a selection transistor.

The present embodiment is characterized in that the bit line BL runs crossing the data lines DL and / DL and is shared by adjacent memory cell arrays. Adjacent memory cell arrays share BL and are finally connected by one CBL running in parallel with DL and / DL, so that wirings running in parallel with DL and / DL overlap with each other. This has the advantage that the number can be greatly reduced and the array area can be further reduced. In addition,
When BL and WL are running in parallel, simultaneous activation of BL and WL enables so-called page mode reading in which memory cells in the row direction are read at a time.

(Sixth Embodiment) FIG. 17 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a sixth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements have one end connected to independent data lines DL1 and / DL, respectively, and the other end connected to the same bit line BL1 via a cell selection transistor. In the memory cell adjacent to the memory cell in the word line direction, one ends of two TMR elements are connected to data lines DL2 and / DL, respectively, and the other end is connected to the same bit line BL2 via a cell selection transistor. Have been. That is, / DL is shared by memory cells adjacent in the word line direction.

The select transistors 31 to 34 have independent word lines WL1 to WL4, respectively.
The data lines DL1 and / DL are connected to the current detection type differential amplifier 4 via a selection transistor having a common word line DSL1.
01 is connected. / DL is shared with the adjacent memory cell array, but the selection transistor is different.
DL2 and / DL are connected to a current detection type differential amplifier 401 via a selection transistor having a common word line DSL2. Here, DL1 and DL2 do not share the word line of the selection transistor in order to prevent stray current through DL2.

The present embodiment is characterized in that adjacent memory cell arrays share a data line / DL.
Sharing the data lines in this way has the advantage that the array area can be further reduced.

(Seventh Embodiment) FIG. 18 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a seventh embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
One of the two TMR elements has one end connected to each of the sub data lines sDL and / sDL. TM
The other end of the R element is connected to the same sub bit line sBL via a cell selection transistor. Select transistors 31 to 34 have independent word lines WL1 to WL1 respectively.
WL4 is arranged.

The sub-data lines sDL, / sDL and the sub-bit line sBL are connected to the data lines DL, / DL,
It is connected to the bit line BL. Data lines DL, / DL
Are connected to a current detection type differential amplifier 401 via a selection transistor having a common word line DSL. The bit line BL is connected to a bias voltage clamp circuit 420 via a selection transistor having a word line BSL outside the memory cell array region.

The present embodiment is characterized in that the memory cell array is divided in the data line direction to form a sub cell array. By using such a configuration, it is possible to reduce the number of memory cells in the cell array without extremely increasing the array area. This makes it possible to avoid the problem of a decrease in the output signal due to an increase in the number of memory cells.

(Eighth Embodiment) FIG. 19 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to an eighth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
One of the two TMR elements has one end connected to each of the sub data lines sDL and / sDL. TM
The other end of the R element is connected to the bit line BL via a cell selection transistor, but each memory cell arranged in the data line direction has an independent bit line BL1 to BL1.
Connected to BL4.

The select transistors 31 to 34 have independent word lines WL1 to WL4, respectively.
Sub data lines sDL and / sDL share common word line SA.
The data lines DL,
/ DL. The data lines DL and / DL are connected to a current detection type differential amplifier 401 via a selection transistor having a common word line DSL.

The present embodiment is characterized in that the bit line BL runs crossing the data lines DL and / DL.
The bit line BL can also be used as a write line.

(Ninth Embodiment) FIG. 20 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a ninth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
Corresponds to 1. In each memory cell, one TM
One end of the R element is connected to each of the data lines DLR1 to DLR4, and one end of the other TMR element is connected to the same data line DLC. Each other end of the TMR element is connected to the same bit line BL via a cell selection transistor. Independent word lines WL1 to WL4 are arranged in the selection transistors 31 to 34, respectively. The bit line BL is connected to the word line B outside the memory cell array region.
It is connected to the bias voltage clamp circuit 420 via a selection transistor having SL.

In this embodiment, the data line pair DLR, DL
It is characterized in that C crosses and travels, and similarly, BL crosses WL. Further, since the bit lines are not shared in the word line direction, the cell selection at the time of reading can be uniquely performed by controlling the BL and WL potentials, and a bias voltage is applied to cells other than the selected cells. Never. Further, since the data line pair DLR and DLC cross each other, no unselected cells short-circuit the data line pair. Therefore, stable operation with high power consumption efficiency can be expected.

(Tenth Embodiment) FIG. 21 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a tenth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements are respectively connected to the data lines D
One end is connected to L and / DL, and the other end is connected to the same bit line BL via a cell selection transistor. Independent word lines WL1 to WL4 are arranged in the selection transistors 31 to 34, respectively. The data lines DL and / DL are connected to a bias voltage clamp circuit 420 and a current detection type differential amplifier 401 via a selection transistor having a common word line DSL. The bit line BL is grounded.

In the present embodiment, the bit line BL is at a lower potential than the data lines DL and / DL,
A feature is that a current flows from the DL to the bit line BL via the selection transistor. In FIG. 21, the bit line potential is set to the ground potential, but may be set to an arbitrary voltage within a range not exceeding the data line potential. In the present embodiment, it is necessary to completely equalize the potentials of the data lines DL and / DL. This can be easily realized by a bias voltage clamp circuit as shown in the drawing or the like.

(Eleventh Embodiment) FIG. 22 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to an eleventh embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements have one ends connected to independent data lines DL and / DL, respectively. TM
The other end of the R element is connected to a bit line BL via a cell selection transistor. However, memory cells arranged in the data line direction have independent bit lines BL1 to BL4.
It is connected to the. The selection transistors 31 to 34 include:
Independent word lines WL1 to WL4 are arranged. The data line DL is connected to a bias voltage clamp circuit 420 via a selection transistor having a word line DSL, and the data line / DL is grounded. Bit line B
L1 to BL4 are respectively different differential sense amplifiers SA
It is connected to the.

Next, the operation of this circuit will be described using the memory cell 201 as an example. Now, consider a case where the magnetization arrangement of the recording layer and the pinned layer of the TMR element 11 is in a parallel state and the TMR element 21 is in an anti-parallel state (recording information “1”). In the initial state, the potentials of WL1 and DSL are 0. Then DS
With the potential of L as V _DD and V _{bias applied} to DL,
The selection transistor 31 is made conductive by setting WL1 to V _DD . When the resistance value of the TMR element 11 is R (1−MR / 2), T
Assuming that the resistance value of the MR element 21 is R (1 + MR / 2),
The value of the voltage induced in BL is as follows: V ₁ = Vbias / 2 × (1 + MR / 2) (16)

On the other hand, the recording information "0", that is, the TMR element 1
When the magnetization arrangement of No. 1 is in the antiparallel state and the TMR element 21 is in the parallel state, the value of the voltage induced in BL is as follows.

V ₀ = V _bias / 2 × (1−MR / 2) (17) Therefore, for example, the reference voltage of the differential sense amplifier is V _REF =
If V _bias / 2 is set, stored information can be determined by comparing the magnitude of the BL potential with the reference voltage.

In this reading method, since the division ratio of the bias voltage V by the two TMR elements is detected, (1) T
It does not depend at all on the value of the current flowing through the MR element. That is, the number of memory cells in the memory cell array changes and DL, / D
Even if the impedance between L changes, the output is not affected. (2) Since the bias voltage is divided by two TMR elements, the bias voltage dependence of MR can be reduced. Since almost no current flows, there is an advantage that variations in characteristics of the selection semiconductor element, particularly variations in source / drain resistance, can be ignored.

(Twelfth Embodiment) FIG. 23 is a view showing an electrical equivalent circuit of a magnetic memory cell array according to a twelfth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements are respectively connected to the data lines D
One end is connected to L and / DL, and the other end is connected to the same bit line BL via a cell selection transistor 31. Independent word lines WL1 to WL4 are arranged in the selection transistors 31 to 34, respectively. The data line DL is connected to a bias voltage clamp circuit 420 via a selection transistor having a word line DSL, and the data line / DL is grounded. The bit line BL is connected to the differential sense amplifier SA via a selection transistor connected to the word line BSL.

In this embodiment, since the bit line BL is shared by a plurality of memory cells, the array area can be further reduced.

(Thirteenth Embodiment) FIG. 24 is a view showing an electrical equivalent circuit of a magnetic memory cell array according to a thirteenth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the structure of the memory cell array is basically the same as that of the twelfth embodiment. However, the bit line BL is divided into the sub-bit lines sBL via the current conversion circuit, and the fluctuation of the sBL voltage caused by the read operation is transmitted to the subsequent main amplifier SA via the bit line BL as a current difference by the current conversion circuit. Will be transferred. In the present embodiment, the length of the bit BL can be shortened to reduce the stray capacitance and the wiring resistance, and the bit line delay can be reduced and high-speed operation can be realized.

(Fourteenth Embodiment) FIG. 25 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fourteenth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements are respectively connected to the data lines D
One end is connected to L and / DL. The other end of the TMR element is connected to the bit line BL via the cell selecting diode element 31. The memory cells arranged in the data line direction have independent bit lines BL1 to BL4.
It is connected to the. The data line DL is connected to a bias voltage clamp circuit 420 via a selection transistor having a word line DSL, and the data line / DL is grounded. The bit line BL is grounded via a load resistor and a selection transistor connected to the word line BSL.

In this embodiment, the forward voltage drop of the diode is used for cell selection. That is, it is assumed that the value of the forward voltage drop of the diode is V _F and V _F <V ₀ is satisfied. Now, when a potential difference V is applied to specific data lines DL and / DL, a voltage of V ₀ -V _F or V ₁ -V _F is applied to a sense amplifier connected to a bit line group crossing DL and / DL. appear. Therefore, the stored information can be read by determining the magnitude.

As the diode element for cell selection in this embodiment, in addition to a junction type diode such as a pn diode, a Schottky diode, and a MIS diode, as shown in FIG. MOS transistors can be used. In general, in a magnetic memory device, MOS transistors are frequently used, and forming a pn diode in a semiconductor portion requires an extra element isolation region, which leads to an increase in cell area. A diode using an nMOS transistor does not have such a problem and can be said to be a preferable mode.

(Fifteenth Embodiment) FIG. 27 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fifteenth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The area surrounded by the broken line in FIG.
1, two TMR elements are respectively connected to the data lines D
One end is connected to L and / DL. The other end of the TMR element is connected to the bit line BL via the cell selecting diode element 31. The memory cells arranged in the data line direction have independent bit lines BL1 to BL4.
It is connected to the. The data line DL is connected to a bias voltage clamp circuit 420 via a selection transistor having a word line DSL, and the data line / DL is grounded. The bit line BL is connected to the offset voltage circuit 430 and the current sense amplifier 402.

[0132] Figure 28, in this embodiment, the measurement of the current flowing in the bit line as a function of the offset voltage V _{of f.} The two curves are respectively recorded information "1",
The currents I ₀ and I ₁ corresponding to “0” are shown. V _off
= 500 mV, there is a region where only I ₀ is almost zero. In this region, the value of I ₁ / I ₂ becomes very large, which is very advantageous in practice.

Such a change in I ₀ and I ₁ according to the recorded information can be realized by combining a voltage change according to the recorded information and a strong nonlinearity near the forward threshold voltage V _{TO of the} diode. Usually, the magnitude of _VTO of the diode is determined by the manufacturing method. Therefore, the method of applying the offset voltage as in the present embodiment is a preferable mode.

(Sixteenth Embodiment) FIG. 29 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a sixteenth embodiment of the present invention.

A region surrounded by a broken line in the figure corresponds to one memory cell 201. In this memory cell 201, TM
The R elements 11 and 21 are independent data lines 41 and 4 respectively.
2 is connected at one end, and the other ends of the TMR elements 11 and 21 are commonly connected to a cell selection transistor 32.

In each memory cell, an independent word line 30 is connected to each of the cell selecting transistors 31 to 34.
1 to 304 are arranged respectively. One end of each of the data line 41 and the data line 42 is connected to a separate constant current source 401,
The other end is connected to the sense amplifier 404. A common word line 403 is arranged for the MOS transistors forming the constant current sources 401 and 402. The sense amplifier 404 is a voltage latch type flip-flop amplifier, and has a common source terminal 405 and a data terminal 406.

Next, a method for reading information in the magnetic memory cell array of the present embodiment will be described in detail.

FIG. 30 shows the potential WL of the word line 302 of the cell selection transistor 32, the potential DLW of the word line 403 connected to the constant current sources 401 and 402, the data line 41,
Changes in the potentials DL and / DL at 42 and the potential SS at the common source terminal 405 of the sense amplifier 404 during reading are shown with the time axis taken along the horizontal axis.

Now, consider a case where the magnetizations of the recording layer and the pinned layer of the TMR element 11 are in an antiparallel state (recorded information “1”). In the initial state, the cell selection transistor 32
The word line WL, the potential of the word line DLW controlling the constant current source 401 and 402 0, the potential of the common source terminal of the sense amplifier 404 is set to V _D. In this state, the data lines 41 and 42 are at the floating potential, and the sense amplifier 404 is disconnected from the data lines 41 and 42.

Next, after WL is set to the high potential Vcc to turn on the cell selection transistor 32, the high potential Vs is applied to the DLW.
give. As a result, a sense current Is equal to the TMR elements 11 and 21 flows through the data lines 41 and 42. Assuming that the voltage drop at the cell selection transistor 32 is Vr, the potentials of the data lines 41 and 42 are DL = V _D = (R + △ R) × Is + Vr / DL = V _D ′ = R × Is + Vr. (18) That is, ΔV = ΔR × Is (19) is obtained as the differential voltage of the data lines 41 and 42.

Next, in this state, a read pulse that changes from _VD to 0 is applied to the common source terminal 405 of the sense amplifier 404 as shown. When the potential difference between DL and SS exceeds the threshold potential Vth of the transistor, the transistor connected to the low potential data line 42 starts discharging,
As a result, the data line 41 maintains the initial potential Vd, and one data line 42 is latched at 0V.

When the recording information is "0", the TMR element 1
The magnetization of the recording layer 1 and the pinned layer are in a parallel state, and the data line 41 is at a low potential when a sense current is flowing. Therefore, when a read pulse is given, the data line 41 becomes 0
Latched to V. Therefore, when a pulse is applied to the common source terminal 405 and a certain period of time elapses, the voltage D of the data line 41 is extracted using the terminal 406 of the sense amplifier to perform reading. After reading the data, the potential of each terminal is returned to the initial state as shown in FIG.
Are reset, and the read operation is completed.

In the configuration of this embodiment, the sense amplifier 40
4 of the size phi read pulse applied to the common source terminal 405, it is necessary to _{V D '≦ φ ≦ V D} . That is, the margin for the magnitude of the pulse is about the differential voltage between the data lines at the time of reading.
In order to stabilize the operation of this part, (1) a voltage amplifier circuit in the preceding stage of the sense amplifier, (2) a circuit for compensating for variations in V _D and V _D ′, and the like may be provided. Although the flip-flop amplifier is used in this embodiment, another amplifier circuit, for example, a current mirror amplifier may be used as the sense amplifier.

FIG. 31 is a diagram schematically showing the entire configuration of the magnetic memory cell array of the present embodiment. The memory cell array includes memory cells arranged two-dimensionally, a data line group connected to these memory cells, a word line group, and a write line group crossing in the vicinity of the memory cell. The two write lines RWL and CWL are connected to a column decoder and a row decoder, respectively, thereby enabling selective writing corresponding to an external address input.

On the other hand, a word line DWL for driving the pair of data lines DL and / DL and a word line WL orthogonal to the word line DWL for driving the transistor for cell selection are connected to a column decoder and a row decoder, respectively. Selective readout corresponding to the address input from the CPU. The sense amplifier SA is provided for each data line pair, and is driven by a common word line SS. Then, the read data is to be read to the common data line D.

As described above, in this embodiment, two TMRs are used.
One memory cell (for example, 201) is composed of elements (for example, 11, 21), and the write lines 51 arranged in parallel are arranged.
Since the memory cells are respectively arranged at the intersections of the write lines a and 51b and the write lines 52 orthogonal to the write lines 52a and 51b, the current can be passed through the write lines 51a and 51b and the write line 52 to select any memory cell. The writing can be performed in an efficient manner.

The directions of the currents flowing through the write lines 51a and 51b are opposite to each other, and the two TMR elements 11 and 12 forming one memory cell 201 in the write operation.
Since the magnetization direction of the first storage layer 101 is always antiparallel, the TMR elements 11 and 21 are used when reading stored information.
By taking the difference between the respective outputs, a large difference voltage can be obtained as compared with the prior art. Also, the TMR element 11
And TMR element 21 are the same cell selection transistor 3
2, the offset of the cell output voltage due to variation in the characteristics of the transistor can be completely removed.

Therefore, according to the present embodiment, the cell output voltage at the time of reading can be increased, the signal-to-noise ratio can be improved without increasing the power consumption at the time of reading, and low power consumption can be achieved. And high-speed readability.

The present invention is not limited to the above-described embodiments, but can be implemented in various modifications without departing from the scope of the invention.

[0150]

As described above in detail, by using the magnetic memory cell array structure of the present invention, it is possible to realize a much higher output and lower noise at the time of reading information as compared with the case of using the prior art. Becomes possible. Therefore, a solid-state magnetic memory device having low power consumption and high-speed readability can be realized.

[Brief description of the drawings]

FIG. 1 is an exemplary view showing an electrical equivalent circuit of a magnetic memory cell array according to a first embodiment.

FIG. 2 is a view for explaining the first embodiment, in which D
L, illustrates a change in the current value I _1, I ₂ as the time changes flowing to / DL.

FIG. 3 is a diagram for explaining the first embodiment, showing a waveform when recording information of a plurality of memory cells is continuously read.

FIG. 4 is an equivalent circuit diagram showing elements other than a selected cell assuming short-circuit resistance.

FIG. 5 is a diagram showing a result of a simulation using the equivalent circuit of FIG. 4;

FIG. 6 is a diagram schematically showing the arrangement of TMR elements and write lines constituting the magnetic memory cell array according to the first embodiment.

FIG. 7 is a diagram showing a planar structure of a memory cell used in the first embodiment.

8 is a diagram showing a cross section taken along line AA ′ and a cross section taken along line BB ′ of the memory cell structure in FIG. 7;

FIG. 9 is a diagram showing a cross section of a memory cell structure when a write line and a data line are shared.

FIG. 10 is a diagram schematically showing the arrangement of TMR elements and write lines constituting a magnetic memory cell array according to a second embodiment.

FIG. 11 is a diagram showing a planar structure of a memory cell according to a second embodiment.

12 is a view taken along the line AA ′ in the memory cell structure of FIG. 8;
The figure which shows a cross section and BB 'arrow cross section.

FIG. 13 is a diagram schematically showing the arrangement of TMR elements and write lines constituting a magnetic memory cell array according to a third embodiment.

FIG. 14 is a view showing an element sectional structure of a magnetic memory cell array according to a third embodiment.

FIG. 15 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fourth embodiment.

FIG. 16 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a fifth embodiment.

FIG. 17 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a sixth embodiment.

FIG. 18 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a seventh embodiment.

FIG. 19 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to the eighth embodiment.

FIG. 20 is a diagram showing an electrical equivalent circuit of a magnetic memory cell array according to a ninth embodiment.

FIG. 21 is a view showing an electrical equivalent circuit of the magnetic memory cell array according to the tenth embodiment.

FIG. 22 is a view showing an electrical equivalent circuit of the magnetic memory cell array according to the eleventh embodiment.

FIG. 23 is a view showing an electrical equivalent circuit of the magnetic memory cell array according to the twelfth embodiment;

FIG. 24 is a view showing an electrical equivalent circuit of a magnetic memory cell array according to the thirteenth embodiment.

FIG. 25 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the fourteenth embodiment.

FIG. 26 is a diagram showing an equivalent circuit in which a pn diode of the magnetic memory cell array according to the fourteenth embodiment is replaced with a MOS transistor.

FIG. 27 is a view showing an electrical equivalent circuit of the magnetic memory cell array according to the fifteenth embodiment;

FIG. 28 is for describing a fifteenth embodiment;
FIG. 9 is a diagram showing a result of measuring a current flowing through a bit line as a function of an offset voltage V _off .

FIG. 29 is a diagram showing an electrical equivalent circuit of the magnetic memory cell array according to the sixteenth embodiment.

FIG. 30 is a timing chart for explaining a read operation in the magnetic memory cell array according to the sixteenth embodiment.

FIG. 31 is a diagram showing an overall configuration of a magnetic memory cell array according to a sixteenth embodiment.

[Explanation of symbols]

 10,..., 14, 20,..., 24... TMR element 31,..., 34... Selection transistor 201... Memory cell 301,. 52 Write line 60 Interlayer insulating layer 101 Recording layer 102 Insulating layer 103 Fixed layer 70 Si substrate 71 Drain region 72 Source region 401 Sense amplifier 420 Bias voltage clamp circuit 430 Offset voltage circuit

Continued on the front page (72) Inventor Yoshiaki Saito 1st Toshiba R & D Center, Komukai-ku, Kawasaki City, Kanagawa Prefecture (72) Inventor Masayuki Sunai Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture No. 1 Toshiba R & D Center

Claims (10)

[Claims] A fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field are stacked, and a plurality of tunnel junctions having a single or double or more tunnel junction are provided. In a magnetic memory device, a memory cell as a unit for recording information includes first and second tunnel junctions, and one end of the first tunnel junction in the stacking direction and the other end of the second tunnel junction in the stacking direction. One end is connected to another data line, and the other end in the stacking direction of the first tunnel junction and the other end in the stacking direction of the second tunnel junction are connected to the bit line via the same cell selecting semiconductor element. A magnetic memory device which is connected. 2. A first write line is arranged at one end of the first tunnel junction in the stacking direction, and a second write line is arranged at one end of the second tunnel junction in the stacking direction. A common third write line is arranged at one end or the other end of the first tunnel junction in the stacking direction and at one end or the other end of the second tunnel junction in the stacking direction. 2. The magnetic memory device according to claim 1, wherein a direction of a current flowing through the first write line and a direction of a current flowing through the second write line are opposite to each other. 3. The first tunnel junction and the second tunnel junction are arranged in the same plane, the first write line and the second write line are arranged in the same plane in parallel, and 3
3. The write line according to claim 2, wherein the first write line and the first and second write lines are in different planes, and are arranged to intersect near the first and second tunnel junctions. Magnetic memory device. 4. A first tunnel junction and a second tunnel junction are vertically arranged, and a first write line and a second
The third write line and the first and second write lines are arranged in a different plane from the first and second tunnel junctions in a plane different from the first and second write lines. 3. The magnetic memory device according to claim 2, wherein the magnetic memory devices are arranged so as to cross each other. 5. The recording layer is written so that the resistance value and the magnetoresistance ratio of the first and second tunnel junctions are substantially equal and both magnetization directions are always antiparallel. The magnetic memory device according to claim 1. 6. A method of reading information, comprising the steps of: reading a potential difference between a bit line and a first data line connected to a first tunnel junction and a second data line connected to a second tunnel junction; 2. The magnetic memory device according to claim 1, wherein the comparison is made by comparing the magnitude of the amount of current flowing through the first and second data lines when. 7. A method for reading information, comprising: applying a potential difference between a first data line connected to a first tunnel junction and a second data line connected to a second tunnel junction. 2. The magnetic memory device according to claim 1, wherein the magnitude of the voltage appearing on the bit line is compared with a reference potential. 8. A plurality of tunnel junctions comprising a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field are laminated to form a single or double or more tunnel junction. A magnetic memory device comprising a magnetic memory cell array, wherein the magnetic memory cell array is composed of a plurality of sub-cell arrays, each sub-cell array intersecting first and second data lines arranged in parallel with these data lines. A plurality of word lines, a plurality of bit lines crossing the data lines, and a plurality of magnetic memory cells, wherein the magnetic memory cells include first and second tunnel junctions and a first tunnel. One end of the joining portion in the stacking direction is the first
And one end of the second tunnel junction in the stacking direction is connected to the second data line, and the other end of the first tunnel junction in the stacking direction and the stacking direction of the second tunnel junction are stacked. The other end of the magnetic memory device is connected to a bit line via the same cell selecting semiconductor element, and magnetic memory cells in the same sub-cell array are connected to different bit lines. 9. A plurality of tunnel junctions comprising a fixed layer having a fixed magnetization direction and a recording layer whose magnetization direction is changed by an external magnetic field are laminated to form a single or double or more tunnel junction. A magnetic memory device comprising a magnetic memory cell array, wherein the magnetic memory cell array is composed of a plurality of sub-cell arrays, each sub-cell array intersecting first and second data lines arranged in parallel with these data lines. A plurality of word lines, a bit line running parallel to the data lines, and a plurality of magnetic memory cells, wherein the magnetic memory cells include first and second tunnel junctions, One end of the joining portion in the stacking direction is the first
And one end of the second tunnel junction in the stacking direction is connected to the second data line, and the other end of the first tunnel junction in the stacking direction and the stacking direction of the second tunnel junction are stacked. The other end of the magnetic memory device is connected to the bit line via the same cell selecting semiconductor element, and the magnetic memory cells in the same sub-cell array are connected to the same bit line. 10. A plurality of tunnel junctions comprising a fixed layer having a fixed magnetization direction and a recording layer having a magnetization direction changed by an external magnetic field, and forming a single or double or more tunnel junction. A magnetic memory device comprising a magnetic memory cell array, wherein the magnetic memory cell array comprises a plurality of sub-cell arrays, and each sub-cell array includes first and second sub-data lines arranged in parallel, and these sub-data lines A plurality of word lines, a sub-bit line running parallel to the sub-data line, and a plurality of magnetic memory cells, wherein the magnetic memory cells include first and second tunnel junctions, One end of the tunnel junction in the stacking direction is the first
, One end of the second tunnel junction in the stacking direction is connected to the second sub-data line, and the other end of the first tunnel junction in the stacking direction and the other end of the second tunnel junction are connected. The other end in the stacking direction is connected to the same sub-bit line via the same cell selecting semiconductor element, and
Wherein the sub data lines are connected to first and second data lines via data line selection transistors, respectively, and the sub bit lines are connected to bit lines via bit line selection transistors, respectively. Memory device.