JP2001306188A - Power control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power control unit that can shut down certainly the power in power supply circuits by single operation, cancel a power shutdown operation after switching-off operation and realize decreasing of scale of circuit and lowering of cost. SOLUTION: The time constant of an integration circuit 21 is set at lower than that of an integration circuit 22. If the off status continues for the first elapse time from the point of time when a power switch 10 turns to off, an interruption signal INT output from the integration circuit 21 increases to a high level and power on/off signal OF output from CPU 100 goes up to a high level, while the relay on/off signal V7 output from a flip-flop circuit 17 goes down to a low level. During abnormal status of CPU, an output signal from the integration circuit 22 goes up to high level and a relay on/off signal V7 output from the flip/flop circuit 17 goes down to a low level when the off status continued for the second elapse time from the point of time when the power switch 10 turns to off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control device for controlling power cutoff in a power supply circuit.

[0002]

2. Description of the Related Art Conventional information processors such as word processors and personal computers are provided with a mechanical switch and a software switch for shutting off power in a power supply circuit.

When a user turns off a mechanical switch,
Interrupt processing of a CPU (Central Processing Unit) is performed. As a result, the CPU executes a predetermined end process required to end the process of the information processing device, and shuts down the power by software when the end process is completed. With such a software switch, the processing in the information processing apparatus ends normally.

However, when the CPU operates abnormally,
The software switch does not work and the power cannot be turned off. So, after turning off the mechanical switch,
In the case where the power supply is not cut off due to abnormal operation of the CPU, a power supply control device has been proposed which forcibly cuts off the power supply in the power supply circuit by turning on a mechanical switch and then turning it off again.

FIG. 5 is a circuit diagram showing a configuration of a conventional power supply control device. 5, the on / off signal a output from the power switch 31 is supplied to the set terminal S of the flip-flop circuit 32, the input terminal of the inverter 34, and one input terminal of the AND circuit 37. Interrupt signal b output from output terminal Q of flip-flop circuit 32
Is given to the CPU 33. The CPU 33 outputs the permission signal c
To the reset terminal R of the flip-flop circuit 32,
The power-off instruction signal d is supplied to one input terminal of the OR circuit 36.

[0006] An output signal of the inverter 34 is applied to a set terminal S of a flip-flop circuit 35. The output signal e from the output terminal Q of the flip-flop circuit 35 is provided to the other input terminal of the OR circuit 36. The output signal of the OR circuit 36 is provided to the other input terminal of the AND circuit 37. The output signal of the AND circuit 37 is a relay on / off signal f
To the relay 38. The relay 38 is used to shut off power in the power circuit.

FIGS. 6 and 7 are timing charts for explaining the operation of the power supply control circuit shown in FIG. 5. FIG. 6 shows a power supply cutoff process when the CPU 33 operates normally, and FIG. Shows the power supply cutoff processing of FIG.

First, with reference to FIG. 6, a description will be given of a power-off process during a normal operation of the CPU 33. As shown in FIG. 6, when the power switch 31 is turned on, the switch on / off signal a becomes low level (“L”). When the power switch 31 is turned off, the switch on / off signal a rises to a high level ("H"). Switch on / off signal a
, The flip-flop circuit 32 is set, and the interrupt signal b output from the output terminal Q
Rises from low level to high level. Thereby, the CPU 33 raises the permission signal c from a low level to a high level. In response to the rise of the enable signal c, the flip-flop circuit 32 is reset, and the interrupt signal b falls from the high level to the low level.

The CPU 33 performs predetermined termination processing, and after the termination processing is completed, raises the power-off instruction signal d from a low level to a high level. As a result, the output signal of the OR circuit 36 rises from a low level to a high level. At this time, since the switch on / off signal a is at the high level, the relay on / off signal f output from the AND circuit 37 rises from the low level to the high level. As a result, the relay 38 is turned off, and the power supply in the power supply circuit is cut off.

Next, with reference to FIG. 7, a description will be given of the power-off process when the CPU 33 operates abnormally. As shown in FIG. 7, when the power switch 31 is turned on, the switch on / off signal a becomes low level. When the power switch 31 is turned off, the switch on / off signal a rises to a high level. In response to the rise of the switch on / off signal a, the flip-flop circuit 32 is set, and the interrupt signal b output from the output terminal Q rises from a low level to a high level. Thereby, the CPU 33 raises the permission signal c from a low level to a high level. In response to the rise of the enable signal c, the flip-flop circuit 32 is reset, and the interrupt signal b falls from the high level to the low level.

When the CPU 33 operates abnormally, the CPU 33
Does not perform the termination processing, and the power-off instruction signal d is kept at the low level. On the other hand, since the switch on / off signal a is at the high level, the output signal of the inverter 34 is at the low level, and the output signal e from the output terminal Q of the flip-flop circuit 35 is at the low level. Therefore, the output signal of the OR circuit 36 is also at the low level, and the output signal of the AND circuit 37 is not changed at the low level. As a result, the power supply in the power supply circuit is not shut off.

When the power switch 31 is turned on again, the switch on / off signal a goes low. As a result, the output signal of the inverter 34 becomes high level, the flip-flop circuit 35 is set, and the output signal e from the output terminal Q rises to high level. Therefore,
The output signal of the OR circuit 36 also becomes high level, and the relay on / off signal f output from the AND circuit 37 rises to high level. As a result, the relay 38 is turned off, and the power supply in the power supply circuit is cut off.

In this way, when the CPU 33 operates abnormally, the power supply in the power supply circuit can be forcibly shut off by turning off the power switch 31 and then turning it on and off again.

[0014]

SUMMARY OF THE INVENTION However, CPU
When the software switch by the CPU 33 does not operate normally, the actual use of the information processing apparatus is often already disabled due to the abnormal operation of the CPU 33, and the user can easily grasp the abnormal operation of the CPU 33. As described above, although the user can easily grasp the abnormal operation of the CPU 33, it is necessary to turn on and off the power switch 31 twice in order to cut off the power supply in the power supply circuit. Is troublesome.

If the power switch 31 is turned on and off twice, it becomes impossible to cancel the forcible shut-off operation of the power supply. For example, even if an abnormal operation occurs in the CPU 33, normal data may be stored in the memory. In such a case, if the power is forcibly shut down,
Data stored in the memory is lost. Even after the power switch 31 is turned on and off twice, it is not possible to cancel the forced power-off operation even if the user notices that normal data remains in the memory.

Further, in the power supply control device of FIG. 5, two flip-flop circuits 32 and 35 having a relatively large circuit scale are connected.
Since it is necessary to use a single circuit, the overall circuit scale is increased and the cost is increased.

It is an object of the present invention to be able to surely shut off the power supply in a power supply circuit by one operation, to cancel the power supply cutoff operation after the switch is turned off, to reduce the circuit scale and to reduce the cost. It is an object of the present invention to provide a power supply control device that can be implemented.

[0018]

Means for Solving the Problems and Effects of the Invention A power control device according to a first aspect of the present invention is a power control device for controlling power cutoff in a power circuit, comprising: a switch; First signal generating means for generating a first signal when the off state continues for a first time;
The second signal generating means for generating a second signal when the off state continues for a second time longer than the first time from the time of the switch-off operation, and the first signal generating means. An arithmetic processing unit for generating a third signal after performing a predetermined process in response to the first signal; and a second signal generated by the second signal generating means or a second signal generated by the arithmetic processing unit. And a shut-off signal generating means for generating a shut-off signal for shutting off the power in the power supply circuit in response to the signal of (3). It is set to a time that can be completed.

In the power supply control device according to the present invention, when the switch is turned off, the first signal generating means outputs the first signal when the off state continues for the first time from the time of the switch off operation. Is generated. During a normal operation of the arithmetic processing unit, a third signal is generated after predetermined processing is performed by the arithmetic processing unit in response to the signal generated by the first signal generation unit. As a result, in response to the third signal, a shutoff signal for shutting off the power supply in the power supply circuit is generated by the shutoff signal generating means. As a result, the power supply in the power supply circuit is cut off.

During an abnormal operation of the arithmetic processing unit, the third signal is not generated by the arithmetic processing unit even if the off state continues for the first time from the time when the switch is turned off. In this case, the second signal is generated by the second signal generation means when the off state continues for the second time longer than the first time from the time of the switch off operation. Thereby, the second
In response to this signal, a shutoff signal for shutting off the power in the power supply circuit is generated by the shutoff signal generating means. As a result, the power supply in the power supply circuit is forcibly shut off.

In this case, the second time is set to a time during which the predetermined processing by the arithmetic processing device can be completed during normal operation of the arithmetic processing device. The second signal is not generated until the predetermined processing is completed. Therefore, during normal operation of the arithmetic processing device, the power supply in the power supply circuit is shut off after the predetermined processing by the arithmetic processing device is completed.

If the switch is turned on after the switch is turned off and before the second time elapses from the time of the off operation, the second signal is not generated by the second signal generating means, and the cutoff signal is output. No shutoff signal is generated by the generating means. Therefore, the forcible shut-off operation of the power supply in the power supply circuit is released.

As described above, even when the arithmetic processing device operates abnormally, the switch is turned on for the second time.
The power supply in the power supply circuit can be reliably shut off.
In addition, forcibly shutting off the power supply in the power supply circuit can be easily released by performing the on operation again after the switch is turned off. Further, since the power supply control device includes the first and second signal generation means, the arithmetic processing unit, and the cutoff signal generation means, it is possible to reduce the circuit scale and cost.

According to a second aspect of the present invention, in the power supply control device according to the first aspect, the first signal generating means includes a first resistance means to which a current is supplied when a switch is turned off. And a first integration circuit configured by a first capacitance means charged by a current flowing through the first resistance means, wherein the first integration circuit comprises a first integration circuit configured to output the first capacitance when the voltage of the first capacitance means reaches a predetermined level. The second signal generating means includes a second resistance means to which a current is supplied when the switch is turned off, and a second capacitance means to be charged by a current flowing through the second resistance means. A second integration circuit configured to generate a second signal when the voltage of the second capacitance means reaches a predetermined level, and to set the time constant of the first integration means to the second integration means. It is smaller than the time constant.

In this case, when the switch is turned off, the first
A current flows through the first resistance means of the integration circuit, and the first capacitance means is charged, and a current flows through the second resistance means of the second integration circuit, thereby charging the second capacitance means. . Since the time constant of the first integration circuit is smaller than the time constant of the second integration circuit, the first capacitance means of the first integration circuit is charged faster than the second capacitance means of the second integration circuit. You.

In this way, when the off state continues for the first time from the time point when the switch is turned off, the voltage of the first capacitance means of the first integration circuit becomes the predetermined level, and the first signal Is generated. Further, when the off state continues for the second time from the time point when the switch is turned off, the voltage of the second capacitance means of the second integration circuit becomes a predetermined level, and the second signal is generated.

Since the first and second signal generating means are constituted by simple integrating circuits, the circuit scale is small and inexpensive.

In the power supply control device according to a third aspect of the present invention, in the power supply control device according to the first aspect of the invention, the first signal generation means measures a time in an off state from a time point when the switch is turned off, The first signal generating means generates a first signal when a first time elapses, and the second signal generating means measures an off-state time from a time point when the switch is turned off, and outputs a second time signal. It includes a second timing means for generating a second signal upon elapse.

In this case, the off-state time is measured by the first timer means from the point of time when the switch is turned off, and the off-state time is measured by the second timer means. Then, a first signal is generated by the first timer when the first time has elapsed, and a second signal is generated by the second timer when the second time has elapsed.

The first time and the second time can be easily adjusted by adjusting the settings of the first time measuring means and the second time measuring means.

[0031]

FIG. 1 is a circuit diagram showing a configuration of a power supply control device according to a first embodiment of the present invention.

The power supply control device shown in FIG. 1 includes a power supply switch 10 composed of a mechanical switch, integration circuits 21 and 22, buffers 15 and 16, a flip-flop circuit 17, and an OR circuit 19. The integrating circuit 21 includes the resistor 11 and the capacitor 13, and the integrating circuit 22 includes the resistor 12 and the capacitor 14.

A power supply voltage Vcc is applied to one terminal of the power supply switch 10. The other terminal of the power switch 10 is connected to the node N0. Node N0 is a resistor 11
And the node N1 is grounded via the capacitor 13. The node N1 is connected to the node N3 via the buffer 15, and the node N3
Is connected to the set terminal S of the flip-flop circuit 17.

The node N0 is connected to the node N2 via the resistor 12, and the node N2 is grounded via the capacitor 14. The node N2 is connected to the node N4 via the buffer 16, and the node N4 is connected to the OR circuit 1
9 is connected to one input terminal. The other input terminal of the OR circuit 19 is connected to the node N5, and the node N5 is grounded via the resistor 20. The output terminal of the OR circuit 19 is connected to the reset terminal R of the flip-flop circuit 17. Output terminal Q of flip-flop circuit 17
Is connected to the relay 18.

In this embodiment, pressing (closing) the power switch 10 corresponds to an OFF operation.

Assuming that the resistance value of the resistor 11 is R1 and the capacitance value of the capacitor 13 is C1, the time constant of the integrating circuit 21 constituted by the resistor 11 and the capacitor 13 is C1 ·
R1. Assuming that the resistance value of the resistor 12 is R2 and the capacitance value of the capacitor 14 is C2, the time constant of the integrating circuit 22 constituted by the resistor 12 and the capacitor 14 is C2 · R2. In the present embodiment, C1 · R1 <C
2. Set to R2.

Here, it is assumed that the voltage of the node N0 is V0, the voltage of the node N1 is V1, and the voltage of the node N2 is V2. Further, the voltage of the node N3 is set to V3,
Is set to V4, the voltage of node N5 is set to V5, and OR
The voltage of the output signal of the circuit 19 is set to V6. Voltage V3 of node N3 is applied to CPU 100 as an interrupt signal INT. CPU 100 provides a power on / off signal OF to node N5. The output signal of the output terminal Q of the flip-flop circuit 17 is provided to the relay 18 as a relay on / off signal V7.

In this embodiment, the power switch 10 corresponds to a switch, the integrating circuit 21 corresponds to a first signal generating means and a first integrating circuit, and the integrating circuit 22 corresponds to a second signal generating means and a second signal generating means. 2 integration circuits. Also, C
The PU 100 corresponds to an arithmetic processing device, and the flip-flop circuit 17 and the OR circuit 19 correspond to a cutoff signal generating unit. The relay 18 is used as power cutoff means for cutting off power in the power supply circuit.

Further, the high level of the voltage V3 at the node N3 and the high level of the interrupt signal INT correspond to the first signal, the high level of the voltage V4 at the node N4 corresponds to the second signal, and the power on / off signal OF Corresponds to the third signal, and the low level of the relay on / off signal corresponds to the cutoff signal.

Next, the operation of the power supply control device of FIG. 1 will be described with reference to the timing charts of FIGS.

FIG. 2 shows a CPU in the power supply control device of FIG.
5 is a timing chart showing a power supply cutoff process during normal operation of the power supply 100.

At time t1, when the power switch 10 is turned off, the voltage V0 of the node N0 becomes low level "L".
Rises to a high level "H". Thus, the capacitor 13 is charged via the resistor 11 and the capacitor 14 is charged via the resistor 12. here,
Since the time constant C1 · R1 of the integrating circuit 21 is smaller than the time constant C2 · R2 of the integrating circuit 22, the capacitor 13 is charged faster than the capacitor 14. Thereby, voltage V1 at node N1 rises faster than voltage V2 at node N2.

At time t2, the voltage V1 of node N1
Exceeds a predetermined threshold value TH, the voltage V
3 rises from a low level to a high level. That is, the interrupt signal INT rises from a low level to a high level. Thereby, the interrupt processing of the CPU 100 is performed. The CPU 100 executes a predetermined end process, and after completion of the end process, raises the power on / off signal OF to a high level for a certain period of time at time t3. That is, the voltage V5 of the node N5 rises to the high level for a certain time.

As a result, the voltage V6 of the output signal of the OR circuit 19 also rises to the high level for a certain time. Therefore, the flip-flop circuit 17 is reset, and the relay on / off signal V7 output from the output terminal Q falls from the high level to the low level. As a result, the relay 18
Is turned off, and the power supply in the power supply circuit is cut off.

The period T from time t2 to time t3
Reference numeral 1 denotes a management period during which the CPU 100 performs an end process.

FIG. 3 shows a CPU in the power supply control device of FIG.
4 is a timing chart showing a power cut-off process when the abnormal operation of the power supply 100 is performed.

At time t1, when the power switch 10 is turned off, the voltage V0 of the node N0 rises from a low level to a high level. Thus, the capacitor 13 is charged via the resistor 11 and the capacitor 14 is charged via the resistor 12. In this case, the integration circuit 2
1 is the time constant C2 · R of the integrating circuit 22.
The capacitor 13 is smaller than the capacitor 1
It is charged faster than 4. Thereby, voltage V1 at node N1 rises faster than voltage V2 at node N2.

At time t2, the voltage V1 of node N1
Exceeds the threshold value TH, the voltage V3 of the node N3 rises from a low level to a high level. That is, the interrupt signal INT rises from a low level to a high level. However, when the CPU 100 operates abnormally, C
The power on / off signal OF output from the PU 100 remains unchanged at the low level. That is, the voltage V5 of the node N5 is kept at a low level.

Therefore, the voltage V6 of the output signal of the OR circuit 19 is also maintained at a low level, and the relay on / off signal V7 output from the output terminal Q of the flip-flop circuit 17 is maintained at a high level.

When power switch 10 continues to be off, at time t4, voltage V2 at node N2 exceeds threshold value TH. Thereby, the voltage V4 of the node N4 rises from a low level to a high level. And OR
The voltage V6 of the output signal of the circuit 19 also rises from a low level to a high level. Therefore, the flip-flop circuit 17 is reset, and the relay on / off signal V7 output from the output terminal Q falls from the high level to the low level. As a result, the relay 18 is turned off, and the power supply in the power supply circuit is cut off.

In the above example, the time from time t1 to time t2 corresponds to the first time. Further, the time from time t1 to time t4 corresponds to the second time.

As described above, when the CPU 100 operates abnormally, the power supply in the power supply circuit is forcibly shut off by turning off the power switch 10 for a predetermined time or more.

Further, by turning on the power switch 10 again after the power switch 10 is turned off, it is possible to easily cancel the forcible shut-off operation of the power in the power circuit.

Further, the power supply control device shown in FIG. 1 includes a power supply switch 10, integration circuits 21 and 22, buffers 15 and 16,
Flip-flop circuit 17, OR circuit 19 and resistor 2
Since it can be configured with 0, the circuit scale is small and the cost is reduced.

In the power supply control device shown in FIG. 1, the buffers 15 and 16 need not always be provided.

FIG. 4 is a circuit diagram showing a configuration of a power supply control device according to a second embodiment of the present invention.

The power control device of FIG. 4 is different from the power control device of FIG.
The point is that timers 25 and 26 are provided instead of 5 and 16. As the timers 25 and 26, a digital timer or an analog timer can be used.

When the voltage V0 of the node N0 rises to the high level, the timer 25 starts the time counting operation. When the first time has elapsed while the voltage V0 is at the high level, the timer 25 changes the voltage V3 of the node N3 to the low level. To a high level. When the voltage V0 of the node N0 rises from the low level to the high level, the timer 26 starts the time counting operation. When the second time has elapsed while the voltage V0 is at the high level, the timer 26 changes the voltage V4 of the node N4. Start from low level to high level. The first time corresponds to the time from time t1 to time t2 in FIGS. 2 and 3, and the second time
Corresponds to the time from time t1 to time t4.

In this embodiment, the timer 25 corresponds to the first signal generating means and the first time measuring means, and the timer 26
Correspond to the second signal generating means and the second timing means.

The timers 25 and 26 are configured to stop the timekeeping operation when the voltage V0 of the node N0 goes low. Thus, by turning on the power switch 10 after turning off the power switch 10,
The power-off operation can be canceled.

In the power supply control device shown in FIG.
By adjusting the set times 5 and 26, the first and second times can be easily adjusted.

The power supply control device according to the present invention can be used, for example, in an industrial endoscope used for observing the inside of a production facility or a product which is not directly visible from the outside on a production line of a factory. . Since such an industrial endoscope is used in a noisy environment such as a factory, an abnormal operation is likely to occur in the CPU due to the noise. Therefore, it is particularly effective to use the power supply control device according to the present invention for an industrial endoscope.

The power supply control device according to the present invention can be used not only for an industrial endoscope but also for an endoscope for other uses, and furthermore, an information processing device such as a word processor or a personal computer, or other information processing device. Can be used for various electronic devices.

In the first embodiment, integrating circuits 21 and 22 are used as the first and second signal generating means.
In the second embodiment, the timers 25 and 26 are used as the first and second signal generating means. However, the configuration of the first and second signal generating means is not limited to this. Other circuit configurations may be used as long as the first signal and the second signal can be generated when the OFF state continues for the first time and the second time from the time of the OFF operation.

In the first and second embodiments,
Although the flip-flop circuit 17 and the OR circuit 19 are used as the cutoff signal generating means, the present invention is not limited to this. For example, instead of the flip-flop circuit 17, another storage circuit including a transistor or the like may be used. O
Another logic circuit may be used instead of the R circuit 19.

Further, instead of the relay 18, another power supply cutoff means constituted by a transistor or the like may be used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power supply control circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a power supply cutoff process during a normal operation of a CPU in the power supply control circuit of FIG. 1;

FIG. 3 is a timing chart showing a power supply cutoff process when the CPU in the power supply control circuit of FIG. 1 operates abnormally.

FIG. 4 is a circuit diagram showing a configuration of a power supply control device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional power supply control device.

FIG. 6 is a timing chart showing a power cutoff process during a normal operation of a CPU in the power control circuit of FIG. 5;

FIG. 7 is a timing chart showing a power-off process when the CPU in the power control device of FIG. 5 operates abnormally.

[Explanation of symbols]

 Reference Signs List 10 Power switch 11, 12, 20 Resistance 13, 14 Capacitor 15, 16 Buffer 17 Flip-flop circuit 18 Relay 19 OR circuit 21, 22 Integrator circuit 25, 26 Timer INT Interrupt signal OF Power on / off signal V7 Relay on / off signal

Claims (3)

[Claims] 1. A power supply control device for controlling a power supply cutoff in a power supply circuit, comprising: a switch; and generating a first signal when the off state continues for a first time from a time point when the switch is turned off. First signal generating means, and second signal generating means for generating a second signal when the off state continues for a second time longer than the first time from the time of the turning-off operation of the switch; An arithmetic processing unit that generates a third signal after performing a predetermined process in response to the first signal generated by the first signal generating unit; and an arithmetic processing unit that generates the third signal. Shut-off signal generating means for generating a shut-off signal for shutting off power in the power supply circuit in response to the second signal or the third signal generated by the arithmetic processing unit; The time is said A power supply control device, wherein the time is set to a time when the predetermined processing by the arithmetic processing device can be completed when the arithmetic processing device operates normally. 2. The first signal generating means includes: first resistance means to which current is supplied when the switch is turned off;
A first resistor charged by a current flowing through the first resistor means;
A first integrating circuit constituted by
The first signal is generated when the voltage of the first capacitor reaches a predetermined level, and the second signal generator is a second resistor to which a current is supplied when the switch is turned off. Means, and a second integration circuit constituted by a second capacitance means charged by a current flowing through the second resistance means, and when a voltage of the second capacitance means reaches a predetermined level. The power supply control device according to claim 1, wherein the second signal is generated, and a time constant of the first integration circuit is smaller than a time constant of the second integration circuit. 3. A first timer for measuring a time of an off state from a time point of an off operation of the switch and generating the first signal when the first time elapses. Means for measuring the off-state time from the time of turning off the switch, and generating the second signal when the second time has elapsed. The power supply control device according to claim 1, further comprising: