JP2001319475A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the increment factor of man-hours for design and manufacturing by securing margin of set-up/hold and relaxing the necessity of severe delay control. SOLUTION: Each of memories 1 is provided with a delay control section 11 outputting setting the prescribed delay time to each of data d0-dQ and a clock ck in accordance with a control signal ci/cd delay corresponding data a0-aQ, clock chd, and an input circuit 12 inputting each of delay data of the data a0-aQ outputted by the delay control section 11 to the memory 1 synchronizing with the clock ckd as data di0-diQ. Memory input data having optimum setup/hold margin is generated by adjusting the delay time of the delay control section 11 and varying setup/hold of the input circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a synchronous DRAM type semiconductor memory device for writing / reading input / output data in synchronization with a clock.

[0002]

2. Description of the Related Art In a synchronous DRAM for writing / reading input / output data in synchronization with a clock, the timing relationship of input data with respect to a clock is particularly important, and a flip-flop of a data input circuit is required for high reliability operation. The setup time / hold time based on the characteristics of (1) and (2) is defined. That is, if the rising of the input data is later than the specified setup time with respect to the clock timing, the predetermined setup time cannot be secured, and the flip-flop cannot perform the inversion operation at the clock timing. On the other hand, if the fall of the input data is earlier than the specified hold time with respect to the clock timing,
The predetermined hold time cannot be secured, and the flip-flop cannot perform the reinversion operation at the clock timing. That is, in any case, data cannot be determined. As a result, the output data of the input circuit may be out of synchronization with the timing of the clock, that is, delayed or advanced with respect to the clock timing, or in the worst case, the data may be lost. For this reason, generally, a specified setup time (hereinafter referred to as “setup”) / hold time (hereinafter referred to as “hold”) has a margin time (margin).

A conventional general semiconductor memory device of this kind does not have a margin control function for securing a margin of input data setup time (hereinafter, setup) / hold time (hereinafter, hold).

Such margin control is generally unnecessary for a clock frequency of about 100 to 133 MHz or a small memory capacity. However, the recent increase in clock frequency is remarkable,
A clock frequency of 800 MHz has been adopted. In addition, as the capacity of the memory has been increased, the relative distance of each memory cell to the input / output terminal, that is, the distance difference between the near-end cell and the far-end cell that are close to the terminal, also in the arrangement of the memory cells on the memory chip. Are open, and the delay time in signal transmission between each memory cell and the input / output terminal varies. For this reason, even when an input signal is applied to the input / output terminals at the same time, the time at which the input signal reaches individual memory cells varies. In addition, the above-mentioned delay time fluctuates even with a temperature change in the use environment. Furthermore, the arrival time of a clock for synchronizing with data also varies. As described above, a certain margin time, that is, a margin is set for setup / hold in response to the variation of the input data timing with respect to the clock timing of this type of memory. If the set margin is exceeded, a problem such as erroneous recognition of input data occurs, and the memory does not operate normally.

Referring to FIG. 7, which shows a block diagram of a conventional general semiconductor memory device, this conventional semiconductor memory device has Q (positive integer) +1 bit data d0 to d0.
Memory 101 having a memory cell array for storing dQ
And a memory controller 102 for performing control including input / output of each memory 101, a bus 4 composed of a plurality of bus signal lines for transmitting data between the memory controller 102 and the memory 101, and supply from the memory controller 102. A clock line 5 for transmitting a clock ck.

FIG. 8 is a block diagram showing the configuration of the memory 101.
, The memory 101 stores Q (positive integer) +1
An input circuit 120 for inputting bit data d0 to dQ in synchronization with the clock ck, and a buffer B101 for buffer-amplifying the input clock ck and outputting the clock ckd
And buffers B10 to B1Q for buffer-amplifying each of the input data d0 to dQ and outputting data e0 to eQ.

The input circuit 120 includes flip-flops F0 to FQ which receive the clock ckd at their clock terminals and output each of the input data di0 to diQ in response to the supply of the data a0 to aQ.

Next, the operation of the conventional semiconductor memory device will be described with reference to FIGS. 7 and 8 and FIG.
Supplies a clock ck to the memories 101 via the clock line 5 and data d0 to dQ (hereinafter, referred to as data d) via the bus 4. Hereinafter, for convenience of explanation, the number of memories 101 will be referred to as memories 101A, 101B, 1
01C. These memories 101A, 101
B, 101C are connected to the memory controller 10
Points A, B, and C at which the distance from the output end of No. 2 sequentially increases. Assuming that the rising edges of the clock ck at points A, B, and C are t1, t2, and t3, respectively, in the example of this figure, for the rising edge t1 of the clock ck, the data d at the point A is the flip-flop of the input circuit 120. The data d at the point B, which is at the center of the standard value of the setup TS / hold TH but farther from the standard value, is advanced from the center of the standard value of the setup / hold with respect to the rising t2 of the clock ck, and delayed from the hold TH. And does not satisfy the standard. On the other hand, the data at point C is delayed from the center of the standard value of the setup / hold with respect to the rising t3 of the clock ck and has advanced beyond the limit of the setup TS, and does not satisfy the standard. As described above, when the data timing difference (skew) with respect to the rise of the clock ck exceeds the setup / hold standard value, the flip-flop of the input circuit 120 does not operate normally and the input data of the memory is uncertain. And does not operate normally.

As is well known, the setup TS / hold TH defines the timing relationship between the clock ck and the data d. For a stable operation, the timing difference (skew) between the clock ck and the data d is set up. It must be within the TS / hold TH standard value.

As described above, the conventional semiconductor memory device does not have the margin control function for securing the setup / hold margin of the input data. Since the hold margin is reduced, strict delay time management and the like of each signal path in the design and manufacturing processes are required to perform stable operation, which increases the design and manufacturing man-hours.

[0011]

Since the conventional semiconductor memory device described above does not have a margin control function for securing a setup / hold margin for input data, the clock frequency is increased and the memory capacity is increased. As a result, the setup / hold margin is reduced, and strict delay time management of each signal path in the design and manufacturing process is required to perform stable operation, which causes an increase in design and manufacturing man-hours. There was a disadvantage.

An object of the present invention is to solve the above-mentioned drawbacks and to alleviate the need for strict delay management by securing a setup / hold margin even when the clock frequency is increased and the memory capacity is increased. It is an object of the present invention to provide a semiconductor memory device capable of eliminating an increase in design and manufacturing steps.

[0013]

A semiconductor memory device according to the present invention has a plurality of memories having a memory cell array for storing n (positive integer) bit data, and writes input / output data in synchronization with a clock. / Synchronous DRA to read
In an M-type semiconductor storage device, each of the memories is
A delay control unit that sets a predetermined delay time for each of the n-bit data and the clock according to the supplied control signal and outputs corresponding delay data and a delay clock; and the n that is output by the delay control unit. An input circuit for inputting each of the bit delay data in synchronization with the delay clock, and adjusting a delay time of the delay control unit to set up a setup time / hold time (hereinafter, setup / hold) of the input circuit. It is characterized in that memory input data having an optimal setup / hold margin is generated by changing it.

Further, the delay control section inputs a clock, applies a delay according to a first control signal, and outputs the delayed clock, and inputs each of the n-bit data. A second delay generating circuit for providing a delay according to a second control signal and outputting the delayed clock;
A register value input circuit for outputting the first and second control signals based on a set value set from outside may be provided.

Further, the input circuit receives each of the delayed clock and the n-bit delayed data at a clock terminal and outputs each of the corresponding n-bit memory input data in synchronization with the delayed clock. May be provided.

Each of the first and second delay generation circuits constituting the delay control section buffers and amplifies an input clock or data (hereinafter, clock / data) and outputs a buffer clock / buffer data. ,
In response to the control of the count signal, the buffer clock /
A delay circuit that delays buffer data by a predetermined delay time and outputs the delayed clock / delayed data;
A counter that counts up / down according to the control of the control signal and outputs the count signal.

Further, the delay circuit applies first and second capacitive loads to a signal line for transmitting the buffer data in response to the control of the count signal, whereby the delay data corresponding to the buffer data is provided. And first and second delay elements for respectively setting first and second delay times set in advance.

Still further, the delay element of the delay circuit has a transistor connected to the signal line at a drain and receiving the count signal at a gate, and one end connected to the source of the transistor and the other end grounded. A capacitor having a predetermined capacity may be provided.

[0019]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The semiconductor memory device according to the present embodiment is characterized by including a delay control unit 11 for setting a delay time of data and a clock input to the memory 1.
The delay control unit 11 externally changes the setup time / hold time (hereinafter referred to as setup / hold) of the input circuit, so that a memory input having an optimal setup / hold margin according to a memory configuration, a temperature change, or the like. Generate data.

Next, referring to FIG. 1 showing a block diagram of an embodiment of the present invention, the semiconductor memory device of the present embodiment shown in FIG. 1 has Q (positive integer) +1 bit data d0 to dQ , A memory controller 2 for controlling input / output of each memory 1, and a low-speed signal for low-speed data transmission such as a command supplied to each memory 1 and the memory controller 2. A line 3, a bus 4 composed of a plurality of bus signal lines for transmitting high-speed data between the memory controller 2 and the memory 1, and a clock line 5 for transmitting a clock ck supplied from the memory controller 2 are provided.

Referring to FIG. 2 showing a block diagram of the configuration of the memory 1, the memory 1 receives Q (positive integer) + 1-bit data d0 to dQ and a control signal ci, cd supplied and supplied with a clock ck. Data d0-d
It comprises a delay control unit 11 which supplies data a0 to aQ and a clock ckd to Q and a clock ck, respectively, and an input circuit 12 which inputs data a0 to aQ in synchronization with the clock ckd.

The delay control unit 11 receives a clock ck, applies a delay according to the control signals cik and cdk, and outputs a clock ckd.
Each of dQ is input and control signals ci0 to ciQ, cd0
delay generating circuits 1110 to 111Q for giving respective delays according to each of cdQ and outputting each of data a0 to aQ, and register values rk, r0 to rQ (described later) set from outside via low-speed signal line 3 Hereinafter, r) corresponding control signals cik and cdk and control signals ci0 to ciQ and cd0
And a register value input circuit 13 for outputting.

The input circuit 12 includes flip-flops F0 to FQ that receive clock ckd at their clock terminals and output each of input data di0 to diQ in response to the supply of data a0 to aQ.

Delay generation circuits 110, 110 to 111Q
FIG. 3 is a block diagram showing an example of the configuration of a delay generation circuit 1110 which is representative of FIG. 3. The delay generation circuit 1110 shown in FIG. 3 includes a buffer B1 for buffer-amplifying input data d0 and outputting data e0, and a count signal. nc, the data e0 from the buffer B1 is delayed and the data a
0, and a control signal ci0 / cd0
And a counter 16 that counts up / down in response to and outputs a count signal nc.

FIG. 4 is a block diagram showing the configuration of the delay circuit 15.
Referring to (A), delay circuit 15 applies a capacitive load to signal line W1 transmitting signal e1 in response to control of each of count signals nc1, nc2, and nc3 (count signal nc in a representative case). Accordingly, delay elements D1, D2, and D3 are provided for setting delay times d1, d2, and d3 in signal a1 corresponding to signal e1, respectively.

In this embodiment, for convenience of explanation,
The delay time set by the delay circuit 15 is set to three delay times d1, d2, and d3 in ascending order.

FIG. 4 is a circuit diagram showing the configuration of delay element D1.
Referring to (B), the delay element D1 has a transistor M1 connected to the signal line W1 at the drain and receiving the count signal nc at the gate, and one end connected to the source of the transistor M1 and the other end to the ground G. A capacitor C1 having a predetermined capacity is provided. Since the capacitance of the capacitor C1 increases as the delay time increases, the delay elements D1, D2, D
It increases in the order of 3.

Next, the operation of the present embodiment will be described with reference to FIG. 1 to FIG. 4 and FIG. 5 showing the waveforms of respective parts in a time chart. First, each of the delay generating circuits 110 and 1110 of the memory 1 will be described. During normal operation after the 111Q is optimally adjusted, the memory controller 2 clocks input data d0 to dQ (hereinafter, referred to as data d) via the bus 4 via the clock line 5. ck is supplied to each of the memories 1. Hereinafter, for convenience of explanation,
The number of memories 1 is three, that is, memories 1A, 1B, and 1C.

The delay generation circuits 110, 1110 to 111Q of the delay control units 11 of the memories 1A, 1B, 1C
Since the optimal adjustment has been completed, only the internal buffer B1 performs the same operation as the buffers B10 to B1Q in the conventional memory 101, the delay generation circuit 110 outputs the clock cdd, and each of the delay generation circuits 110 to 111Q stores the data a0 To aQ.

The flip-flops F0 to F of the input circuit 12
Q latches data a0-aQ in synchronization with clock ckd, and inputs data di0-di to corresponding memory cells.
Output Q.

The input terminals of these memories 1A, 1B and 1C are points A, B and C at which the distance from the output terminal of the memory controller 2 increases in the same manner as in the prior art. A,
Assuming that the rising edges of the clock ck at the points B and C are t1, t2 and t3, respectively, the rising edges t1, t2 and t3 of the clock ck at the points A, B and C are different from those A and B in the example of FIG. , C at the center of the standard value of the setup TS / hold TH of the flip-flops F0 to FQ of the input circuit 12.

That is, since all of the memories 1A, 1B, 1C have been optimally adjusted, the memories 1A, 1B,
Input data a0 to 1C flip-flops F0 to FQ
aQ is sufficient for flip-flop F0 for clock ckd
.About.FQ, which is within the standard range of setup TS / hold TH, so that stable operation is guaranteed.

Next, referring again to FIGS. 2 to 4, flip-flops F0 to FQ of the semiconductor memory device of the present embodiment will be described.
The operation when the standard of setup TS / hold TH is not satisfied will be described. First, as a result of the timing verification described later, when the timing of data, for example, data di0 is earlier, the delay corresponding to data di0 of delay controller 11 The generator 1110 is adjusted to delay the data.

Each transistor M1 of delay elements D1 to D3 constituting delay circuit 15 of delay generation circuit 1110
Turns on / off according to the level of the count signal nc supplied from the counter 16. Hereinafter, for convenience of description, assuming that the transistor M1 is an N-channel MOS transistor, the transistor M1 conducts when the level of the count signal nc is H level and shuts off when the level of the count signal nc is L level.

First, one of the delay elements D1 to D3 is selected according to the delay time to be set. That is, one of the count signals nc1 to nc3 is set to the H level. Here, it is assumed that the minimum delay time d1 is set, the count signal nc1 is set to the H level, and the delay element D1 is set.
Select

First, a delay time set from the outside via the low-speed signal line 3 to the register value input circuit 13 of the delay control unit 11 for the correction of the delay generation circuit 1110 corresponding to the data di0 to be corrected corresponds to the delay time. Register value r to be set. Here, a register value r0 corresponding to the delay time d1 to be corrected is set. Register value input circuit 13
Is a control signal ci0 / cd0 corresponding to the register value r0.
Is supplied to the delay generation circuit 1110. Here, the control signal ci is a signal for counting up so as to increase the count value cn of the counter 16 of the delay circuit 15, and the control signal cd is a signal for counting down so as to decrease the count value cn. In this example, the register value input circuit 13 compares the register value r0 with the count value of the counter 16 of the delay generation circuit 1110, and increments the counter 16 by the control signal ci0 / cd0 until the predetermined count signal nc0 becomes H level. / Count down.

The transistor M1 of the delay element D1 constituting the delay generation circuit 1110 conducts in response to the H level of the count signal nc1, and connects the capacitor C1 to the signal line W1 via the transistor M1. As a result, the delay circuit 15 loads the signal line W1 with the capacitance of the capacitor C1 and temporarily stores the charge corresponding to the input signal e1 in the capacitor C1 to delay the signal e1 by the delay time d.
The signal is delayed by one and output as an output signal a1.

On the contrary, data di0 to di7
If all the timings are late, the clock ck delay generation circuit 110 is similarly adjusted to delay the clock ckd. Here, the delay time d is used as the corrected delay time value.
2 shall be set. Therefore, the delay generation circuit 110
Is selected.

A register value rk corresponding to the delay time d2 set for correction of the delay generation circuit 110 corresponding to the clock ckd to be corrected is set in the register value input circuit 13 via the low-speed signal line 3 from outside. I do. The register value input circuit 13 outputs a control signal c corresponding to the register value rk.
ik / cdk is supplied to the delay generation circuit 110, the register value rk is compared with the count value of the counter 16 of the delay generation circuit 110, and the control signal cik is maintained until the count signal nc2 for selecting the delay element D2 becomes H level. / Cdk causes the counter 16 to count up / down.

The transistor M1 of the delay element D2 conducts in response to the H level of the count signal nc2, and connects the capacitor C1 to the signal line W1 via the transistor M1. As a result, the delay circuit 15 loads the signal line W1 with the capacitance of the capacitor C1 and temporarily stores the charge corresponding to the input signal ck in the capacitor C1, thereby delaying the signal ck by the delay time d2 and outputting the output signal cdd. Output as

When the adjustment of all the delay controllers 11 of the memories 1A, 1B, 1C is completed, these memories 1A, 1B,
1C are already optimally adjusted.
The input data a0 to aQ of the flip-flops F0 to FQ of A, 1B, and 1C are sufficiently within the standard range of the setup TS / hold TH of the flip-flops F0 to FQ with respect to the clock ckd, so that a stable operation is guaranteed.

Next, referring to FIG. 6 which shows an example of a method of verifying the operation of the semiconductor memory device of the present embodiment in a flow chart, the standard of setup TS / hold TH of flip-flops F0 to FQ is satisfied. The operation in the case of verifying the presence / absence will be described. For this verification, flip-flops F0 to FQ are used as registers for temporarily storing verification data. First, "0" is applied to the flip-flops F0 to FQ from the outside via the low-speed signal line 3.
To initialize (step S1).

For convenience of description, memory input data di
The number of bits 0 to diQ is 8 bits, that is, input data di0 to di7. Therefore, the flip-flops to be verified are F0 to F7.

Next, the delay control unit 11
8 bits of test data, for example, 01101001 as input data d0 to d7 of the flip-flop F0
To FQ (step S2).

Next, the data di0 to di0 are transmitted via the bus 4.
The above test data which is di7, in this example 011010
01 is read (step S3).

Next, the clock c for the read data
Output data di0 to di for kd timing
7 (011101001) determines whether or not the setup / hold standard is satisfied (step S4). If the setup / hold standard is satisfied, the process ends.

As a result of the determination in step s4, the setup /
If the hold standard is not satisfied, it judges the speed of the output data di0 to di7 (01101001) with respect to the timing of the clock cdd for the read data (step S5). Data (eg, data di
If the timing of (0) is earlier, as described above, the corresponding delay generation circuit of the delay controller 11 (in this example, 111)
0) is adjusted to delay the data (step S6). Conversely, if the data timing is late, the clock is delayed by adjusting the clock ck delay generation circuit 110 (step S7).

The above processing of steps S2 to S7 is repeated until the standards of the setup TS / hold TH of the flip-flops F0 to F7 to be verified are satisfied.

In the above verification, the flip-flops F0 to FQ of the input circuit 12 are used for temporarily holding verification data, but an external register built in a memory tester or the like may be used for this purpose. Further, a register may be provided in a register value input circuit or the like.

[0051]

As described above, in the semiconductor memory device of the present invention, each of the memories sets a predetermined delay time for each of n-bit data and a clock in accordance with the control signal, and sets the corresponding delay data and A delay control unit that outputs a delay clock; and an input circuit that inputs each of the n-bit delay data in synchronization with the delay clock. By externally adjusting a delay generation circuit that configures the delay control unit, Since the relative delay between the clock and the data is eliminated by setting the optimal condition of the setup / hold, there is an effect that the setup / hold margin can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a memory in FIG. 1;

FIG. 3 is a block diagram illustrating an example of a configuration of a delay generation unit in FIG. 2;

FIG. 4 is a block diagram illustrating an example of a configuration of a delay circuit of FIG. 3 and a delay element of the delay circuit.

FIG. 5 is a time chart illustrating an example of an operation in the semiconductor memory device according to the present embodiment;

FIG. 6 is a flowchart illustrating an example of an operation verification method of the semiconductor memory device according to the present embodiment;

FIG. 7 is a block diagram showing an example of a conventional semiconductor memory device.

FIG. 8 is a block diagram illustrating an example of a configuration of a memory in FIG. 8;

FIG. 9 is a time chart showing an example of an operation in a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 101 Memory 2, 102 Memory controller 3 Low-speed signal line 4 Bus 5 Clock line 11 Delay control unit 12, 120 Input circuit 13 Register value input circuit 15 Delay circuit 16 Counter 110, 1110-111Q Delay generation circuit B1 Buffer C1 Capacitor D1 , D2, D3 Delay elements F0-FQ Flip-flop M1 Transistor W1 Signal line

Claims (6)

[Claims] 1. A synchronous DRAM type semiconductor memory device having a plurality of memories having a memory cell array for storing data of n (positive integer) bits and writing / reading input / output data in synchronization with a clock. A delay control unit that sets a predetermined delay time for each of the n-bit data and a clock according to a supplied control signal and outputs corresponding delay data and a delay clock; An input circuit for inputting each of the n-bit delay data output by the control unit in synchronization with the delay clock, and adjusting the delay time of the delay control unit to set up / hold time of the input circuit. (Hereinafter referred to as setup / hold) to generate memory input data with an optimal setup / hold margin. A semiconductor memory device characterized by comprising: 2. A first delay generating circuit for receiving a clock, applying a delay in accordance with a first control signal, and outputting the delayed clock, the delay control unit receiving each of the n-bit data, A second delay generating circuit for providing a delay according to a second control signal and outputting the delayed clock; and a register value for outputting the first and second control signals based on a set value set from outside. 2. The semiconductor memory device according to claim 1, further comprising an input circuit. 3. The input circuit receives a supply of each of the delay clock and the n-bit delay data at a clock terminal, respectively, and synchronizes with the corresponding delay clock.
2. The semiconductor memory device according to claim 1, further comprising n flip-flops each outputting bit memory input data. 4. A buffer for amplifying an input clock or data (hereinafter, clock / data) and outputting a buffer clock / buffer data, each of the first and second delay generation circuits responding to control of a count signal. And the buffer clock /
A delay circuit that delays the buffer data by a predetermined delay time and outputs the delay clock / delay data; and a counter that counts up / down and outputs the count signal according to control of a first or second control signal. 3. The semiconductor memory device according to claim 2, wherein: 5. The delay circuit corresponding to the buffer data by applying each of a first and a second capacitive load to a signal line transmitting the buffer data in response to the control of the count signal. The first, preset in
5. The semiconductor memory device according to claim 4, further comprising first and second delay elements for respectively setting a second delay time. 6. The delay element includes a transistor connected to the signal line at a drain and receiving the count signal at a gate, a capacitor having a predetermined capacitance having one end connected to the source of the transistor and the other end connected to ground. 6. The semiconductor memory device according to claim 5, comprising: