JP2001320021A - ASIC test circuit - Google Patents

Abstract

An ASIC test circuit capable of shortening a test time by an ASIC tester and performing an interactive test in a system. SOLUTION: An A is used for testing an integrated circuit such as an ASIC.
The SIC test circuit includes switch circuits 3, 20, 4 for switching between a normal input signal of input / output terminals A, B, n and test input / output, and a test terminal 2 for outputting a switch signal of the switch circuit. In the test mode, the test terminal is set to the ground (Lo) level, and V is applied from terminals A and B.
The DD level is propagated from the terminal n to the ground level to the internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an ASIC test circuit capable of shortening a test time of an advanced integrated circuit such as an ASIC and performing a test in a system.

[0002]

2. Description of the Related Art In a conventional ASIC test circuit, for example, in the case of a test circuit as shown in the schematic diagram of measuring current consumption shown in FIG. 3, a device under test DUT (Device Un
derTest), each terminal A to n1 of the DUT 100
02, the terminals A to n connected by the LSI tester 101.
By applying a predetermined potential to the current 102, the current consumption Ic
c was measured. The output from the LSI tester 101 is a specific combination of signals (for example, terminal A, terminal B
Is set to the VDD level and the terminal n is set to the ground level, so that when the combination of H, H, and L) is used as a whole, the standby state is established.

[0003]

However, in the case of the above conventional example, an LSI tester is always required for testing an integrated circuit such as an ASIC, and the occupation time of the tester is ASIC.
As the number of varieties increases, the number of varieties increases, and there is a problem that it is becoming a major obstacle in terms of test cost. Furthermore, since many ASICs are built into the system and operated, it is impossible to make DUT-specific measurements in this state, and it is difficult to test the interactive DUT on the system, and it is difficult to test the failure of the system. There is a problem that it is difficult to specify the failure mode or the failure mode of the DUT, so that satisfactory quality cannot be obtained. Therefore, an object of the present invention is to provide an ASIC test circuit capable of shortening a measurement time by a tester, reducing a test cost, and enabling an interactive DUT to be tested on a system to improve quality. And

[0004]

According to one aspect of the present invention, there is provided an ASIC test circuit for testing an integrated circuit such as an ASIC. It has a switch circuit for switching between input and output, and a test terminal for outputting a switch signal for the switch circuit. According to this ASIC test circuit,
A simple test circuit block is added to the logic block of an integrated circuit such as an ASIC, so that the normal input signal of the input / output terminal and the test input / output can be switched by the switch circuit. As well as interactive testing on the system. The invention according to claim 2 is an ASIC.
An ASIC test circuit for testing an integrated circuit such as that described above includes a switch circuit for switching between normal input / output of input / output terminals and a test input / output, and a register circuit for outputting a switch signal of the switch circuit. According to this ASIC test circuit, by incorporating a simple test circuit block into a logic block of an integrated circuit such as an ASIC, the normal input signal at the input / output terminal and the test input / output can be switched by the output of the register circuit. As a result, the required test can be performed without using a tester, and the ASIC can be disconnected from the system by completely interrupting the normal incoming signal to perform an interactive test. The test terminal according to claim 3, wherein the test terminal is a pMOS and an nMOS constituting the switch circuit in a test mode.
Is turned on by a switching signal to transmit the test H and L signals to the internal circuit, and during normal operation, the pMOS and nMOS are turned off and the incoming signal is transmitted to the internal circuit as it is. According to the ASIC test circuit, normally, a normal incoming signal can be input / output to / from the ASIC regardless of the test circuit. In the test mode, the pMOS and the nMOS are turned on by a switching signal (eg, Lo signal) from the test terminal. By becoming
Instead, H and L test signals for testing are applied to the internal circuit from the test circuit, and the required test can be performed by the DUT alone or interactively. According to a fourth aspect of the present invention, in the register circuit, the plurality of output signals of the register circuit by the internal write signal in the test mode are used for each of the analog switches, the pMOS, the nMOS, and the signal input for the switch circuit. The analog input signal is applied to an analog switch, the analog switches are turned off to shut off a normal incoming signal, the pMOS and nMOS are turned on, and test H and L signals are propagated to an internal circuit. A switch is turned on to propagate a predetermined signal such as a test clock, and during normal operation, the pMOS, nMOS and analog switch for signal input are turned off and the incoming signal is directly propagated to an internal circuit. I have. This AS
According to the IC test circuit, the normal incoming signal is normally passed, and in the test mode, the normal incoming signal is cut off and placed by shutting off each analog switch by a switching signal from the register circuit, and the pMOS and the nMOS Is turned on, H and L signals for testing can be applied to the internal circuit, and a test signal such as a predetermined clock can be applied to the internal circuit by turning on another analog switch for inputting and outputting a test signal. , Various tests can be performed without depending on the tester. At that time, the DUT is normally shut off completely, regardless of the presence or absence of an incoming signal.
Enables testing alone or interactively.

[0005]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the ASIC test circuit according to the first embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes an ASIC test circuit incorporated in the DUT 9, and reference numeral 2 denotes a test terminal thereof which is normally open and in a state where a power supply voltage level VDD is applied. 3 is p1 (pMOS), 20 is p2 (pMO
S) and 4 are n1 (nMOS) switch elements, which constitute a switch circuit that is turned on / off by a switching signal from a test terminal 2. 5, 6, and 7 are terminal A, terminal B,
Represents a terminal n. 8 is an inv (inverter) for signal inversion. Next, the operation will be described. Here, based on the circuit of FIG. 1, the same DUT (A
An example of the standby current measurement of the SIC will be described. First, during normal operation, the test terminal 2 is open (no potential is applied). Therefore, in this case, a power supply voltage level of pull-up level (hereinafter, referred to as VDD level) is applied to the test terminal 2. At this time, the switch p1 (pM
OS) 3 and the gate of p2 (pMOS) 20 have VD
Since the ground level is applied to the gate of n1 (nMOS) 4 via the inverter 8, the level of D
Both the S and nMOS are cut off and the terminals A5 and B6
To propagate the signal entering terminal n7 to the internal circuit. Next, in the test mode, when the test terminal 2 is set to the ground level (for example, this is set to L level and the VDD level is set to H level), p1 (pMOS) 3 and p2 (pM
OS) 20 is at the ground level and the nMOS 4
Becomes the VDD level, and the switch p1
(PMOS) 3 and p2 (pMOS) 20, nMOS
4 are both turned on, and if no potential is applied to the terminals A5 to n7 at this time, the voltage from the terminals A5 and B6 is
DD is propagated to the internal circuit. Similarly, the ground potential is propagated from the terminal n7 to the internal circuit, and the signal combination at this time becomes H, H, and L as in the conventional case of FIG. 3, and the same state as in the case where the tester 101 is used can be created. If the current is measured in this state, the standby current can be easily measured. Further, at this time, not only measurement by the DUT itself, but also interactive measurement on the system is possible. (Of course, various tests by a tester input from the terminals An are also possible).

As described above, according to the present embodiment, in the normal state where the test terminal 2 is open (H), the state becomes the same as that of the DUT 100 shown in FIG. The standby current can be measured by applying a signal. When the test terminal 2 is set to the test mode of (L), a test signal of the same combination as H, H, and L applied from the tester in FIG. 3 is applied. Measurement becomes possible and interactive measurement becomes possible. Therefore, in general, by incorporating a test circuit like the present embodiment capable of outputting the same test signal as a specific combination signal given to the DUT from the LSI tester in the ASIC, the LSI tester can be used. The same required tests as performed can be performed on the DUT alone or interactively in the system.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of the ASIC test circuit according to the second embodiment of the present invention. 10 is D
An ASIC test circuit built in the UT 19. 1
1 is a switch circuit for pMOS (p2) and nMOS (n
2) Complementary analog switch elements,
It is composed of a combination of inv15 and is turned off when the ground level is applied to the gate of inv15 and turned on at the VDD level. The switch circuits 12 and 13 have the same configuration. The switch circuit 14 has a similar pMOS
(P3), composed of nMOS (n3) and inv17. Reference numeral 16 denotes a register circuit which is constituted by a flip-flop of a predetermined bit, takes in predetermined data, and sets desired data as r1 to r3 by an internal write signal WR.
Through an inverter, inv15 is applied to the gates of the same switches p1 (pMOS) 3 and n1 (nMOS) 4 as in FIG. The signal rn is applied to the gate of inv17. Next, the operation will be described. First, when the register circuit 16 is reset, the output signals r1 to rn based on the register data are at the ground level, the VDD level is applied to the gate of the inv15 and the switch p1, and the switch n1
Since the ground level is applied as is, the switch circuits 11 to 13 are turned on, and the switches p1 and n1 are cut off. If such a reset state is maintained as it is during normal operation, the switches p1, n1
Is cut off, the switch circuit 14 is cut off,
The signals at the terminals An are transmitted to the internal circuit as they are. Next, in the test mode, first, as the register data, the VDD level is set to r1, the VDD level is set to r2, and the register data is set to r2.
3 is written with the internal write signal and the VDD level is written into rn with the internal write signal. In this case, terminal A5 is connected to inv
Since the gate level of the switch 15 becomes the ground level, the switch circuit 11 is cut off. Further, the gate level of the switch p1 becomes the ground level and turns on, so that the VDD level is propagated to the internal circuit. Similarly, the switch circuit 12 of the terminal B6 is cut off, the gate of the switch n1 is turned on at the VDD level, and the ground level is transmitted to the internal circuit. The terminal n is connected to the VDD level r.
Since n is applied as it is, the switch circuit 14 for signal input is turned on, and a predetermined test clock signal or the like is propagated to the internal circuit via inv18. As described above, according to the second embodiment, the test terminal is omitted, and the output signal from the register circuit is used. In the test mode, the VDD level is transmitted from the terminal A5 to the internal circuit, and the terminal B6 is output from the terminal B6. Since the ground level is propagated to the internal circuit and the clock signal is propagated from the terminal n7 to the internal circuit, the combination of the signals becomes H, L and the clock signal, and the signal set in the first embodiment is used. H, H,
A combination of signals different from L can be applied to the DUT. As a result, measurements other than the standby current measurement (for example, voltage, input / output resistance measurement, etc.) can be performed without a tester. In addition, a wide range of tests using a signal comparison method using a clock signal can be performed. Since these tests can be performed irrespective of an incoming signal, a test using a DUT alone and various interactive tests in a system can be performed.

[0008]

As described above, according to the present invention,
Since the ASIC test circuit is configured to switch between a normal input signal at the input / output terminal and a test input / output, and to switch the switch circuit by a switching signal from the test terminal or a switching signal from the register circuit. In the case where the switching signal from the test terminal is used, the measurement time occupied by the tester can be shortened, the interactive measurement on the system becomes easy, and the quality can be improved. In addition, when the switching signal from the register circuit is used, the test terminal can be omitted and the terminal input can be cut off by the circuit signal, so that the measurement time by the tester can be shortened and various interactive signals can be obtained regardless of the presence or absence of the incoming signal. The test can be performed and the quality can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an ASIC test circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an ASIC test circuit according to a second embodiment of the present invention.

FIG. 3 is a measurement diagram of current consumption of a conventional ASIC.

[Explanation of symbols]

 1, 10 ASIC test circuit 2 test terminal 3 switch p1 4 switch n1 5 terminal A 6 terminal B 7 terminal n 8, 15, 17, 18 inv 9, 19 DUT 11, 12, 13, 14 switch circuit 16 register circuit 20 switch p2

Claims (4)

[Claims] 1. An ASIC test circuit for testing an integrated circuit such as an ASIC, comprising: a switch circuit for switching between a normal input / output and a test input / output of an input / output terminal; and a test terminal for outputting a switching signal of the switch circuit. An ASIC test circuit comprising: 2. An ASIC test circuit for testing an integrated circuit such as an ASIC, comprising: a switch circuit for switching between normal input / output of the input / output terminal and a test input / output; and a register circuit for outputting a switching signal of the switch circuit. An ASIC test circuit comprising: 3. The test terminal turns on a pMOS and an nMOS constituting the switch circuit in a test mode by a switching signal, and propagates test H and L signals to an internal circuit.
2. The ASIC test circuit according to claim 1, wherein the OS is turned off and the incoming signal is propagated to the internal circuit as it is. 4. The register circuit outputs a plurality of output signals of the register circuit by an internal write signal in a test mode to each analog switch constituting the switch circuit.
Apply to pMOS, nMOS and analog switch for signal input, turn off each analog switch to cut off normal incoming signal, turn on pMOS and nMOS to propagate test H and L signals to internal circuit Then, the signal input analog switch is turned on to transmit a predetermined signal such as a test clock to an internal circuit, and during normal operation, the pMOS, nMOS and the signal input analog switch are turned off and the incoming signal is turned off. Is transmitted to the internal circuit as it is.
SIC test circuit.