JP2002040998A - Lcd display control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LCD (liquid crystal display) display control circuit capable of solving the problem that it is needed to design a display circuit again when an interface system with an LCD is fixed and a specification change is generated in the original specification of a display device and the changing of the interface system of the LCD becomes necessary and capable of coping with various LCD panels flexibly. SOLUTION: An LCD display control circuit selects display data based on a display mode signal 8 by changing the constitution of display data FIFOs 51, 52 for holding the display data temporarily and providing display data selectors 9 to 13 at the output parts of these display FIFOs 51, 52. Thus, the LCD display control circuit capable of coping with plural kinds (a 4-bit single scanning, an 8-bit dual scanning, and an 8-bit single scanning) of interface systems is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD (Liquid Crystal Display Panel) display control circuit, and more particularly to an improvement in an interface system with an LCD.

[0002]

2. Description of the Related Art LCDs are now replacing the CRT (CRT), which has been the mainstream, because of its light weight and low power consumption. In particular, in the fields of portable personal computers (PCs), word processors (WPs), personal digital assistants (PDTs), etc., it is no exaggeration to say that display devices are monopolized. 10, 11 and 12 show examples of a conventional LCD display circuit.
Figure 10 shows an LC compatible with a 4-bit single scan LCD
It is a block diagram of the example of a D display control circuit. FIG.
FIG. 3 is a block diagram of an example of an LCD display control circuit compatible with an 8-bit single scan LCD. FIG. 12 is a block diagram of an example of an LCD display control circuit compatible with an 8-bit dual scan LCD.

The LCD display control circuit shown in FIGS. 10 and 11 comprises a display data read control unit 1, a display address generation unit (UD) 2, a display data memory unit 3, a FIFO (first in first out) control unit 4, and a display data FIFO 5. Is done. The FIFO control unit 4 includes a display timing signal 7
Is input and the display data request signal 411 which is the output
Is supplied to the display data read control unit 1 with the FIFO control signal (write pointer) 412 and the FIFO control signal (read pointer) 413 to the display data FIFO 5, and the display data FIFO 5 outputs the display data signal 511. The display data read control unit 1 outputs an address generation instruction signal 111 to the display address generation unit 2. The display address generation unit 2 outputs a display address signal 211 to the display data memory unit 3. Also,
The display data memory unit 3 outputs display data to the display data FIFO 5.

On the other hand, in the case of the 8-bit dual scan timing shown in FIG. 12, the display data read controller 1, display address generator (LD) 21, display address generator (UD) 22, display address selector 6, display data selector Memory unit (frame buffer) 3, FIFO control unit (U
D) 41, FIFO control unit (LD) 42, display data F
IFO (UD) 51 and display data FIFO (LD)
52. The display timing signal 7 is input to the FIFO control units 41 and 42. Display data request signals 411, 4 which are outputs of these FOFO control units 41, 42
21 is input to the display data read control unit 1 and the display data FIFO (UD) 51 and the display data FI
FIFO control signals (write pointers) 412 and 422 and FIFO control signals (read pointers) 413 and 423 are input to the FO (LD) 52, respectively. Then, the display data FIFOs 51 and 52 output display data signals 511 and 521, respectively. The display data read control unit 1 outputs an address generation instruction signal 111 to the display address generation units 21 and 22 and outputs an address selection signal 1 to the display address selector 6.
12 is output. The display address selector 6 receives display address signals 211 and 221 from the display address generators 21 and 22, respectively, and outputs a display address signal 611 to the display data memory 3. Further, the display data memory unit 3 outputs display data to the display data FIFOs 51 and 52.

As described above, in the conventional LCD display control circuit, these FIGS.
Is used. As a similar prior art, Japanese Patent Laid-Open Publication No. Hei 5-94277 proposes "a portable computer having a function of supporting a plurality of types of flat panel displays". This discloses a technique for switching between a monochrome / color LCD panel interface.

[0006]

However, in the prior art as described above, since the interface system with the LCD is fixed, a specification change occurs from the initial device specification, or the LCD interface system needs to be changed. In such a case, there is a problem that it is necessary to redesign the display circuit.

[0007]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an LCD display control circuit corresponding to a plurality of types of LCD interface systems. Another object of the present invention is to provide an LCD display control circuit which can flexibly cope with a need to change the interface method of the LCD by achieving the above-mentioned objects. is there.

[0008]

According to the present invention, there is provided an LCD display control circuit comprising a FIFO receiving a display timing signal.
A control unit; a display data read control unit to which a display data request signal from the FIFO control unit is input; a pair of display address generation units to which an address generation instruction signal from the display data read control unit is input; A display address selector for selecting a display address signal from the display address generation unit by an address select signal from a display data read control unit; a display data memory unit to which a display address signal from the display address selector is input; A display data FIFO for receiving display data from the display data memory unit and temporarily storing the display data, and for controlling the display of the LCD panel; a display data selector is provided at a subsequent stage of the display data FIFO; By controlling this display data selector based on the display mode signal, LC It allows for multiple types of LCD interface manner of panels.

According to a preferred embodiment of the LCD display control circuit of the present invention, the display data FIFO includes a display data FIFO (UD) and a display data FIFO (LD), and the display data FIFO (LD) is written. The divided data is divided every four bits, and four display data signals are output to the display data selector. Also, LC
The D panel can be selected from an interface system of 4-bit single scan, 8-bit dual scan, and 8-bit single scan.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of an LCD display control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of an LCD display control circuit according to the present invention.
The LCD display control circuit includes a bus interface control unit 101, a frame buffer access arbitration unit 102, a mode register unit 103, an LCD display timing signal generation unit 104, a display data FIFO unit 105, a display address generation unit 106, a CPU (central processing unit). (Apparatus) An address generation unit 107, a CPU write FIFO unit 108, a memory control signal generation unit 109, a display data memory unit 110, and a memory address selector 130. And
Outputs of the LCD display timing signal generator 104 and the display data FIFO 105 are input to the LCD panel 120. Here, the LCD display timing signal generator 10
4. The display data FIFO unit 105 and the display address generation unit 106 constitute a display control unit. The CPU address generation unit 107 and the CPU write FIFO unit 10
8.

An LCD interface system and a display start address are set by the mode register section 103, and each functional block operates according to the address. Display data is written from the bus interface unit 101 to the CPU write F.
The data is written to the IFO unit 108. At this time, the display control unit (10
4 to 106), the signal generated by the memory control signal generator 109 causes C
The memory address specified by the PU address generation unit 107 is written to the display data memory unit 110 by the CPU write FIFO unit 108.

When there is a data read request from the display control unit (104 to 106) by the frame buffer access arbitration unit 102, the memory control is performed based on the memory address of the display data memory unit 110 specified by the display address generation unit 106. Data is read out by the signal generated by the signal generation unit 109 and written to the display data FIFO unit 105. Thereafter, according to the timing signal generated by the LCD display timing signal generation unit 104, the LCD
The data is transferred as display data of panel 120. The LCD display control circuit according to the present invention particularly includes a display control unit (104 to 104).
106) and an LCD display control circuit including a part of the frame buffer (display data memory) access arbitration unit 102.

FIG. 2 is a block diagram of a preferred embodiment of the LCD display control circuit shown in FIG. 1 and described above. Note that, for convenience, the same reference numerals are used for components corresponding to the components of the conventional circuit described above with reference to FIGS. The LCD display control circuit shown in FIG.
Display data read control unit 1, display address generation unit (L
D) 21, display address generation unit (UD) 22, display address selector 6, display data memory unit 3, FIFO control unit (UD) 41, FIFO control unit (LD) 42, display data FIFO unit (UD) 51, display It comprises a data FIFO (LD) 52 and display data selectors 9-13. The display timing signal 7 is transmitted to the FIFO control units 41 and 4
2 is input. The display mode signal 8 is input to the display data read control unit 1, the FIFO control units 41 and 42, and the display data selectors 12 and 13. The display data read control unit 1 receives display data request signals 411 and 421 from the FIFO control unit (UD) 41 and the FIFO control unit (LD) 42, respectively, and receives the display address generation unit (LD) 21 and the display address generation unit ( UD) 22, address generation instruction signals 111 and 113, respectively.
And outputs an address select signal 112 to the display address selector 6.

Based on the description of FIG. 1 described above, FIG.
The operation of the LCD display control circuit shown in FIG. The display mode signal 8 is a signal supplied from the mode register unit 103 (FIG. 1), and is a part of the frame buffer (display data memory) access arbitration unit 102 (FIG. 1). The information is supplied to the control units 41 and 42 and instructs the method of the LCD interface. When a write request to the display data FIFOs 51 and 52 is issued from the FIFO control units 41 and 42, the display data read control unit 1 sends an address generation instruction signal to the display address generation unit (LD) 21 or the display address generation unit (UD) 22. 111 is used to instruct address generation. At the same time, an address select signal 112 is supplied to the display address selector 6 to instruct whether to supply the LD address signal 211 or the UD address signal 221 as the memory address signal 611.

When an address generation instruction is given to the display address generation unit (LD) 21, an LD address signal 211 is supplied to the display data memory unit 3 as a memory address signal 611. Then, the read data is written to the display data FIFO unit (LD) 52 (16 bits × n stages). When the display address generation unit (UD) 22 is instructed to generate an address, the UD address signal 221 is used as the memory address signal 611 in the display data memory unit 3.
Supplied to Then, the read data is written in the display data FIFO (UD) 51 (4 bits × n stages) in units of 16 bits. The FIFO control unit 41 generates the FIFO control signals 412 and 413 and the display data request signal 411 in accordance with the timing of the display timing signal 7. The FIFO control unit 42 similarly generates a display data select signal 424, FIFO control signals 422 and 423, and a display data request signal 421 in accordance with the timing of the display timing signal 7, and outputs the display data signal 131.
1 and 1211 are generated.

The present invention provides a display data FIFO for temporarily holding display data in an LCD display control circuit.
The structure of the FIFOs 51 and 52 has been changed.
By providing the data selectors 9 to 13 at the output portions of 1 and 52, a plurality of types (4-bit single scan, 8
It is characterized by providing an LCD display circuit compatible with a bit dual scan or 8-bit single scan) interface system.

According to the LCD display control circuit of the present invention shown in FIG. 2, the conventional 4-bit single scan configuration shown in FIG. 10, the conventional 8-bit single scan configuration shown in FIG. A display mode signal 8 and display data selectors 9 to 13 are provided for the 8-bit dual scan configuration.
Data signals 521 to 524 which are internal signals of IFO 52
Is available. This makes it possible to form an equivalent circuit with each of the conventional configurations shown in FIGS. 10 to 12 according to the instruction of the display mode signal 8. Therefore, a plurality of types (4-bit single scan,
LCD display of 8-bit dual scan and 8-bit single scan) can be performed.

Next, the operation in each mode will be described with reference to FIG. (1) In the case of 4-bit single scan type LCD In the case of this scan display type, the display address generation is performed only by the display address generation unit (LD) 21 and the display data FIFO is generated only by the display data FIFO (LD) 52. use. The display data is stored in a display address generation unit (LD) 21.
Is read out from the display data memory unit 3 in accordance with the address generated in the step S3, and the display data FIFO is read in accordance with the write pointer signal 422 generated in the FIFO control unit (LD) 42.
O (LD) 52 is written. This display data FIF
The data written in the O (LD) 52 is divided into four bits, and the display data signals 521, 522,
23 and 524 are supplied to the display data selector 9. At this time, the display data signals 521, 522, and 5 are generated by the read pointer signal 423 and the display data select signal 424 generated by the FIFO control unit (LD) 42.
Either one of 23 and 524 is set as the display data signal 911.
At this time, the display mode signal 8 is supplied to the display data selector 12 so as to select the display data signal 911, and the display data signal 911 is supplied to the display data signal 1211.
11 is supplied, and a circuit operation corresponding to FIG.

FIG. 3 shows a timing chart in the above case. In FIG. 3, (a) is a reference clock signal,
(B) is a memory clock signal, (c) is a display address signal 211 from the display address generation unit (LD), (d) is display data 311 from the display data memory unit 3, (e).
Is a FIFO control signal (write pointer) 422 from the FIFO control unit 42, (f) is a FIFO control signal (read pointer) 423 from the FIFO control unit 42,
(G) is a display timing signal 7, (h) is a display data request signal 421 from the FIFO control unit 42, (i) is a display synchronization clock signal, and (j) is a display data selector 1.
2 is a display data signal 911 output from the display device 2. Here, the display timing signal 7 is a 2-bit signal,
The following states are shown, respectively. "00": Display disabled / display data read disabled "01": Display disabled / display data read enabled "11": Display enabled / display data read enabled

The display timing signal 7 is initially "00", and both the reading of the display data and the display operation are in the "non-permitted" state. At this time, the display data request signal 421 is in an invalid state, and becomes effective when the display timing signal 7 becomes “01”. As a result, the address generation instruction signal 111 is generated from the display data read control unit 1, and the address generation instruction signal 111 is synchronized with the memory clock signal.
A D address signal 211 is generated. At this time, the address select signal 1 supplied to the display address selector 6
12 is fixed so as to select the LD address signal 211, and the memory address signal 611 becomes the LD address signal 211.

The display data memory section 3 outputs display data 311 according to a memory address signal 611. This data is stored in a FIFO control signal (write pointer) 42
Written to the FIFO location indicated by 2. Here, the bit width of the memory data is 16 bits and the
The number of O stages is represented by eight stages. When the FIFO becomes full, the display data request signal 421 becomes invalid and the FIFO
Writing of display data to O is stopped. When the display timing signal 7 becomes “11”, the display is set to the “display permitted” state, and the FIFO control unit 42 reads out the FIFO control signal (read pointer) 423 and the display data select signal 42.
4 is generated. In this example, while the FIFO control signal 423 counts one, the display data select signal 424 is controlled to count four. Thereby, the display data signals 521, 522, 523, 52
4 are assigned to the display data signal 911 in order. Also,
At this time, the display data selector 12 is fixed to select the display data signal 911 according to the supplied display mode signal 8. FIG. 6 shows an LCD display image at this time.

(2) L of 8-bit single scan system
In the case of the CD, also in the case of this scan method, the display address is generated only by the display address generation unit (LD) 21 and the display data FIFO.
O uses only the display data FIFO (LD) 52, and the basic operation is the same as the above-described (1) 4-bit single scan method. The difference is that the display data selectors 10 and 11 are enabled in place of the display data selector 9 enabled in the above-described 4-bit single scan method, and the selection data of the display data selector 12 is changed to the display data signal 1011. Is to choose. Further, the display data selector 13 which has been invalidated in the 4-bit single scan method becomes valid, and the display data signal 1111 is selected. This results in a circuit operation corresponding to FIG.

FIG. 4 shows a timing chart of this scanning method. FIGS. 4A to 4I show FIGS.
Same as (i). 4 (j) and (k) show the display data signal 1011 (1211) and the display data selector 11 from the display data selectors 10 and 12, respectively.
And 13 are display data signals 1111 (1311). The display timing signal 7 is a 2-bit signal,
The following states are shown. "00": Display disabled / display data read disabled "01": Display disabled / display data read enabled "11": Display enabled / display data read enabled The display timing signal 7 is initially "00". ,
Both the reading of the display data and the display operation are in the “non-permitted” state. At this time, the display data request signal 421
Is in an invalid state, and the display timing signal 7 is “0”.
It becomes effective when it becomes "1". As a result, an address generation instruction signal 111 is generated from the display data read control unit 1, and the LD address signal 2 is synchronized with the memory clock signal.
11 is generated. At this time, the display address selector 6
Is fixed so as to select the LD address signal 211, and the memory address signal 611 becomes the LD address signal 211.

The display data memory section 3 outputs the display data 311 according to the memory address signal 611. This display data 311 is written to the FIFO position indicated by the FIFO control signal (write pointer) 422. Here, the bit width of the memory data is 16 bits, and the number of FIFO stages is expressed by eight stages. Note that F
When the IFO is full, the display data request signal 421 becomes invalid, and the writing of the display data to the FIFO stops.

When the display timing signal 7 becomes "11", the display is set to the "display permitted" state, and the FIFO control unit 42 generates a FIFO control signal (read pointer) 423 and a display data select signal 424. In this example, while the signal 423 counts one, the signal 424
Is controlled to count 2. Therefore, the display data selector 10 sets the display data signals 521 and 5
23 are alternately assigned to the display data signal 1011, and the display data selector 11 alternately assigns 522 and 524 to the display data signal 1111. At this time, the display data selector 12 is fixed to select the display data signal 1011 according to the supplied display mode signal 8, and the display data selector 13 is similarly fixed to select the display data signal 1111. FIG. 7 shows an LCD display image at this time.

(3) L of 8-bit dual scan system
In the case of a CD In the case of this scanning method, the display address generation is performed by the display address generation unit (LD) 21 and the display address generation unit.
(UD) 22 and the display data FIFO is the display data F
IFO (LD) 52, display data FIFO (UD) 51
Use The display data written in the display data FIFO (LD) 52 is divided every four bits and supplied to the display data selector 9 as display data signals 521, 522, 523, and 524, respectively. The display data similarly written in the display data FIFO (UD) 51 is used as the display data signal 511 by the display data selector 1.
3 is supplied. Here, when writing display data from the display data memory unit 3 to the display data FIFO (UD) 51, it is assumed that 16 bits, that is, data of four FIFO stages are written simultaneously. At this time, one of the display data signals 521, 522, 523, and 524 is set as the display data signal 911 according to the FIFO control signal (read pointer) 423 and the display data select signal 424 generated by the FIFO control unit 42. At this time, the display mode signal 8 is supplied to the display data selector 12 so as to select the display data signal 911, and the display data signal 911 is supplied to the display data signal 1211. Similarly, the FIFO generated by the FIFO control unit 41
The data of the display data signal 511 is selected by the control signal (read pointer) 413. As a result, a circuit operation corresponding to FIG.

FIGS. 5A to 5O are timing charts in the case of the above-mentioned scanning method (3). The display timing signal 7 is a 2-bit signal and indicates the following state. "00": Display disabled / display data read disabled "01": Display disabled / display data read enabled "11": Display enabled / display data read enabled The display timing signal 7 is initially "00". ,
Both the reading of the display data and the display operation are in the “non-permitted” state. At this time, the display data request signal 42
1 and 411 are in an invalid state, and become effective when the display timing signal 7 becomes “01”. by this,
Address generation instruction signal 1 from display data read control unit 1
11 is generated, and the LD address signal 211 is generated in synchronization with the memory clock. At this time, the address select signal 112 supplied to the display address selector 6 is
The LD address signal 211 is fixed so as to be selected, and the memory address signal 611 becomes the LD address signal 211.

Thereafter, when the FIFO control unit (UD) 41 becomes full and the display data request signal 421 becomes invalid,
Address generation instruction signal 1 from display data read control unit 1
13 is generated, and the UD address signal 221 is generated in synchronization with the memory clock. At this time, the address select signal 112 supplied to the display address selector 6 is
It changes to select the UD address signal 221. Then, the memory address signal 611 becomes the UD address signal 221. Thereafter, when the FIFO control unit (UD) 41 becomes full, the display data request signal 411 becomes invalid, and the writing of display data to the FIFO stops.

The display data memory 3 outputs the display data 311 according to the memory address signal 611. The display data 311 is written to the FIFO position indicated by the FIFO control signals (write pointers) 422 and 412. Here, the bit width of the memory data is
The display data FIFO (LD) 52 has 16 stages and the display data FIFO (UD) 51 has 8 stages.
Expressed in 32 steps. In addition, the display data FIFO (U
D) It is assumed that writing to 51 is performed simultaneously by four stages.

When the display timing signal 7 becomes "11", the display is set to the "display permitted" state, and the FIFO control unit 42 generates a FIFO control signal (read pointer) 423 and a display data select signal 424. In this example, while the signal 423 counts one, the signal 424
Is controlled to count four. This allows
The display data signals 521, 522, 523, and 524 are sequentially assigned to the display data signals 911. The display data selector 12 is fixed so as to select the display data signal 911 according to the supplied display mode signal 8. Similarly, the FIFO control unit 41
A control signal (read pointer) 413 is generated. At this time, the display data selector 13 is fixed so as to select the display data signal 511 according to the supplied display mode signal 8.

FIG. 8 shows an LCD display image at this time. In this embodiment, 4 bits and 8 bits
As for the correspondence to bits, it is possible to deal with n bits and 2n bits by devising the bit configuration of each FIFO.

FIG. 9 is a block diagram showing the configuration of another embodiment of the LCD display control circuit according to the present invention. FIG.
Is a portion surrounded by a broken line in FIG. 2, that is, a circuit corresponding to an 8-bit single scan interface,
Two more circuits are added for the display data memory, and the color L
It is compatible with CD panels. Where color LC
It is assumed that the interface of the D panel has an interface signal of 6 bits for each of R, G, and B colors. In the case of the conventional operation, the display data memory unit 31 and the 8-bit single scan circuit 141 are used, and a plurality of types of interfaces (4 bit single scan, 8 bit (Dual scan and 8-bit single scan)
Corresponding to the interface method.

In the case of the color mode, the control of the 8-bit single scan of the conventional operation is used, and the display data memory sections 31, 32, 33 and the 8-bit single scan circuits 141, 142, 143 are B, R, G. To correspond to. The interface unit with the LCD has 6 bits out of BLD3-0 and BUD3-0, and similarly RLD3-0.
And RUD3-0, and 6 bits among GLD3-0 and GUD3-0.

The configuration and operation of the preferred embodiment of the LCD display control circuit according to the present invention have been described above in detail. However, it should be noted that such an embodiment is merely an example of the present invention and does not limit the present invention in any way.

[0036]

As is clear from the above description, according to the LCD display control circuit of the present invention, it is possible to cope with a plurality of types (4 bit single scan, 8 bit dual scan or 8 bit single scan) of the interface system. It is. The reason is that the configuration of the display data FIFO for temporarily holding the display data in the LCD display control circuit has been changed, and that the data output selector has a data selector. Therefore, various L
A practically remarkable effect of being able to flexibly respond to a CD is obtained.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an LCD display control circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a preferred embodiment of an LCD display control circuit according to the present invention.

FIG. 3 is a 4-bit single scan operation timing chart of the embodiment.

FIG. 4 is an 8-bit single scan operation timing chart of the embodiment.

FIG. 5 is an 8-bit dual scan operation timing chart according to the embodiment.

FIG. 6 is a view showing a display image of a 4-bit single scan LCD according to the embodiment.

FIG. 7 is a display image diagram of an 8-bit single scan LCD according to the embodiment.

FIG. 8 is a display image diagram of an 8-bit dual scan LCD according to the embodiment.

FIG. 9 is a block diagram showing the configuration of another embodiment of the LCD display control circuit according to the present invention.

FIG. 10 shows a conventional 4-bit single scan LC.
It is a block diagram of a D display control circuit.

FIG. 11 shows a conventional 8-bit single scan type LC.
It is a block diagram of a D display control circuit.

FIG. 12 shows a conventional 8-bit dual scan LC.
It is a block diagram of a D display control circuit.

[Explanation of symbols]

 Reference Signs List 1 display data read control unit 3 display data memory unit 6 display address selector 7 display timing signal 8 display mode signal 9 to 13 display data selector 21 display address generation unit (LD) 22 display address generation unit (UD) 41 FIFO control unit ( UD) 42 FIFO control unit (LD) 51 display data FIFO (UD) 52 display data FIFO (LD) 111, 113 address generation instruction signal 112 address select signal 211, 221 display address signal 311 display data 411, 421 display data request signal 511 display data signal 521 to 524 display data signal 611 display address signal

Claims (3)

[Claims] 1. A FIFO to which a display timing signal is input.
A control unit, a display data read control unit to which a display data request signal from the FIFO control unit is input, and a pair of display address generation units to which an address generation instruction signal from the display data read control unit is input; A display address selector for selecting a display address signal from the display address generation unit by an address select signal from the display data read control unit; a display data memory unit to which a display address signal from the display address selector is input; A display data FIFO for receiving display data from the display data memory unit and temporarily storing the display data;
In an LCD display control circuit for controlling display of a panel, a display data selector is provided at a subsequent stage of the display data FIFO, and the display data selector is controlled based on a display mode signal, whereby a plurality of types of LCD interface methods of the LCD panel are provided. An LCD display control circuit characterized in that the LCD display control circuit can be adapted to the following. 2. The display data FIFO according to claim 1, wherein:
An IFO (UD) and a display data FIFO (LD). The display data FIFO (LD) divides the written data into four bits, and outputs four display data signals to the display data selector. The LCD display control circuit according to claim 1, wherein: 3. The LCD display control circuit according to claim 1, wherein the LCD panel can be selected from an interface system of 4-bit single scan, 8-bit dual scan, and 8-bit single scan.