JP2002042122A - Image processing device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide an image processing apparatus having both hardware features of high-speed processing and software features of easily responding to changes in processing content. In each module of an image processing apparatus, a circuit element constituting the module is mounted on a single board, and the board of each module has the same dimensions, and is mounted on a cross-point switch serving as a motherboard. The connector is detachable from the cross point switch by connecting and disconnecting a plurality of connectors provided in the switch. The pre-processing module 26 _{1 and the} like further include a plurality of sub-processing blocks. However, no matter what path data passes through which sub-processing module, the module delay time is set to be constant for each pre-processing module. I have. This facilitates calculation of the processing time and the like even when the entire image processing content is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which is useful for performing product inspection using an image processing technique.

[0002]

2. Description of the Related Art When performing a defect inspection of a product, an image processing technique is sometimes used. The image processing device adopts a method of processing image data obtained from an imaging device such as a camera using a computer as a method of processing the image data in a form suitable for defect detection,
There is a method in which processing is performed by hardware using an electronic circuit or the like.

[0003]

The conventional image processing apparatus for defect inspection, which uses a hardware method, has the advantage that the processing can be performed at high speed, but the processing contents are changed. However, even if it could not be done, or if it could be changed, its range had to be rather limited. For this reason,
It has been difficult to flexibly respond to changes in inspection contents or changes in products to be inspected.

On the other hand, in the case of using a software method, it is easy to change the processing content, so that even if the product to be inspected changes, it can be easily dealt with only by changing the program. There is. However, on the other hand, in terms of processing speed, although the speed of CPUs and the like has been increased as in recent years, in the field of image processing with a large amount of data, it still does not reach the processing by hardware, and If a high-speed inspection is to be performed on the above-mentioned product, there is a problem that the contents that can be inspected are limited in terms of processing speed.

The present invention has been made based on such a technical background. That is, an object of the present invention is to provide an image processing apparatus having both a hardware feature of high-speed processing and a software feature of easily coping with a change in processing content.

[0006]

According to an aspect of the present invention, there is provided an image processing apparatus comprising: a plurality of processing modules which operate independently and perform processing on image data by hardware; Provided, each processing module includes one or two or more sub-processing blocks and, if necessary, a delay block, and can select a passing path to pass through which sub-processing block or delay block. By setting a combination of processing modules necessary for overall image processing and a passing order of image data from among the plurality of processing modules, and selecting a passing path of image data in each processing module, The data processing to be performed on the data is determined, and one or more processing blocks or delay blocks through which the image data passes. The processing content of the input image data can be changed depending on the process, but no matter what path the image data passes, the module delay time from when the image data is input to one processing module until it is output is It is characterized in that it has processing time control means which is made constant and adjusts the entire processing time based on the module delay time of each processing module.

According to a second aspect of the present invention, in the image processing apparatus of the first aspect, the plurality of processing modules have the same size and are detachably attached to a common motherboard. And

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, a combination of necessary processing modules among the plurality of processing modules and a setting of a passing order of image data, and each processing are performed. The selection of the passage of the image data in the module is performed by an external host.

According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, each of the processing modules holds its own module delay time in hardware, and receives an inquiry about the module delay time from the host. In this case, the value of the held module delay time is notified to the host.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically illustrating a configuration of an image processing apparatus 10 according to the present embodiment.

As shown in FIG. 1, an image processing apparatus 10 of this embodiment includes an input module 21, an output module 22, measuring modules 23 ₁ ,..., 23 _m , a control module 24, A memory module 25 and preprocessing modules 26 ₁ ,..., 26 _n are provided. The measuring modules 23 ₁ ,..., 23 _m and the control module 24 are connected by a local bus 38-1.
-2 is connected to the PCI bus 37.

In each of the blocks shown in FIG. 1, a central part of the image processing is performed by the preprocessing module 26 ₁ ,
.., 26 _n . Note that the name “pre-processing module” is intended for product inspection by the image processing apparatus of the present embodiment, and finally the measurement modules 23 ₁ ,.
This means that the process is performed before the final process of determining the presence or absence of a product defect based on the measurement result at 3 _m .

A camera 30 for picking up an image of a product to be inspected outputs an image signal as an analog signal. This analog image signal is supplied to the input module 21 by A
/ D converted to digital image data. At this time, the synchronization signal included in the analog signal is separated. As the input module 21, a module that matches the specifications of the image signal output from the camera is used. A plurality of types of cameras 30 that can be used are prepared, and when these are used properly, input modules 21 corresponding to each type are prepared, and an input module corresponding to the type of camera to be used is mounted. When a digital camera is used as the camera 30, A / D conversion in the input module is naturally unnecessary.

The digitized image data is temporarily stored in the memory module 25. When performing image processing by software, there is no concept of signal synchronization, but when performing image processing by hardware, a synchronization signal is still necessary. In the conventional hardware processing in which each processing is not modularized, after a synchronization signal is separated at a portion corresponding to the input module 21, this is handled in a completely different system from the data processing. A synchronization signal is generated in a portion corresponding to
When performing the / A conversion, it is added to the image data.

On the other hand, in the present embodiment, the synchronization signal is separated in the input module 21 and only the pure image data is stored in the memory module 25. When sending this image data to each pre-processing module, a digital synchronization signal is added, and as shown in FIG. Perform only processing.

Each module of the image processing apparatus 10 shown in FIG. 1 is one in which circuit elements constituting the module are mounted on one substrate, and the substrate of each module has the same dimensions and becomes a motherboard. By connecting and disconnecting a plurality of connectors provided on the cross point switch 20, the connector can be attached to and detached from the cross point switch. Therefore, the apparatus can be easily improved or modified by, for example, improving the circuit configuration of a certain preprocessing module, or adding a preprocessing module substrate that performs completely new processing.

As shown in FIG. 2, the cross point switch 20 switches the connection state between each module on the input point side and each module on the output point side. The switching of the connection state by the cross point switch 20 is performed under the control of the control module 24 shown in FIG. The host 39 shown in FIG. 1 instructs the control module which module is to be connected to which module based on the running program. The control module 24 receives this information, interprets the content, and issues an instruction to the cross point switch 20. Note that a personal computer or the like can be used as the host 39.

An image finally obtained greatly differs depending on what kind of processing is performed on image data and in what order. For this reason, according to the contents to be inspected, what processing is performed and in what order are determined in advance, and the control module 24 performs the processing between the modules so that the data passes through each module according to the order. Control the exchange of data.

Each pre-processing module 26 ₁ ,..., 26 _n
The respective image processings are executed by hardware. There is no particular limitation on how fine the unit processing performed by one preprocessing module is. However, in general, for example, when performing one large process of extracting only a defective portion generated in a product in the entire image processing apparatus, one significant process that constitutes the process, for example, a binarization process In general, each processing such as filter processing, thinning processing, noise removal processing, dilation / contraction processing, and the like is treated as one processing unit, and one preprocessing module is assigned to each processing unit. In such a case, one preprocessing module includes one or more circuit blocks (hereinafter, referred to as “sub processing blocks”) for performing even smaller processing.

FIG. 3 is a block diagram showing a circuit configuration of one preprocessing module 26. Input image data is
The image data is input in units of one pixel, processed one pixel at a time, and sent to the next module as output image data. Note that some processes require other pixel data of the same image when processing data of a certain pixel.
In that case, the pixel data is temporarily stored until the necessary image data is input in the preprocessing module, but even in such a case, the data input and output are
This is performed in units of one pixel.

As shown in FIG. 3, the image data input to a certain pre-processing module 26
At 0, the synchronization signal added at the beginning is separated. As described above, when the analog image signal sent from the camera 30 is A / D-converted in the input module 21 and the digital data is temporarily stored in the memory module 25, as described above, This is added to the image data by the memory module 25. The pure image data from which the synchronization signal has been separated is subjected to predetermined data processing in the data processing unit 41. On the other hand, the separated synchronizing signal is delayed by a predetermined time in the delay circuit 42, and then, after being synthesized with the processed image data in the synchronizing signal synthesizing circuit 43, is output as output data of this preprocessing module. You.

By the way, even with the same one preprocessing,
The details of processing vary slightly depending on the type of data and the content of the inspection. In order to cope with such a situation, the data processing unit 41 of one pre-processing module is provided with a plurality of sub-processing blocks constituting the pre-processing. FIG. 4A shows that a plurality of sub-processing blocks A, B, C,
D shows a case where D is prepared. As shown in FIG. 4 (b), depending on the path through which the data is passed between the plurality of sub-processing blocks, even if the pre-processing is the same one filter processing, the processing content is somewhat different. different.

In one pre-processing module, possible processing paths for all the sub-processing modules provided therein are prepared in advance, and which processing path is used to process data is shown in FIG. Instructed by the host 39 shown in FIG. In each of these processing paths, when the processing path is designated, the time required from when the image data is input to this preprocessing module to when it is output (hereinafter referred to as “module delay time”) is always set. A predetermined delay value is automatically set for each route so as to be constant. This delay value is set using a delay (delay) block 50 shown in FIG.

As a result, on the host 39 side, the host 3
9 needs to know only the module delay time of each preprocessing module when calculating the time of the entire image processing, the delay time in a sub-processing block lower than the preprocessing module, and the It is not necessary to adjust the delay time in consideration of the data transit time. Therefore, the host 39 can respond quickly even when the inspection target changes and the content of the image processing changes.

For example, it is assumed that the route passing through the process A, the process B, the process C, and the process D shown in FIG. In this case, using the delay block 50, the module delay is set so that the time required for data to pass through each path is equal to the time required for passing data through the paths A, B, C, and D. Adjust the time.
As a result, as shown in FIG. 4B, if the same pre-processing module is used, the module delay time becomes the same regardless of the path inside the module. Each preprocessing module 26 holds its own module delay time data in its internal module delay time holding circuit 44 so that such a module delay time can be answered when an inquiry is made from the host.

Further, among the plurality of preprocessing modules, there is provided a module which merely performs data delay without performing substantial image processing. That is, even if data passes through such a pre-processing module, the contents of the data do not change at all before and after the input, and simply have a fixed module delay time between the input and the output of the data. It just takes. This delay module has a structure in which a delay time can be arbitrarily set. The module delay time is set by the host 39, and the set value is held in hardware in the preprocessing module.

In this way, even when a certain preprocessing module is removed and another preprocessing module is mounted, the host 39 can immediately know the module delay time by inquiring of a new preprocessing module. Can be.

As described above, by making the module delay time constant for each pre-processing module regardless of the path through which the data passes, data processing is performed simultaneously on a plurality of paths, and In the case where further processing is performed using the data for which processing has been completed, the calculation of the entire processing time becomes easy, and the time required for this calculation can be significantly reduced as compared with the conventional method. . By keeping the module delay time constant for each preprocessing module as described above, it is possible to perform so-called pipeline processing. This can also greatly reduce the overall time required for image processing.

Conventionally, in the case of an image processing apparatus based on software, it was difficult to perform a defect inspection in real time in the first place. However, originally, when a product is inspected on a production line and an abnormality is found, There is also a demand that, in conjunction with the function of removing a product from a line, if a defective product is found, the product should be immediately removed from the line.

On the other hand, in the case of a hardware-based image processing apparatus, it is possible to perform real-time inspection with a conventional apparatus. In the case where the type of flowing product changes, in a conventional hardware-based image processing apparatus, if the content of the processing is changed according to the product, fine processing equivalent to the sub-processing module of the present embodiment is thereby performed. It is necessary to change the processing content,
It takes a lot of time to calculate the delay time of each detailed process and calculate the entire processing time by software based on those. Therefore, when the product to be inspected is changed, the production line must be temporarily stopped for this calculation.

On the other hand, in the case of the image processing apparatus according to the present embodiment, since it is based on hardware, it is possible to perform real-time inspection, and furthermore, to perform binarization processing,
Image processing with a certain unity such as filter processing, thinning processing, noise removal processing, dilation / compression processing, etc. is considered as one module, and even if the finer processing lower than it changes, that is, the data in one module Since the module delay time of one module is always constant even if the route that passes through changes, it becomes easy to calculate the processing time of the entire image processing. Is shortened to As a result, even if a product to be inspected flowing through the line changes, the inspection does not need to be interrupted immediately without stopping the production line each time.

As an example, when the type of the product flowing on the manufacturing line changes and the content of the image processing is changed accordingly, the host 39 determines which pre-processing module based on the changed processing content. The order and timing of use are determined, and the path of the sub-processing module constituting each pre-processing module is determined. At that time, from the module delay time of each preprocessing module,
The order and timing of flowing data to each preprocessing module to be used are calculated. If this calculation takes a long time, the line must be stopped during that time. However, as described above, if the time required for this calculation is significantly reduced, for example, if a current personal computer is used as the host 39, even if the type of product flowing on the production line changes suddenly, Necessary calculations can be performed in real time without stopping the line, and the content of image processing can be changed immediately.

The data for which the image processing in the pre-processing module has been completed is subjected to a predetermined measurement process in any of the measurement modules 23 ₁ ,..., 23 _m . The data obtained by this measurement processing is stored in the local bus 38-1 and P
CI (Peripheral Component Interconnect) bus 37
Is sent to the host 39 via.

At each stage of processing in each module, an image is output to the monitor 35 via the output module 22 when necessary. As a result, not only the final image data, but also at each stage during the processing,
It is possible to visually confirm the contents of the image data.

FIG. 5 is a flowchart showing a processing procedure when image processing for detecting a defect is performed on image data obtained from a camera using a plurality of preprocessing modules. FIG. 6 is a diagram schematically showing an example of image data at each processing stage when image processing for defect detection is performed.

Referring to FIG. 5, the procedure for performing image processing will be described. First, it is assumed that the original image data is stored in the memory module 25 of FIG. 1 (S10). First, image data is read from the memory module 25, and filtering is performed in a preprocessing module that performs a filtering process (S11). Next, the data that has been filtered by the pre-processing module that performs the binarization processing is binarized (S12). FIG. 6 (a)
This shows a binarized image. A portion surrounded by a dotted line circle in the center of this drawing represents a small projection-like defect generated in this product. This binary image data is divided into two paths, and in one path, the data is expanded and
After passing through the pre-processing module for performing the contraction processing (S1
3) On the other path, the data passes through a pre-processing module only for delay (S14). In the preprocessing module for this delay, the same module delay time as in the expansion / contraction processing is set. The portion corresponding to the small defect as shown in the dotted circle in FIG.
As is well known, by continuously performing the contraction processing and the expansion processing, the image disappears from the image as shown in FIG. 6B, and the image becomes a state close to the original shape of the product.

When an operation for obtaining a difference is performed between the image data subjected to the expansion / contraction processing and the image data simply delayed (S15), as shown in FIG. Only the image corresponding to the projection-like defect having a small size remains. Then, after performing a masking process (S16) based on the image and the delayed image data from the memory module 25 (S18), the measurement module extracts a feature amount (S1).
7) It is possible to specify the position, size, shape, and the like of the projecting defect.

The operation of the image processing apparatus 10 is as follows. First, the operator displays on the GUI screen of the host 39,
Specify what processing to perform. Then, host 3
9 sends this information to the control module 24. The control module 24 transmits switching data to the cross point switch 20 based on the information received from the host 39, and switches the connection state of the preprocessing module as needed. Further, settings are made as to what path data is passed through the sub-processing block inside each pre-processing module. Then, at the actual inspection stage, the inspection is executed based on this setting. As described above, the fact that the procedure that the operator has to perform is very simple is also a feature of the image processing apparatus according to the present embodiment.

Although the present invention has been described above, the present invention is not limited to the above embodiments, and various changes may be made within the scope of the invention described in each claim. It is possible and included in the technical scope of the present invention.

For example, the configuration in which one module corresponds to one substrate as in the above embodiment is merely one example of the present invention, and other than this, for example, each module may be integrated into one semiconductor chip. A plurality of module chips that may be integrated and used are mounted on one substrate, and the connection state of each module chip is electrically switched by a crosspoint switch. include. Further, in addition to integrating one module on one semiconductor chip, a plurality of modules including a cross point switch circuit may be integrated on one semiconductor chip. With such a configuration using a semiconductor chip, the overall size of the device can be further reduced.

In the above embodiment, each preprocessing module has a constant module processing time irrespective of the internal processing path. However, the module processing time is different for each preprocessing module. It had been. The technical processing of the present invention is also applicable to a case where the module processing time in each preprocessing module is made constant for all the preprocessing modules, for example, to make it easier to calculate the processing time of the entire image processing in the host. Included in the range.

[0042]

As described above, according to the present invention,
Since the entire processing is performed by hardware, quick processing is possible. In addition, for a plurality of processing modules that operate independently and perform hardware processing on image data, overall image processing is performed. By setting the combination of the processing modules required for the above and the passing order of the image data, it is possible to easily change the entire contents of the image processing, although it is a hardware processing.
In particular, since the processing modules have the same dimensions and are detachably attached to a common motherboard, it is easier to change the content of the entire image processing.

Each processing module includes one or two or more sub-processing blocks and, if necessary, a delay block, and allows selection of a passing path through which sub-processing block or delay block. The processing content of the input image data can be changed by one or more processing blocks or delay blocks through which the image data passes. By making the module delay time from the input of image data to the output of the image data constant, the calculation and adjustment of the entire processing time becomes easy and quick, and as a result, the products to be inspected and searched through the line Even if is changed, the inspection can be continued without stopping the production line each time.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of an image processing apparatus 10 according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating switching of a connection state between modules by a cross point switch 20;

FIG. 3 is a block diagram showing a circuit configuration of one preprocessing module 26;

FIG. 4 is a diagram schematically showing a state in which a plurality of sub-processing blocks A, B, C, and D are prepared in one pre-processing module.

FIG. 5 is a flowchart illustrating an example of a processing procedure when performing image processing for defect detection on image data obtained from a camera using a plurality of preprocessing modules.

FIG. 6 is a diagram schematically illustrating an example of image data at each processing stage when image processing for defect detection is performed.

[Explanation of symbols]

10 image processing device 20 cross point switch
21 input module 22 output module 23 ₁ ,... 23 _m measurement module 24 control module 25 memory module 26 ₁ ,... 26 _n pre-processing module 30 camera 35 monitor 37 bus PCI bus 39 host 4
0 synchronization signal separation circuit 41 data processing unit 42 delay circuit 43 synchronization signal synthesis circuit 44 module delay time holding circuit 50 delay (delay) block

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G051 AA90 AB02 CA03 CA04 CA07 DA13 EA04 EA11 EA12 EA14 EA23 EC05 ED01 ED07 ED14 ED23 FA10 5B047 AA11 EB03 5B057 AA01 CE12 CH03 CH09 CH18 DA03 DB02 DC32

Claims (4)

[Claims] A plurality of processing modules that operate independently and perform processing on image data in a hardware manner are provided. Each processing module includes one or more sub-processing blocks and, if necessary, A delay block is included, and it is possible to select a passage path to pass through which sub-processing block or delay block, and a combination of a processing module and an image required for overall image processing from among the plurality of processing modules. By setting the data passing order and selecting the image data passing path in each processing module, the content of data processing to be performed on the image data is determined. The processing contents for input image data can be changed by the above processing blocks or delay blocks. Regardless of the route of data, the module delay time from when image data is input to one processing module to when it is output is made constant, and based on the module delay time of each processing module. An image processing apparatus comprising processing time control means for adjusting the entire processing time. 2. The image processing apparatus according to claim 1, wherein the plurality of processing modules have the same size and are detachably attached to a common motherboard. 3. An external host performs a combination of necessary processing modules from among the plurality of processing modules, sets a passing order of image data, and selects a passing path of image data in each processing module. The image processing apparatus according to claim 1, wherein: 4. Each of the processing modules holds its own module delay time in hardware, and when an inquiry about the module delay time is received from the host, the value of the held module delay time is stored in the host module. The image processing apparatus according to claim 3, wherein the notification is sent to the image processing apparatus.