JP2002043385A - Semiconductor wafer having test pattern, semiconductor wafer inspection method, manufacturing process management method, and semiconductor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test pattern with which a circuit pattern can be inspected for defects with high sensitivity in a semiconductor manufacturing process, a method for detecting defect, and a method for managing manufacturing process both of which use the test pattern. SOLUTION: The variation of the misalignment amounts of an interlayer pattern is monitored from the occurring amounts of defects in the misalignment amounts of a plurality of test patterns having different misalignment amounts. Alternatively, defects such as short circuits, continuity defects, short circuits caused by foreign matters, etc., are detected by forming test patterns having different circuit patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer having a test pattern, a method for inspecting a wafer, a method for managing a manufacturing process, and a method for manufacturing a semiconductor, and more particularly to a method for managing an abnormality in a manufacturing process in a semiconductor manufacturing line. It is suitable for.

[0002]

2. Description of the Related Art In a semiconductor device, a conduction failure of a plug for connecting a circuit between layers, a short circuit or a disconnection of a wiring are fatal defects, and have a great influence on a yield of the semiconductor device. Such defects often occur due to fluctuations in manufacturing conditions, defects in manufacturing equipment, and the like, and often result in a large number of defective products. As a method of preventing the occurrence of such a defect, a wafer for defect detection is periodically flowed to a semiconductor manufacturing line. In particular, as a prior art of a wiring failure detection technique for detecting a short circuit of a wiring pattern, there is IEEE TRANSACTION.
NS ON SEMICONDUCTOR MANUF
The method described in ACTURING, pages 384-389 (1997) is known. Here, a circuit pattern is used in which pads in an electrically floating state (a state not connected to the ground) and test wiring connected to the semiconductor substrate are arranged around the pads. This is a method that utilizes that the pad is connected to the substrate when a short circuit occurs between the pad and the test wiring.

As another method for detecting a short circuit in a wiring, there is a technique described in Japanese Patent Application Laid-Open No. H11-330181. This is a method in which wirings having different electric capacities are alternately arranged, and utilizes the fact that the resistance of the wiring changes due to a short circuit.

In both of the above methods, a defective portion is detected by a change in the amount of charge-up of a pattern due to electron beam irradiation, using an electron microscope or the like.

[0005]

As described above, the conventional test pattern is for detecting a short circuit of a wiring. However, an important defect of a semiconductor manufacturing line is not only a wiring process but also a defective connection of a plug. It is necessary to detect such things.

Further, such a test pattern for detecting a defect is different from a circuit pattern of an actual semiconductor device, and there is a problem that test reliability is low. In particular, in a circuit pattern having multiple layers, alignment between the layers is also an important issue, but it is still not sufficient.

Further, even if a defect is detected by a test pattern, there is a problem that it is difficult to elucidate the cause and a time is required for a countermeasure.

An object of the present invention is to provide a semiconductor wafer provided with a test pattern that can easily detect not only wiring but also plug defects.

Another object of the present invention is to provide a technique capable of quantitatively evaluating such a state of alignment between layers using a circuit pattern for defect detection similar to that of an actual semiconductor device.

It is still another object of the present invention to provide a test pattern for defect detection that can easily estimate the cause from the distribution of detected defects and the like and a technique for analyzing the test pattern.

[0011]

In order to achieve the above object, according to the present invention, a plurality of test patterns having different amounts of misalignment are formed in advance, and the number of defects generated with respect to each amount of misalignment is determined based on the amount of defects. The pattern misalignment is estimated. By monitoring the change in the amount of misalignment and changing the conditions of the exposure apparatus based on the result, the occurrence of defects is prevented in advance.

In addition, a test pattern is formed such that the change in the electrical properties of the circuit pattern due to short-circuiting, disconnection failure, conduction failure, etc. of the wiring and the conduction hole becomes large, thereby improving the inspection sensitivity based on an electron microscope image. Achieve highly reliable inspection.

Hereinafter, the present invention will be described in detail.

In the first invention, a semiconductor wafer has a first circuit pattern formed in a first step and a second circuit pattern formed in a second step on a semiconductor substrate, A test pattern for detecting a defect using the first and second circuit patterns is provided.

[0015] In the second invention, the semiconductor wafer includes the first plurality of circuit patterns formed in the first step and the second circuit pattern formed in the second step on the semiconductor substrate. A test pattern formed by arranging the second circuit pattern between the first circuit pattern and the second circuit pattern, and setting an interval between the first and second circuit patterns to the first circuit pattern. And a plurality of test patterns that are changed between values that are less than or equal to the contact of the second circuit pattern with the second circuit pattern. In this semiconductor wafer, the intervals between the first circuit pattern and the second circuit pattern in the plurality of test patterns are gradually changed.

In the third invention, the semiconductor wafer includes a first plurality of circuit patterns formed in the first step and a second circuit pattern formed in the second step on the semiconductor substrate. A test pattern formed by arranging the second circuit pattern between the first circuit patterns, and setting a distance between the first and second circuit patterns to the first circuit pattern and the second circuit pattern. A plurality of test patterns, which are changed between values not more than the contact of the circuit pattern, are provided at the end of the semiconductor chip.

In the fourth invention, the semiconductor wafer is formed on the semiconductor substrate and the first plurality of circuit patterns is formed on the first circuit pattern so as to be in contact with the first circuit pattern. And the second circuit pattern is shifted with respect to the first pattern within a range where the first circuit pattern and the second circuit pattern are in contact with each other. And a plurality of test patterns arranged in the same manner. Further, the plurality of test patterns are the first test patterns.
The amount of deviation between the second circuit pattern and the second circuit pattern is gradually changed.

In the fifth aspect, the semiconductor wafer is provided with the first circuit pattern formed on the semiconductor substrate and the first circuit pattern formed on the first circuit pattern so as to be in contact with the first circuit pattern. And the second circuit pattern is displaced with respect to the first pattern within a range where the first circuit pattern and the second circuit pattern are in contact with each other. The plurality of test patterns obtained are provided at the end of the semiconductor chip.

In a sixth aspect, a semiconductor wafer is formed on a semiconductor substrate and has a first circuit pattern electrically connected to the semiconductor substrate and a second circuit pattern electrically connected to the semiconductor substrate. And a test pattern in which the value of the connection resistance of the first circuit pattern to the semiconductor substrate and the value of the connection resistance of the second circuit pattern to the semiconductor substrate are different. In this semiconductor wafer, the first circuit pattern is connected to a diffusion layer different from the semiconductor substrate, and the second circuit pattern is directly connected to the semiconductor substrate. Also, the first circuit pattern and the second circuit pattern
Are alternately or alternately arranged. A first wiring pattern disposed on the first circuit pattern so as to be in contact with the first circuit pattern; and a first wiring pattern disposed on the second circuit pattern so as to be in contact with the second circuit pattern. A second wiring pattern is provided, and the first wiring pattern and the second wiring pattern are arranged in parallel with each other and alternately or alternately. At least one of the first wiring pattern and the second wiring pattern is divided in a direction orthogonal to the parallel direction.

In a seventh aspect, a semiconductor wafer is formed on a semiconductor substrate and a first circuit pattern electrically connected to the semiconductor substrate and a second circuit pattern electrically connected to the semiconductor substrate. A test pattern in which the connection resistance of the first circuit pattern to the semiconductor substrate and the connection resistance of the second circuit pattern to the semiconductor substrate are different from each other. It is configured to be arranged in.

In the eighth invention, the semiconductor wafer includes a circuit pattern formed on the semiconductor substrate of the semiconductor chip and electrically connected to the semiconductor substrate directly or through a plug, wiring, or the like. It has the same shape and arrangement as a part of the circuit pattern of the semiconductor chip, and is configured such that the connection resistance with the semiconductor substrate has a test pattern different from the connection resistance of the circuit pattern of the semiconductor chip.

In the semiconductor wafers described in the first to eighth aspects, the test pattern is formed by using the same manufacturing process as the circuit pattern of the semiconductor chip. The test pattern is formed simultaneously with the circuit pattern of the semiconductor chip. The test pattern is formed in the same shape and size as the circuit pattern of the semiconductor chip. Further, the test pattern is formed with a minimum size and a minimum interval among the circuit patterns of the semiconductor chip.

In a ninth aspect, a semiconductor wafer inspection method uses an inspection apparatus for inspecting a circuit pattern using physical properties of an inspection object such as a charged particle beam image, an optical microscope image, and a resistance value of an element. Then, the semiconductor wafer described in any of the above is inspected.

According to a tenth aspect of the present invention, a method for inspecting a semiconductor wafer includes the steps of detecting any one of the physical properties of an inspection object such as an electron microscope image, an optical microscope image, and a resistance value of an element of the semiconductor wafer. To detect the alignment error.

According to an eleventh aspect of the present invention, there is provided the semiconductor wafer inspection method according to any one of the first to fifth aspects, wherein a charged particle beam image, an optical microscope image, an element resistance value, and the like of the semiconductor wafer are inspected. Using physical properties, an alignment error with respect to an already formed pattern is detected.

According to a twelfth aspect, in the semiconductor wafer inspection method according to the sixth aspect, the semiconductor wafer inspection method according to the sixth aspect,
The defect is detected by comparing the physical properties of the second circuit pattern or the second circuit pattern.

According to a thirteenth aspect, the method of managing a manufacturing process is an inspection method using a charged particle beam image or an optical microscope image, wherein the test pattern of the semiconductor wafer described above is formed repeatedly in the wafer. Quantitative evaluation or classification of an image signal at a predetermined position in a chip or a shot is performed, and the quantitative evaluation value, the classification result, or both of the distribution in a wafer and information on a variation between wafers are used for a semiconductor manufacturing process. Manage.

In a fourteenth aspect, a method of managing a manufacturing process includes detecting a defect using a charged particle beam image or an optical microscope image of a semiconductor wafer described in any of the above,
An inspection device having a function of classifying features such as the size, coordinates, signal amount, reference level of the signal amount or the signal amount of a reference image signal amount, the texture, and the like of the defective portion detected in the test pattern of the semiconductor wafer. In addition, the manufacturing process is managed using the information on the distribution within the wafer, the variation between wafers, or the change with time for each feature of the defective portion.

In the fifteenth invention, the method for inspecting a semiconductor wafer is a method of comparing a test result of a semiconductor element such as a yield of a semiconductor product or a probe test and an inspection result of the test pattern by any one of the above-described semiconductor wafer inspection methods. Based on the relationship, the test pattern is changed in sensitivity or the detection result is classified based on the test pattern.

According to a sixteenth aspect, the method of manufacturing a semiconductor chip is a method of manufacturing a semiconductor wafer according to any one of the first to fifth aspects, wherein an electron microscope image, an optical microscope image, a resistance value of an element, or the like of an object to be inspected. An alignment error is detected using any one of the target characteristics, and the operating condition of the manufacturing apparatus is set using the error.

According to a seventeenth aspect, the method of manufacturing a semiconductor chip is a method of manufacturing a semiconductor wafer according to any one of the first to fifth aspects, wherein an electron microscope image, an optical microscope image, a resistance value of an element or the like of a physical object to be inspected. A semiconductor chip is manufactured by detecting an alignment error using any one of the characteristic properties and correcting a position shift of the exposure apparatus of the semiconductor chip using the information of the alignment error.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings using examples.

FIG. 1 shows an example of a circuit pattern of a semiconductor chip to which the present invention is applied. FIG. 1 (a) is a plan view, FIG. 1 (b) is a cross-sectional view, and FIG. It is a top view of the produced circuit pattern. As shown in FIG. 1A, through a wiring process, a wiring pattern 1 is formed on an insulating substrate 30, and a conduction hole 2 is opened in an insulating film 3 between the wiring patterns 1.
The conductive hole 2 is provided with a conductive plug 2a for connection.
FIG. 1A shows a wiring pattern 1, a conduction hole 2, and a conduction plug 2 a embedded in the conduction hole 2.
As shown in (b), the wiring pattern 1 is provided below the insulating film 3 and does not appear on the surface.

In the semiconductor manufacturing apparatus, the circuit pattern is formed by first forming a wiring pattern 1 on a substrate, forming a conductive hole 2 in an insulating film 3 provided on the wiring pattern 1, and inserting a conductive plug in the hole 2. Embedded. As described above, the wiring pattern 1 and the conduction hole 2 are manufactured by different processes. The positional relationship between the patterns manufactured in these two steps is adjusted so as to have a correct value using a pattern for alignment. However, as the pattern rules become stricter, the required accuracy increases, and positioning becomes difficult.

For example, as shown in FIG. 1C, the position of the conductive hole 2 is misaligned with respect to the wiring pattern 1, and if a hole is provided at the position indicated by the conductive hole 4, a positional shift occurs. The conductive plug (not shown) embedded in the conductive hole 4 is short-circuited with the wiring pattern 1.

With reference to FIG. 2, a description will be given of a test pattern which can easily detect the misalignment of the pattern using the inspection apparatus capable of detecting the short circuit.

FIG. 2A is a plan view showing a first embodiment of a test pattern of a semiconductor wafer according to the present invention.
FIG. 2B is a plan view of a semiconductor chip having the test pattern, and FIG. 2C is a characteristic diagram showing the number of short-circuit defects obtained using the test pattern. In FIG. 2C, the horizontal axis indicates the coordinates X in the chip, and the vertical axis indicates the number N of short defects.

In FIG. 2A, reference numerals 7a, 7d, and 7g denote test patterns, and the cross section is configured as shown in FIG. 1B. In the test pattern 7a, a conductive plug 2a is provided at the center between the wiring patterns 1 in the lower layer.
In the test pattern 7d, the conductive plug 2a is arranged with an offset 5 so that the center of the conductive plug 2a is shifted to the right side as viewed in the figure with respect to the center between the circuit patterns 1. In the test pattern 7g, the conductive plug 2a is arranged with an offset 5 so that the center of the conductive plug 2a is shifted leftward from the center between the wiring patterns 1 as viewed in the drawing. These test patterns 7a, 7d, 7g are provided, for example, at the end of a semiconductor chip 6, as shown in FIG. In the test patterns 7a to 7d and 7a to 7g, the offset amount of the center of the conductive plug with respect to the center between the wiring patterns 1 is gradually changed. The semiconductor chip 6 shown in FIG.
As shown in FIG. 2C, when the number of short-circuit defects in the test pattern is plotted with respect to the position X of the test pattern, whether or not the alignment is performed normally and the amount of positional deviation are You can know how much. If the alignment is performed correctly, the number of short-circuit defects is N, as indicated by white circles in FIG.
Is the minimum value at the center (coordinate X in chip is a),
Although the distribution is symmetrical on the left and right, when there is an offset in the relative position between the layers, the point where the number of defects N becomes the minimum as shown by a black circle is shifted. In the embodiment, the coordinates are shifted to the coordinates b. This shift amount is the shift amount itself of the alignment. In this way, by using the test pattern of FIG. 2A for the semiconductor chip 6 shown in FIG. 2B, it is possible to quantitatively evaluate the misalignment between the layers.

By forming the test pattern 7 through the same manufacturing process as an actual semiconductor device, it is possible to always check whether or not the offset amount for alignment is within the margin. Also, as shown in FIG.
If the test pattern 7 is formed on the semiconductor chip 6, it is possible to confirm the state of alignment of the wafer itself during manufacturing. Further, a semiconductor wafer having only the test pattern 7 is separately formed, and the semiconductor wafer is periodically supplied to the production line, so that defects in the production process can be confirmed. By feeding back this data to the manufacturing apparatus, the position of exposure can be changed and alignment can be performed.

Next, a method for evaluating not only the offset of the alignment of the wiring pattern 1 and the conductive plug 2a but also the rotation using the same pattern will be described.

FIG. 3 is a plan view and a characteristic diagram showing a second embodiment of a semiconductor wafer on which a test pattern according to the present invention is arranged. As shown in FIG. 3A, the semiconductor chip 6 has test patterns 7a to 7b shown in FIGS.
g are arranged vertically. FIG. 3A is a characteristic diagram showing the number of short-circuit defects of the test patterns 7a to 7g arranged on the upper portion of the semiconductor chip 6, and FIG. 3C is a diagram showing the test patterns 7a to 7g arranged on the lower portion of the semiconductor chip 6. FIG. 9 is a characteristic diagram showing the number of short defects of 7 g, in which the horizontal axis represents the coordinate X of the test pattern and the vertical axis represents the number N of short defects.
By arranging the test patterns 7a to 7g as shown in FIG. 3B, it is possible to evaluate not only the offset of the pattern alignment between the layers but also the rotation generated between the layers. When the rotation occurs between the layers, as shown in FIGS. 3A and 3C, the locations where the number N of short-circuit defects is minimum at the top and bottom of the semiconductor chip 6 are different. In the present embodiment, as shown in FIG. 3A, in the test pattern on the upper part of the semiconductor chip 6, the number N of short defects at the coordinate e becomes minimum,
FIG. 3C shows a test pattern under the semiconductor chip 6.
As shown in the figure, the number N of short defects at the coordinate b is minimum. If the deviation amount of the minimum position is known, the offset and rotation of the alignment between layers can be easily estimated.

In the embodiments shown in FIGS. 2 and 3, the test patterns 7a to 7g are usually arranged in shot units of the exposure apparatus (the range of chips that can be exposed at one time). Good. Also, in the embodiment of FIG. 3, similarly to the embodiment of FIG. 2, even if a wafer having only a test pattern is used, the offset and rotation of alignment between layers can be easily evaluated.

In the embodiments shown in FIGS. 2 and 3, misalignment is measured by using the number of short defects, but a method using an electron microscope can be considered for detecting the short defects. When observing the pattern to be inspected using an electron microscope,
The brightness of each pattern changes depending on the connection resistance with the substrate and the capacitance of the pattern itself. This is due to a change in the amount of secondary electrons emitted due to a change in the state of charge-up.

If this is used, the capacitance of the conductive plug 2a short-circuited to the wiring pattern 1 becomes large,
The brightness will be different from the other conduction holes. In order to detect the holes having different brightness, an inspection device using an electron microscope image may be used. In this case, wiring pattern 1
Is connected to the substrate through another conductive plug 2a, the difference between the charged state of the short-circuited conductive plug 2a and the charged state of the non-shortened conductive plug is increased, so that a more accurate inspection can be performed.

In this case, if the inspection apparatus has a defect classification function, the accuracy can be further improved by performing an evaluation excluding defects (for example, foreign matters) other than short-circuit defects. In order to determine whether the defect is a short circuit or a high resistance, the conductive plug 2a is previously determined using a wafer of the same product.
What is necessary is just to grasp the relationship between the resistance value of the image and the appearance of the electron microscope image. This may be done by directly measuring the resistance of the conductive plug 2a or by confirming the appearance of the normal part and the defective part when setting the conditions of the manufacturing apparatus (exposure conditions, etching conditions, etc.). .

Hereinafter, how the defect looks under an electron microscope will be described with reference to FIG.

FIG. 4A is a characteristic diagram showing an example of a connection resistance and a signal amount of a conductive plug. FIG. 4B is a plan view showing an example of a test pattern observed by an electron microscope.
(C) is a sectional view of the test pattern showing a defect of the test pattern. As shown in FIG. 4C, the conductive plugs 8a and 9a are manufactured on the conductive plugs 8b and 9b in a separate process.

In FIG. 4A, the horizontal axis represents the connection resistance R, and the vertical axis represents the signal amount R. If the image is bright when the connection resistance is low and dark when the connection resistance is high, FIG.
As shown in (a), as the connection resistance increases, the signal amount decreases. In this case, as shown in FIG. 4 (b), when the shape of the conductive plug is normal but darker than the other, the conductive plug 8 has a poor conduction, and when bright, the plug is short-circuited. When the holes are lined up, a classification such as a short circuit between the lined up holes becomes possible. In FIG. 4B, the poorly connected plug 8 observed darkly has poor conduction at the portion 8c as shown in FIG. 4C, and the two brightly observed plugs 9 correspond to the portion 9
It is connected by c and short-circuited.

As described above, when the appearance of an image by an electron microscope is used, the same evaluation can be performed not on the number of defects but on the brightness of the image itself. The appearance of the defective portion varies depending on the structure of the pattern and the conditions of the electron optical system such as the current of the electron beam to be irradiated and the accelerating voltage. For example, if the short defect looks bright, FIG. c), the vertical axis shown in the graphs of FIGS. 3A and 3C is not the number of short defects, but the same effect can be obtained even if the brightness of the detected image is used. The brightness of the image may be an average value of the entire image acquired in an appropriate field of view, or the position of the hole may be recognized from the image, and the brightness of only the conductive plug pattern may be evaluated. In addition, if the insulating film is a transparent material, the alignment and the rotational displacement can be similarly evaluated by measuring the positional relationship between the wiring and the conductive plug even by an optical method.

In the examples of FIGS. 2 and 3, the pattern alignment is evaluated from the number of occurrences of short-circuit defects in the pattern of the conductive plug 2a and the wiring pattern 1. However, the same pattern is used for the conductive plugs 2a. Can be.

FIG. 5 is a plan view and a sectional view showing a third embodiment of a semiconductor wafer having a test pattern according to the present invention. FIG. 5A is a plan view of a test pattern.
FIG. 5B is a plan view of the semiconductor chip when the test pattern is arranged on the semiconductor chip, and FIG.
FIG. 3 is a cross-sectional view of the test pattern shown in FIG. As shown in FIGS. 5A and 5C, the test pattern 31 has an insulating film 32 provided on a substrate 30, a hole is made in the insulating film 32, and a conductive plug 33b is provided there. Further, an insulating film 34 is provided thereon, a hole is made in the insulating film 34, and a conductive plug 33a is provided. The test pattern 31a is arranged such that the centers of the conductive plugs 33a and 33b are aligned. In the test pattern 31d, each conductive plug 33
The center of a is provided with an offset 5 in the right direction as viewed in the figure. The test pattern 31b is connected to each conductive plug 33b.
With respect to the center passing through, the center of each conductive plug 33a is provided with an offset 5 leftward as viewed in the figure. The test patterns 31 are arranged as shown in FIG.
1a to 31g are arranged so that the offset amount gradually increases.

As shown in FIG. 5, the conduction plugs 33a, 3a
If a pattern in which an offset 5 is given to the relative positions of the 3b is used, the connection resistance is reduced by the offset 5 and a conduction defect is generated. Therefore, instead of the short defect shown in FIGS. It may be used.

As described above, the use of the test patterns shown in FIGS. 2, 3, and 5 makes it possible to evaluate the occurrence of misalignment in the multilayer circuit pattern. By displaying or analyzing the distribution of the misalignment amount of each chip or shot obtained by these methods over the entire wafer, the cause of the misalignment is the alignment of the entire wafer. It is possible to quickly analyze the cause, such as whether the alignment is performed in shot units or not. Thus, by using the test pattern of the present invention,
The misalignment between the multilayer circuits can be detected, and the occurrence of a large number of defects due to the aging of the device can be prevented.

When a circuit pattern is manufactured in two or more types of processes, the positional deviation between the respective processes is evaluated using a semiconductor wafer having the test patterns shown in FIGS. By feeding back to the exposure apparatus and manufacturing the semiconductor wafer while correcting the position shift between the respective steps in the exposure apparatus, it is possible to obtain a semiconductor manufacturing method in which the occurrence of defects due to the position shift is improved.

Next, an example of a test pattern for easily detecting a defective conductive plug will be described. As described above, when an electron microscope is used, the appearance of an image changes depending on the connection resistance and capacitance of the pattern. Therefore, by forming a pattern in which the difference between the normal pattern and the defective pattern is large, an inspection with high sensitivity can be realized.

6 (a) to 6 (d) are cross-sectional views of the test pattern, FIGS. 6 (e) and 6 (f) are plan views when the test pattern is observed with an electron microscope, FIGS. 6 (g) and 6 (g). FIG. 6H is a sectional view showing a fourth embodiment of the test pattern according to the present invention, and FIG. 6I is a plan view showing a fourth embodiment of the semiconductor wafer provided with the test pattern according to the present invention.

The pattern shown in FIG. 6A is an example often seen in a normal semiconductor circuit pattern. For example, an N-type diffusion layer 13 is formed on a P-type substrate 12, and a conductive plug 2a is formed thereon. Are formed. In FIG. 6B, the conductive plugs 9a are short-circuited. When the conductive plug 9a is short-circuited in this way, the capacity of the conductive plug 9a becomes twice or more the original value, and the difference in brightness from a normal portion that is not short-circuited becomes remarkable. Accordingly, as shown in FIG. 6B, when the conductive plug 9a is short-circuited and is in contact with the substrate by a conductor, the substrate resistance also changes significantly compared with the portion having the PN junction. In addition, the amount of charge-up at the time of observation with an electron microscope is greatly different from that of a normal part, and can be easily identified. However, as shown in FIG. 6C, in the case of the conduction plug 8a in which conduction failure occurs in the portion 8c due to the remaining insulating film at the bottom of the hole, the change in capacitance between the patterns is small,
Also, since the resistance to the substrate is high due to the PN junction in the normal part, there is not much difference in the resistance of such a defect from that in the case of FIG. Therefore, the difference between the defective portion 8c shown in FIG. 6C and the normal portion shown in FIG.
Identification becomes difficult. On the other hand, as shown in FIG. 6D, in order to identify a conduction defect, considering a pattern in which the N-type diffusion layer 13 is not formed, the connection resistance with the substrate is very low in a normal portion. The resistance is high in the conduction failure portion 10, and these differences can be easily identified by observation with an electron microscope. Therefore, as shown in FIG. 6F, the circuit pattern 21 provided with the diffusion layer 13 in contact with the conductive plug 2a.
6 (g), a circuit pattern 22 having no diffusion layer is provided, and these circuit patterns 21 and 22 are formed on the end of the semiconductor chip 6 as a short detection pattern 21 and a conduction failure detection pattern 22, respectively. Inspection can detect major defects more sensitively than products. Of course, if the pattern of the main body is the same as the short detection pattern 21, only the conduction failure pattern may be used as the test pattern, and vice versa. FIGS. 6E and 6F are diagrams when the circuit patterns 21 and 22 are observed with an electron microscope, respectively.
When the circuit pattern 21 is short-circuited, for example, the conductive plug 2a becomes bright, and thus can be distinguished from other conductive plugs. Also, since the circuit pattern 22 is bright, if any of the conductive plugs 2a becomes defective in connection, the conductive plug becomes dark, for example, so that the defective connection can be easily identified.

Next, by applying the embodiment shown in FIG.
A method of inspecting both defects with one pattern will be described with reference to FIG.

FIG. 7 shows a fifth test pattern according to the present invention.
It is a top view which shows the Example of FIG.

In FIG. 7, the test pattern 35 has the circuit patterns 21 shown in FIG. 6G and the circuit patterns 22 shown in FIG. This test pattern 35 may be arranged at the end of the semiconductor chip, or a wafer of this test pattern may be manufactured and used for defect inspection. In the test pattern 35, by arranging the same type of pattern in a direction in which rules are strict, it is possible to surely inspect a direction in which a short circuit is more likely to occur. For example, if the distance between the test pattern 21 and the test pattern 22 is a and the distance between the conductive plugs 2a of the test pattern 21 or 22 is b, a> b
In the case of, as shown in the figure, the same type of circuit patterns are arranged in the horizontal direction, and different types of circuit patterns are arranged in the vertical direction. Even in the case of the comparison inspection using the repetition of the repetition pattern, as shown by the arrow in FIG. 7, the inspection can be performed in the same manner as the normal pattern by comparing every other pattern.

When a similar pattern inspection is to be performed on a multilayer pattern, the circuit pattern shown in FIG. 8 may be used.

FIGS. 8A and 8B are cross-sectional views showing another embodiment of the multilayer circuit pattern. In FIG. 8A, an N-type diffusion layer 13 is provided on a P-type substrate 12, an insulating film 32 is formed thereon, a hole is provided in the insulating film 32, and a conductive plug 33b is buried. An insulating film 34 is formed to bury the conductive plug 33a. FIG. 8B
In the above, an insulating film 32 is formed on the P-type substrate 12, a hole is provided in the insulating film 32, a conductive plug 33b is buried, and another insulating film 34 is formed.
Is embedded. Thus, the same pattern may be laminated. In this case, if a defect has occurred in the previous step, the defect is similarly observed in the step of interest.

FIG. 9A is a cross-sectional view of a short circuit pattern of the first layer, FIG. 9B is a plan view of FIG. 9A observed by an electron microscope, and FIG. FIG. 9D is a cross-sectional view showing a circuit pattern, and FIG. 9D is a plan view of FIG. 9D observed with an electron microscope. As shown in FIG. 9A, when a short defect occurs in the portion 9c of the conductive plug 9b at the stage of manufacturing the first layer of the circuit pattern, when this test pattern is observed with an electron microscope, FIG. 9B
As shown in FIG. 7, the short-circuited conductive plug 9b is observed brightly. As shown in FIG. 9C, when the second layer is completed, a portion 8 between the conductive plug 8a and the conductive plug 8b is formed.
When a conduction failure occurs in c, when this is observed with an electron microscope, the conductive plug 8a having the conduction failure is observed dark. However, the short defect generated in the first layer portion 9c is observed bright as in FIG. 9B.

As described above, regardless of whether the defective portion is located on the first layer or the second layer, it is difficult to observe the defect by the electron microscope.
There is a possibility of showing similar results. Therefore, a method for determining the generation step will be described with reference to FIG.

FIG. 10 is a diagram for specifying a process of generating a conduction defect in a multi-layer test pattern. FIG. 10A is a plan view showing a portion where a conduction defect occurs as observed in the first layer.
0 (b) is a plan view showing a conduction failure portion observed in the second layer, and FIG. 10 (c) is a plan view showing a conduction failure portion occurring in the second layer. As shown in FIG. 10A, a defect 17a is observed on the inspection result screen 14 of the first layer,
As shown in FIG. 10B, the inspection result screen 15 of the second layer
In this case, the defect 17b is observed. FIG. 10C shows the defect 17 b on the inspection result screen 15 to the defect 1 on the inspection result screen 14.
This is an inspection result screen from which 7a has been removed, and it is possible to specify a defect 17c generated between the first layer and the second layer.

Although FIGS. 8, 9 and 10 show examples of two layers, even in the case of a multi-layer structure, inspection can be performed by forming a stacked pattern in the same manner.

Next, a description will be given of a test pattern for inspecting the wiring step with high sensitivity.

FIG. 11 is a view showing a fifth embodiment of a semiconductor wafer having a test pattern according to the present invention.
1 (a) is a plan view of a semiconductor wafer, FIG. 11 (b),
FIG. 1C is a cross-sectional view of a circuit pattern of the test pattern, and FIG.
FIG. 1D is a plan view of FIG. 11A observed with an electron microscope. The test pattern shown in FIG.
It is configured by alternately arranging the circuit patterns 36 and 37 shown in (b) and (c). In the circuit pattern 36 of FIG. 11B, the conductive plug 33 is directly connected to the P-type substrate.
a, 33b are provided, and the wiring pattern 19 is provided on the conductive plug 33a. In the circuit pattern 37 of FIG. 11C, an N-type diffusion layer 13 is provided on a P-type substrate 12, a first-layer conductive plug 33b is provided thereon, and a conductive plug 33b is formed thereon. A wiring pattern 18 is provided thereon.

In FIG. 11, wiring patterns 18 and 19
Have different connection resistances with the substrate. That is, since the wiring pattern 18 is connected to the N diffusion layer 13 via the conductive plugs 33a and 33b, the connection resistance with the substrate 12 is high, but the wiring pattern 19 is not connected to the conductive plugs 33a and 33b.
, The connection resistance with the substrate 12 is low. Such a wiring pattern 3
When the wirings 6 and 37 are used, when a short circuit occurs between the wirings, the high-resistance wiring pattern 18 always short-circuits with the low-resistance wiring pattern 19, so that the substrate resistance of the high-resistance wiring pattern 18 is also low-resistance wiring pattern. 19, and the difference from the normal part becomes remarkable. Here, FIG. 11 shows an example in which two layers of conductive plugs 33a and 33b are stacked, but the number of layers may be one or three or more.

FIG. 12 is a plan view showing an observation example when a short defect occurs using the test pattern shown in FIG. As indicated by an arrow 20 in FIG. 12, the wiring pattern 18 originally observed as dark is the wiring pattern 1 next to it.
When the pattern is short-circuited with 9, the pattern is observed brightly, and the difference from the dark pattern in the normal part can be easily found. With an inspection device using an electron microscope image, a defective portion can be easily detected. If the electrical resistance of the wiring pattern 19 is sufficiently low, the brightness of the entire wiring changes if a short circuit occurs even at one point in the wiring as shown in the figure.
In this case, observation with an electron microscope image provides sufficient sensitivity even at a relatively low magnification.

A method for efficiently inspecting using the test pattern shown in FIG. 11 will be described with reference to FIG.

FIG. 13A is a plan view of an electron microscope image obtained by observing the whole, and FIG. 13B is a plan view of an electron microscope image obtained by enlarging a part of the image.

As shown in FIG. 13A, an inspection is performed at a low magnification, a wiring pattern position including a defect (a region surrounded by a dotted line) is specified, and then a wiring pattern position including a defect at a higher magnification is determined. 13B, defects are clearly observed as shown in FIG. 13B. Therefore, if only the periphery of the wiring is inspected, efficient inspection can be performed. When the location where the short circuit occurs is not the outermost surface, it is preferable to use an optical inspection / observation device capable of observing the state of the lower layer.

Further, as shown in FIG. 11, the wiring patterns 18 and 19 are not arranged in a horizontal line, but are formed by dividing the wiring patterns 18 and 19 as shown in FIG. Occurs, only the wiring pattern in the short section where the short-circuit has occurred among the wiring patterns 18 connected to the P-type diffusion layer 13 becomes bright, so that it is easy to determine in which part of the wiring the short-circuit occurred. You can check.

FIG. 14 is a view showing a seventh embodiment of a semiconductor wafer having a test pattern according to the present invention. FIG. 14 (a) is a plan view of a circuit pattern, and FIG.
(B) is a plan view when observed with an electron microscope.

In the example of FIG. 11, the wiring pattern 19 that is not connected to the diffusion layer 13 has a higher contrast with respect to the underlying insulating film, and thus has a higher sensitivity to a disconnection defect. Therefore, the inspection can be performed with higher sensitivity than the pattern connected to the entire diffusion layer. Therefore, FIG.
As shown in FIG. 5, if only the wiring pattern 18 connected to the N-type diffusion layer 13 is formed so as to be divided and the wiring pattern 19 is formed so as not to be divided, the same effect as that of FIG. Disconnection inspection can be performed with high sensitivity by using a wiring longer and closer to the product.

FIG. 15 is a plan view showing an eighth embodiment of a semiconductor wafer having a test pattern according to the present invention.

Both the test pattern using the conductive plug of FIG. 7 and the test pattern of FIG. 11 obtain an image at a low magnification in addition to the detection by the comparative inspection, and determine the presence or absence of a defect from the average signal amount. Only the areas determined to be defective are
A more detailed inspection method is also effective for speeding up the inspection.

This method will be described with reference to FIG.

FIG. 16 (a) is a plan view of a semiconductor wafer, FIG. 16 (b) is a plan view of an observation image of a semiconductor chip provided on the semiconductor wafer, and FIG. 16 (c) shows the average brightness of the semiconductor chip. FIG. In FIG. 16C, the horizontal axis represents the chip coordinates X, and the vertical axis represents the average brightness L.

As shown in FIG. 16A, semiconductor chips 39 are arranged on a semiconductor wafer.
Now, each semiconductor chip 3 of a specific row of semiconductor chips 40
In the case where an image at the same place in FIG.
It is assumed that an image as shown in FIG. When the average brightness is plotted, as shown in FIG. 16C, the average brightness of a chip in which conduction failure occurs frequently is smaller than that of a normal chip. In such a case, if only a chip having a small average brightness is analyzed in detail, the cause of the failure can be determined without inspecting the entire wafer.
An example of poor continuity has been shown.
On the contrary, it becomes bright. In addition to the average brightness, other feature amounts such as image variance and texture may be used. For example, the brightness of the pattern of each of the conductive plugs 2a, 33a, 33b in the field of view may be measured, and the average or variation thereof may be used. In the example of FIG. 16, the brightness of the chips arranged in a line was evaluated. However, if the sampling point is a portion having the same structure (for example, a fixed position in a chip or a shot), the rest of the chip is one by one. One for every two shots, one
An appropriate selection may be made according to the purpose, such as five places in a shot.

In some cases, failures due to failures in the manufacturing apparatus occur suddenly frequently. Depending on the characteristics of the manufacturing apparatus, there are many cases in which the tendency in the wafer is clear or the fluctuation tends to occur daily. Therefore, for example, FIG.
The horizontal axis of the graph in (b) may be changed to day, wafer, or lot to evaluate the image variation at a fixed position in the wafer. Such a method is particularly effective when the contrast of a defect is high as in the test pattern of the present invention.

Next, a method of forming a test pattern will be described. Since the test pattern of the present invention can be formed by exactly the same process as that of a product, it is only necessary to create a necessary test pattern in design data in advance, and it is not necessary to increase the number of manufacturing steps. Also, if the same process and dimensions are used for the circuit pattern of the semiconductor device of the main body, all defects (including residual thin films and differences in the depth of holes) caused by the shapes generated in these patterns will be eliminated. Occurs at a density similar to that of the pattern. In addition, defects such as foreign matter occur relatively randomly, and it is considered that the defects also occur at the same density in the test pattern and the circuit pattern of the main body. Therefore, if a defect can be detected with high sensitivity in a circuit pattern by the test pattern of the present invention, it is possible to obtain the effect of improving the reliability of estimating the defect occurrence rate and quickly investigating the cause of the defect and taking measures. In order to obtain such an effect, it is desirable that the film thickness, pattern density, and the like are almost the same as those of the main circuit, and it is desirable that the circuit is disposed as close as possible to the main pattern.

It is said that the area of the test pattern is sufficient to be about several percent of the entire wafer when managing defects caused by the process. Even if a test pattern of several percent of the wafer is formed and the whole is inspected, the inspection can be performed in several tens of minutes even with an inspection apparatus that requires several to several tens of hours on the entire surface of the wafer. Becomes Of course, instead of the same wafer as the semiconductor device of the main body, only the test pattern may be formed on the entire surface of the wafer, and the test pattern may be periodically supplied to the production line for use. The arrangement of the test patterns may be an efficient arrangement mainly for the device that performs the inspection. When scanning the surface by continuously moving the stage, the stages may be arranged in a line as shown in FIG. In this case, if the field of view of the inspection device is 20 micrometers,
The width of the test pattern may be set to 20 micrometers. Also, when performing an inspection by step & repeat,
What is necessary is just to form a pattern which can be inspected efficiently according to the visual field. For example, if the field of view of the inspection apparatus is 20 micrometers square, the test pattern is also set to 20 micrometers square or an integer multiple thereof and arranged at four corners in the shot. In this case, if the comparison inspection is performed as in the embodiments shown in FIGS. 7 and 11, it is necessary to arrange the comparison direction so that patterns of the same type are always compared.

As the types of test patterns, those which can detect defects of a type which may be generated in each step with high sensitivity may be formed preferentially. Further, when various patterns are formed like a logic wafer, if the test pattern is formed in the same shape as the most difficult pattern (for example, the pattern having the smallest line width or pitch) among them, Good.

As described above, FIGS. 6, 7, 11, 1
By using the semiconductor wafer having the test patterns shown in 4 and 15, it is possible to detect a defect such as a short circuit in the circuit, a disconnection, a short circuit due to a foreign substance, and a location where the defect has occurred. By estimating the shape of the circuit of the semiconductor chip, the film thickness of the wiring pattern, and the insulation film thickness from these information, estimating the cause device, and manufacturing the semiconductor wafer while correcting the cause device according to each defect, And a method for manufacturing a semiconductor wafer in which the generation of pits is improved.

Next, a description will be given of a method for managing a defect of a circuit of a semiconductor chip based on an inspection result based on these test patterns. The test pattern is considered to have defects at the same density as the semiconductor device of the main body. However, the use of the test pattern of the present invention enables defect detection with higher sensitivity than the circuit pattern of the semiconductor device of the main body.

FIG. 17A is a characteristic diagram showing the number of detected defects of the semiconductor chip, FIG. 17B is another characteristic diagram showing the number of detected defects of the test pattern, and FIG. 17C is a graph showing the ratio of defective bits. It is. 17A and 17B, the horizontal axis represents the brightness difference i from the normal part, and the vertical axis represents the number of detected defects Di. The figure shows the number Di of defects detected when the semiconductor chip and the test pattern are inspected for the same area with the same sensitivity. The areas of the graphs in FIGS. 17A and 17B indicate the number of detected defects Di. The characteristics of the test pattern and the semiconductor chip as shown in FIG. 4A, that is, when the connection resistance is low, the signal amount is large and the display is bright, and when the connection resistance is high, the signal amount is small and the image is dark. , It can be said that the larger the difference in brightness from the normal part is, the more fatal the defect is. In the test pattern of the present embodiment, since the change in brightness of the electron microscope image at the defect portion can be emphasized, more defects can be detected. However, emphasizing the appearance of the defect in this way,
At the same time, even subtle variations in characteristics that do not result in defects are emphasized, which may cause false reports. In order to manage the production line, it is necessary to remove such false alarms and manage only significant defects. In a memory product or the like, a pass / fail decision may be made for each bit after the end of the previous process. If the number of defective bits indicates the number of detected defects, for example, FIG. ),
It becomes like the shaded part of (b). The area of the hatched portion in FIG. 17 is obtained by multiplying the defect occurrence rate Pd of the tested bit shown in FIG. , And among the detected defects, only those having a larger difference in brightness from the normal part are determined to be defective. That is, assuming that the number of detected defects of the brightness difference i is Di, (I <= i <∞) ΣDi <=
The range of I, which is Pd · B, is the shaded portion in FIG. Using this result, the white portion in FIG. 17B is a portion that is detected as a defect but is not a defect, and only a defect having a brightness corresponding to a hatched portion needs to be managed at the time of inspection. You can see that. The test sensitivity can be changed based on this result to reduce false alarms. Here, FIG.
The area of the hatched area in FIG. 7A is smaller than the area of the hatched area in FIG. 17B, and all of the detected defects are defective bits. This means that all the defective bits can be detected. That is, that is, (0 <= i <∞) ΣDi <= P
The case of dB is shown, which means that the inspection sensitivity is insufficient.

Defects that cause defects occur in various steps, but this method does not excessively reduce false alarms. When two types of circuit patterns 21 and 22 are mixed as in the embodiment shown in FIG. 7, it is necessary to evaluate each pattern. The difference i in brightness between the detected defective portion and the normal portion can be obtained by processing an electron beam image or the like used for inspection. Further, using an inspection apparatus having such a defect automatic classification function, the found defects can be displayed by type or degree. By using the information, the accuracy of management can be further improved. For example, if it is possible to discriminate between a bright defect (short defect) and a dark defect (conduction defect) from the characteristics of the test pattern as shown in FIG. The evaluation may be performed by using only those that match the defect. Although FIGS. 17A and 17B show the number of defects, depending on the inspection method, if a plurality of bits become defective consecutively, it may be calculated as one defect. The accuracy can be further improved by converting the number of detected defects to the number of bits using an image. Further, if there is a function of automatically classifying defects, there is an advantage that the use of information such as the distribution thereof makes it easy to estimate the cause of failure. This is because there are many cases in which defects having distribution occur due to the characteristics of the manufacturing apparatus.

In the embodiment described above, the case where the test pattern is observed using an electron microscope has been mainly described. However, an optical microscope may be used instead of the electron microscope.

As described above, by using the semiconductor wafer provided with the test pattern according to the present invention, it is possible to inspect a test pattern manufactured by exactly the same process as a semiconductor product with higher sensitivity. Also,
By using the results, it is possible to quickly detect what part of the wafer or shot is likely to have a defect and in which process the problem is occurring. By feeding back the information to the device, it is possible to prevent product defects. In addition, since a defective portion can be reliably detected, there is an advantage that the time required for analyzing the cause can be greatly reduced.

By feeding back information on the position where a defect occurs and the type of the defect to the exposure apparatus, the semiconductor wafer is manufactured while adjusting the alignment at the time of exposure, and a semiconductor wafer with few defects is manufactured. be able to.

[0093]

As described above, according to the present invention, the reliability of the inspection can be improved by realizing the inspection with high sensitivity.
In addition, it is possible to prevent a defect in the production line in advance by using the information of the inspection result, and to take an immediate measure.

[Brief description of the drawings]

FIG. 1 is a plan view, a sectional view, and a plan view of a circuit pattern of a semiconductor chip to which the present invention is applied.

FIG. 2 is a plan view showing a first embodiment of a test pattern of a semiconductor wafer according to the present invention, a plan view of a semiconductor chip provided with this test pattern, and characteristics showing the number of short-circuit defects obtained using this test pattern. FIG.

FIG. 3 is a plan view and a characteristic diagram showing a second embodiment of a semiconductor wafer on which a test pattern according to the present invention is arranged.

FIG. 4 is a characteristic diagram showing an example of a connection resistance and a signal amount of a conductive plug, a plan view showing an example when a test pattern is observed with an electron microscope, and a cross-sectional view of the test pattern.

FIG. 5 is a plan view of a test pattern according to the present invention, a plan view showing a third embodiment of the semiconductor wafer, and a cross-sectional view of the test pattern.

FIG. 6 is a sectional view of a test pattern, a plan view when the test pattern is observed with an electron microscope, and a plan view showing a fourth embodiment of a semiconductor wafer provided with the test pattern.

FIG. 7 is a plan view showing a fifth embodiment of the test pattern according to the present invention.

FIG. 8 is a cross-sectional view showing another embodiment of the multilayer circuit pattern.

FIG. 9 is a sectional view of a short-circuit pattern of a first layer,
Plan view of the circuit pattern of the first layer observed with an electron microscope,
FIG. 3 is a cross-sectional view showing a two-layer circuit pattern, and a plan view of the two-layer circuit pattern observed with an electron microscope.

10A and 10B are a plan view showing a portion where a conduction failure has occurred in a first layer and a second layer, and a plan view showing a portion where a conduction defect has occurred in a second layer.

FIG. 11 is a plan view showing a fifth embodiment of a semiconductor wafer having a test pattern according to the present invention, a sectional view of a circuit pattern of the test pattern, and a plan view of the semiconductor wafer observed with an electron microscope.

12 is a plan view showing an observation example when a short-circuit defect occurs using the test pattern shown in FIG.

FIG. 13 is a plan view of an electron microscope image.

FIG. 14 is a plan view of a circuit pattern and a plan view of a semiconductor wafer having a test pattern according to a seventh embodiment of the present invention when observed with an electron microscope.

FIG. 15 is a plan view showing an eighth embodiment of a semiconductor wafer having a test pattern according to the present invention.

FIG. 16 is a plan view of a semiconductor wafer, a plan view of an observation image of a semiconductor chip provided on the semiconductor wafer, and a characteristic diagram showing average brightness of the semiconductor chip.

FIG. 17 is a characteristic diagram of the number of detected defects of the semiconductor chip, another characteristic diagram showing the number of detected defects of the test pattern, and a graph showing the ratio of defective bits.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wiring pattern, 2 ... Conducting hole, 2a, 8a, 8b, 9
a, 9b, 33a, 33b ... conductive plugs, 3, 32, 3
Reference numeral 4 denotes an insulating film, 4 denotes a conductive hole having a displacement, 5 denotes an offset, 6, 39 denotes a semiconductor chip, 7, 31 denotes a test pattern, 8c denotes a portion of poor conduction, 9c denotes a portion of a short defect, and 10 ... 1. Conducting holes in the layer, 11... Conducting holes in the second layer, 1
2 ... P-type substrate, 13 ... N-type diffusion layer, 14 ... Inspection result screen of the first layer, 15 ... Inspection result screen of the second layer, 16 ... Inspection result screen generated between the first layer and the second layer , 17: detected defect, 18, 19: wiring pattern, 20: low-resistance wiring pattern and high-resistance wiring pattern as shown, 21, 22,.
36, 37: circuit pattern, 30: insulating substrate, 38: semiconductor wafer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Takashi Hiroi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Manufacturing Research Laboratory, Hitachi, Ltd. (72) Chie Shishido 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd. Production Technology Laboratory (72) Inventor Asahiro Kuni 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Ltd. Production Technology Laboratory (72) Inventor Kenji Watanabe Kamizuhoncho, Kodaira-shi, Tokyo 5-20-1, Hitachi Ltd. Semiconductor Group (72) Inventor Yutoshi Sugimoto 6-16, Shinmachi, Ome-shi, Tokyo 3 Hitachi Device Co., Ltd. Device Development Center (72) Inventor Mari Nozoe Tokyo 1-280 Higashi Koigakubo, Kokubunji-shi F-term (reference) in Central Research Laboratory, Hitachi, Ltd. 2G 032 AB02 AC01 AD08 AE04 AE08 AE12 4M106 AA01 AA08 AC07 BA02 BA04 BA14 CA10 CA15 CA39 CA50 CA70 5F038 DT10 DT12 EZ20

Claims (27)

[Claims] A first circuit pattern formed in a first step and a second circuit pattern formed in a second step on a semiconductor substrate, wherein the first and second circuit patterns are formed. A semiconductor wafer comprising a test pattern for detecting a defect using a circuit pattern. 2. A semiconductor device comprising: a first plurality of circuit patterns formed in a first step and a second circuit pattern formed in a second step on a semiconductor substrate; A test pattern is formed by arranging the second circuit pattern between the second circuit patterns, and the distance between the first and second circuit patterns is set to the distance between the first circuit pattern and the second circuit pattern. A semiconductor wafer comprising a plurality of test patterns that are changed between values that are less than or equal to a contact value of a circuit pattern. 3. The semiconductor wafer according to claim 2, wherein said plurality of test patterns include said first circuit pattern and said second circuit pattern.
Wherein the distance between the circuit patterns is gradually changed. 4. A semiconductor device comprising: a first plurality of circuit patterns formed in a first step and a second circuit pattern formed in a second step on a semiconductor substrate; A test pattern is formed by arranging the second circuit pattern between the first circuit pattern and the second circuit pattern. A semiconductor wafer, wherein a plurality of test patterns changed among the plurality of test patterns are provided at an end of a semiconductor chip. 5. A first plurality of circuit patterns formed on a semiconductor substrate, and a second circuit formed on the first circuit pattern and arranged so as to be in contact with the first circuit pattern. A first circuit pattern and a second circuit pattern.
A plurality of test patterns arranged such that the second circuit pattern is displaced from the first pattern within a range in which the circuit patterns come into contact with each other. 6. The semiconductor wafer according to claim 5, wherein said plurality of test patterns include said first circuit pattern and said second circuit pattern.
A semiconductor wafer characterized by gradually changing the amount of deviation between circuit patterns. 7. A first circuit pattern formed on a semiconductor substrate, and a second circuit pattern formed on the first circuit pattern and arranged to be in contact with the first circuit pattern. A plurality of test patterns in which the second circuit pattern is displaced with respect to the first pattern within a range where the first circuit pattern and the second circuit pattern are in contact with each other; A semiconductor wafer provided at an end of a chip. 8. A semiconductor device comprising: a first circuit pattern formed on a semiconductor substrate and electrically connected to the semiconductor substrate; and a second circuit pattern electrically connected to the semiconductor substrate. A semiconductor wafer having a test pattern in which a connection resistance between a first circuit pattern and the semiconductor substrate and a connection resistance between the second circuit pattern and the semiconductor substrate are different. 9. The semiconductor wafer according to claim 8, wherein said first circuit pattern is connected to a diffusion layer different from said semiconductor substrate, and said second circuit pattern is directly connected to said semiconductor substrate. Semiconductor wafer. 10. The semiconductor wafer according to claim 8, wherein
A semiconductor wafer, wherein the first circuit pattern and the second circuit pattern are arranged alternately or alternately. 11. The semiconductor wafer according to claim 8, wherein
A first wiring pattern disposed on the first circuit pattern so as to contact the first circuit pattern; and a first wiring pattern disposed on the second circuit pattern so as to contact the second circuit pattern. A second wiring pattern, wherein the first wiring pattern and the second wiring pattern are arranged in parallel with each other and alternately or alternately. 12. The semiconductor wafer according to claim 11, wherein at least one of said first wiring pattern and said second wiring pattern is divided in a direction orthogonal to said parallel direction. Semiconductor wafer. 13. A semiconductor device comprising: a first circuit pattern formed on a semiconductor substrate and electrically connected to the semiconductor substrate; and a second circuit pattern electrically connected to the semiconductor substrate. A test pattern in which the value of the connection resistance of the first circuit pattern with the semiconductor substrate and the value of the connection resistance of the second circuit pattern with the semiconductor substrate are arranged at the end of the semiconductor chip. Semiconductor wafer. 14. A circuit pattern formed on a semiconductor substrate of the semiconductor chip and electrically connected to the semiconductor substrate directly or through a plug, wiring, or the like, wherein the circuit pattern is a part of the circuit pattern of the semiconductor chip. A semiconductor wafer having the same shape and arrangement as those described above, and having a test pattern whose connection resistance with the semiconductor substrate is different from the connection resistance of the circuit pattern of the semiconductor chip. 15. The semiconductor wafer according to claim 4, wherein the test pattern is formed using the same manufacturing process as the circuit pattern of the semiconductor chip. 16. The semiconductor wafer according to claim 15, wherein said test pattern is formed simultaneously with said circuit pattern of said semiconductor chip. 17. A semiconductor wafer according to claim 4, 7 or 13, wherein said test pattern is formed in the same shape and size as said circuit pattern of said semiconductor chip. 18. The semiconductor wafer according to claim 4, wherein the test pattern is formed with a minimum size and a minimum interval among circuit patterns of the semiconductor chip. 19. An inspection apparatus for inspecting a circuit pattern using a physical property of an inspection object such as a charged particle beam image, an optical microscope image, and a resistance value of an element, according to any one of claims 1 to 18. A method for inspecting a semiconductor wafer, comprising inspecting the semiconductor wafer described in the above. 20. A position of the semiconductor wafer according to any one of claims 1 to 7 and 15 to 18 using an electron microscope image, an optical microscope image, or a physical property of an inspection object such as a resistance value of an element. A method for inspecting a semiconductor wafer, comprising detecting an alignment error. 21. A pattern already formed using a physical property of an inspection object such as a charged particle beam image, an optical microscope image, and a resistance value of an element of the semiconductor wafer according to claim 1. Inspection method for semiconductor wafer, characterized by detecting an alignment error 22. The semiconductor wafer according to claim 8, wherein a defect is detected by comparing physical properties of said first circuit pattern or said second circuit pattern. Characteristic semiconductor wafer inspection method. 23. An inspection method using a charged particle beam image or an optical microscope image, wherein the test pattern chip or semiconductor chip of a semiconductor wafer according to claim 1 is repeatedly formed in the wafer. Perform quantitative evaluation or classification of the image signal at a predetermined position in the shot, and manage the semiconductor manufacturing process using the quantitative evaluation value, the classification result, or both information on the distribution in the wafer or the variation between the wafers. A method for managing a manufacturing process, comprising: 24. A defect detected by using a charged particle beam image or an optical microscope image of the semiconductor wafer according to claim 1, and a size of a defective portion detected in the test pattern of the semiconductor wafer. Using an inspection apparatus having a function of classifying features such as coordinates, signal amount, reference level of signal amount or signal amount of reference image signal amount, texture, etc., distribution of each defect feature in the wafer. Alternatively, a manufacturing process management method characterized in that a manufacturing process is managed using information on variation between wafers or aging. 25. Test results of a semiconductor device such as a yield of a semiconductor product or a probe test, and the like.
A method for inspecting a semiconductor wafer, comprising: changing a sensitivity of an inspection by the test pattern or classifying a detection result based on a relationship between the test pattern and an inspection result of the semiconductor wafer inspection method. 26. A position of the semiconductor wafer according to any one of claims 1 to 7 and 15 to 18 using an electron microscope image, an optical microscope image, or a physical property of an inspection object such as a resistance value of an element. Detecting the alignment error and using the error,
A method for manufacturing a semiconductor chip, comprising setting operating conditions of a manufacturing apparatus. 27. A position of the semiconductor wafer according to any one of claims 1 to 7, 15 to 18, using an electron microscope image, an optical microscope image, or a physical property of an inspection object such as a resistance value of an element. A method of manufacturing a semiconductor chip, comprising detecting an alignment error and manufacturing a semiconductor chip while correcting a positional shift of an exposure device of the semiconductor chip using the information of the alignment error.