JP2002049049A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: In a liquid crystal display device in which two layers of transparent electrodes configured as a pixel electrode and a common signal electrode are arranged on the same substrate with an insulating film interposed therebetween, a part of a wiring material has a low resistance. A configuration that reduces defects at the time of fabrication when a suitable Al or Al alloy film is applied. As a material of an electrode disposed in a lower layer, amorphous indium zinc oxide, amorphous indium germanium oxide, or an amorphous oxide transparent conductive film containing these as a main component is used. (1) It is easy to secure the tapered shape at the end of the transparent electrode pattern, and it is possible to prevent poor rotation of the insulating film and the upper electrode. (2) An insulating film having no pinholes and having excellent insulating properties can be laminated on the transparent electrode at a high temperature. (3) Since it can be etched with a weak acid,
Dissolution of the lower metal (Al) wiring can be prevented. (4) Disconnection at a portion where the transparent electrode directly goes over the lower metal wiring can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device of an in-plane switching mode.

[0002]

2. Description of the Related Art As a liquid crystal display device, a thin film transistor TF is used as a switching element in a display area forming a pixel.
An active matrix system having a structure in which a T (TFT: Thin Film Transistor) element is provided is often used. This type of liquid crystal display device employs a structure in which a liquid crystal layer is inserted between a pair of substrates, and the liquid crystal layer is sandwiched between the substrates. One of the substrates (TFT substrate) has a TFT element,
Pixel electrodes, electrodes and wiring for scanning signals and video signals, and terminals for connecting the wiring to an external drive circuit are formed.
On the other substrate (CF substrate) side, a color filter and a counter electrode are formed, and a twisted nematic display system is adopted in which a vertical electric field substantially perpendicular to the substrate surface is applied for display.

In contrast to this method, as a method of improving the viewing angle and the contrast, which have been problems of the liquid crystal display device, a common signal is provided on the TFT substrate side instead of the counter electrode arranged on the color filter substrate side. By disposing the electrodes and applying a voltage between the comb-shaped pixel electrode and the common signal electrode, an in-plane switching (in plain switching) type liquid crystal display device using an electric field component almost parallel to the substrate surface for display is realized. And JP-A-6-160878. The pixel electrode and the common signal electrode may be made of a metal electrode wiring material, or indium tin oxide (ITO) used as a transparent pixel electrode in a twisted nematic display system as disclosed in JP-A-9-73101. : Indium Tin O
xide).

As examples using ITO electrodes, SHLee et al., SID'98 DIJEST, P371 (1998), and SID'99 DIJEST,
In P202 (1999), the pixel electrode and the common signal electrode are composed of upper and lower two layers of ITO electrodes sandwiching an insulating film, and the electrode width of the comb-shaped pixel electrode and the common signal electrode and the distance between the electrodes are reduced. It is reported that by optimizing in the direction, when a voltage is applied between the upper and lower ITO electrodes, a fringe electric field spreading on the upper ITO electrode can be used for driving the liquid crystal. According to this, the aperture ratio and transmittance of the liquid crystal display device of the in-plane switching mode can be substantially improved, and therefore, the luminance can be improved. In this connection, Japanese Patent Laid-Open No. 11-1
No. 25836 and Japanese Patent Application Laid-Open No. 11-202356 have been filed.

[0005]

In the prior art described above, the following four problems arise when a liquid crystal display device is actually manufactured with a high yield. (1) Deterioration of reliability of insulating film In the conventional technology, the pixel electrode and the common signal electrode are composed of upper and lower two-layer ITO electrodes sandwiching the insulating film. To form In this configuration, in order to prevent a short circuit between the pixel electrode and the common signal electrode, it is necessary to form an insulating film having excellent insulation properties without pinholes, poor rotation, etc., between the two transparent electrodes.
In addition, forming an insulating film having excellent insulation properties without pinholes and throwing defects is a problem in that the etchant permeates the lower layer from the pinholes and throwing defects in the pattern forming step of the pixel electrode located in the upper layer. It is also important to prevent the common electrode and the underlying wiring and electrodes from melting and breaking. When an ITO film is used for a transparent electrode located as a lower layer as a common signal electrode, poor adhesion of the insulating film and an insulating film lacking in density tend to occur. The reason will be described below.

[0006] In order to ensure the surrounding of the upper insulating film, it is desirable that the pattern end portion has a forward tapered shape. Polycrystalline ITO
When a film is used, since the etching of the polycrystalline ITO film proceeds along the crystal grain boundaries, the shape of the pattern edge is not only the film quality of the polycrystalline ITO film but also the arrangement and shape of the crystal grains present at the edge. Will greatly depend on For this reason, the pattern ends will have irregularities reflecting the crystal grain boundaries, and it is difficult to control the end shapes to be constant. . When an insulating film is formed on this polycrystalline ITO film pattern, voids and cracks occur at the ends of the polycrystalline ITO film pattern, and poor adhesion of the insulating film occurs.

When an amorphous ITO film is used, the ITO film is generally easily crystallized easily at a low temperature. Therefore, even an amorphous film formed at room temperature tends to become a film containing a microcrystalline component in the film, and a complete amorphous film is obtained. Is extremely difficult (eg, M.andoet al./Journal of Non-Crys
talline Solids 190-200 (1996) 28-32). Since the etching rate of this microcrystalline portion is lower by one to two orders of magnitude than that of the amorphous portion which forms the majority of the film, the amorphous I
It becomes a residue after etching the TO film, and tends to cause patterning failure. Further, a method has been proposed in which crystallization is suppressed by adding hydrogen or water to the film formation atmosphere during the formation of the amorphous ITO film. Since the film contains adsorbed moisture, the film has a portion where the etching speed is high and a portion where the etching speed is low, and the etching speed tends to be non-uniform. As a result, it is difficult to ensure the stability of the tapered shape of the pattern end portion at the time of etching.

For the above-mentioned reasons, when an ITO film is used, it is difficult to stably secure a tapered shape at the end of the pattern regardless of whether it is polycrystalline or amorphous. In addition, the above-mentioned non-uniform and non-uniform film is further disadvantageous in the case where fine cutting of the transparent electrode is required.

On the other hand, a CVD method is usually used for an interlayer insulating film of a TFT.
A silicon nitride film or a silicon oxide film formed by a method or the like is used. For example, when a silicon nitride film is used as an insulating film between the upper and lower transparent electrodes, for example, monosilane, ammonia, or the like is used as a reaction gas, so that the film forming atmosphere is a reducing plasma atmosphere containing active hydrogen. Therefore, when forming a silicon nitride film on the common electrode, polycrystalline ITO, which is an oxide transparent conductive film, is exposed to a reducing plasma atmosphere. It is known that the ITO surface is reduced depending on the film forming conditions, and that silicon nitride causes abnormal growth with the reduced ITO surface as a nucleus. As a result, in the obtained laminated film, not only surface irregularities become remarkable due to abnormal growth and transparency is lost due to cloudiness, but also the denseness and insulating properties of the silicon nitride film itself are reduced.
The abnormal growth reaction of the silicon nitride film is more likely to occur as the flow rate of the reaction gas serving as a supply source of active hydrogen and as the substrate temperature increases. However, for example, in order to obtain a high-quality insulating film for use as a gate insulating film of a TFT element, it is necessary to form a silicon nitride film at a substrate temperature of about 300 ° C., preferably at a higher temperature. Thus, a film is formed. Therefore, it can be said that the process of forming the silicon nitride film on the ITO film is in a state where cracks, pinholes, poor coverage of surrounding portions, and the like are likely to occur. (2) Disconnection of the upper transparent electrode In the case (1), when the above-described poor rotation of the insulating film on the first transparent electrode disposed on the lower layer occurs, the second transparent electrode disposed on the upper layer of the insulating film In addition, when a metal wiring, an electrode, or the like crosses over the defective portion of the insulating film, the tapering shape of the insulating film is not ensured, so that a similar defective contact occurs, and a defect such as disconnection easily occurs. In the configuration in which the fine comb tooth pattern of the upper transparent electrode is processed, disconnection failure is more likely to occur. (3) Dissolution of common signal wiring and common signal electrode In order to realize a larger, high-definition, high-performance liquid crystal display device, the scanning signal wiring, video signal wiring, and common signal wiring used in the liquid crystal display device must be realized. It is necessary to reduce the resistance. Low resistance Al or Al as common signal wiring material
In a configuration in which an alloy film is used, a polycrystalline ITO film is used as a common electrode, and the Al and the polycrystalline ITO film are present on the same plane without interposing an insulating film, the Al electrode is formed when the common electrode formed of the polycrystalline ITO film is processed. There is also a problem that the common signal wiring including the above is dissolved. When processing a polycrystalline ITO film, a strong acid such as HBr is usually used as an etchant. The Al or Al alloy film is easily etched by a strong acid etchant. Therefore, in a configuration in which the common signal wiring which is exposed in the same plane and is similarly exposed to the etchant in the etching process of the common electrode, there is a problem that the common signal wiring pattern is melted or disconnected. Further, even when the common signal wiring and the common electrode are connected via a contact hole opened in the insulating film, if the insulating film has a pinhole, a crack, or the like, the common signal wiring is similarly melted. Happens. A similar problem occurs when a low-resistance Al or Al alloy film is used for a video signal wiring and a polycrystalline ITO film is used as a pixel electrode.

[0010] As one of the solutions to this problem, the layer order of the common signal electrode and the common wiring is switched, and Al or Al is used.
A method of forming and processing a common electrode made of a polycrystalline ITO film in a step before forming and processing a common signal wiring made of an alloy film can be considered as a method of preventing melting of the common signal wiring.
However, in this case, the polycrystalline IT exposed through the pinhole of the Al or Al alloy film in an alkali developing solution in a photoresist film developing process for processing a common signal wiring is used.
It is known that a battery reaction occurs between an O film and an Al or Al alloy film, and a polycrystalline ITO film is dissolved (for example, J. Electrochem. Soc. 139 (1992) pp. 385-), and a common electrode is formed. It is difficult to solve the problem by changing the layer order of the common signal wiring. (4) Disconnection of Common Electrode When a common electrode is arranged on a common signal wiring, a common electrode made of a transparent electrode is connected directly over the common signal wiring without passing through a through hole. In that case, disconnection of the common electrode at the crossover portion becomes a problem. After forming the common signal wiring, polycrystalline ITO
When a film is formed, the crystal grains of the ITO film grow along the step at the end of the common signal wiring pattern in the crossing portion, and the growth direction of the crystal grains competes at the portion where the step starts, and the film is sparse. Parts will occur. Then, in the etching process for patterning the ITO film, since the film over the step of the common signal wiring is sparse, the side etching failure of the pattern is likely to occur at this portion, and the wedge-shaped crack is formed. Electrode tends to be thin. This wedge-shaped electrode thinning causes disconnection of the common electrode. In a configuration that requires fine combing of the common electrode, disconnection is more likely to occur. As a solution, a method of increasing the line width so as not to cause disconnection even if a wedge-shaped electrode is thinned can be considered. However, an essential problem remains, and a problem remains in reliability.

An essential solution is to reduce wedge-shaped electrode thinning. It is an object of the present invention to make the side etching rate of the pattern at the step crossing over the step equal to that at the step non-stepping over, that is, to form a transparent electrode film of uniform film quality at the step crossing and to process the same. This is a fundamental solution. In addition, even when an amorphous ITO film is used as the common electrode, since there is a heterogeneous film portion having a different etching behavior as described above,
It is not possible to ensure sufficient reliability in the portion over the step. Therefore, the same problem as in the case of using the polycrystalline ITO film remains.

A similar problem occurs in a configuration in which a pixel electrode directly passes over a source / drain electrode of a thin film transistor without passing through a through hole.

An object of the present invention is to provide a liquid crystal display device in which two layers of transparent electrodes configured as pixel electrodes or common signal electrodes are arranged on the same substrate with an insulating film interposed therebetween. Even when a low-resistance Al or Al alloy film is applied to a part of the wiring material for higher performance than higher definition, the above-mentioned problems (1) to (4) can be solved, and the defect at the time of fabrication can be reduced. An object of the present invention is to provide a liquid crystal display device having a configuration that can be reduced.

[0014]

According to one embodiment of the present application, a pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates include a plurality of scanning signals. A plurality of wirings, a plurality of video signal wirings intersecting the wirings in a matrix, and a plurality of thin film transistors formed corresponding to respective intersections of the wirings, and surrounded by a plurality of scanning signal wirings and the video signal wirings At least one pixel is configured corresponding to each region, and each pixel has a common signal electrode connected to a plurality of pixels and a pixel electrode connected to a corresponding thin film transistor. The pixel electrode and the pixel electrode partially overlap with an interlayer insulating film interposed therebetween, and an electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode. And at least a part of each of the common signal electrodes is formed of a transparent conductive film, and the second transparent electrode disposed on the liquid crystal layer side via the insulating film among the pixel electrode and the common signal electrode has a slit shape, or A liquid crystal display device that is processed into a comb shape, and includes a first wiring or a first electrode using a metal material, a first transparent electrode on a side closer to the first substrate of the pixel electrode and the common electrode. The electrode and the first wiring or at least a part of the first electrode are stacked and connected, and the first wiring or the first electrode is disposed closer to the first substrate with respect to the first transparent electrode. In the above configuration, the first transparent electrode is made of amorphous indium zinc oxide, amorphous indium germanium oxide, or an amorphous oxide transparent conductive film containing these as main components.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle of the present invention will be described below by taking as an example the case of amorphous indium zinc oxide (hereinafter abbreviated as IZO: Indium Zinc Oxide) based on experimental results obtained by the present inventors.

FIG. 38 shows that the amorphous I of the present invention
An observation example of the pattern shape when the ZO film is processed into a fine comb pattern of 3 μm as an example is shown. amorphous
As for the shape of the pattern end portion of the IZO film, a uniform forward taper shape of approximately 45 ° was secured, and it can be seen that uniform etching with good controllability was realized. When an insulating film is formed on the insulating film, the pattern ends can be well adhered, and an insulating film having excellent physical and electrical insulating properties can be obtained. Furthermore, even when metal wiring, transparent electrodes, etc. are processed and formed on the upper layer of the insulating film, the surroundings of the insulating film are ensured, so that there is no immersion of the etching solution and the amorphous layer already formed on the lower layer is formed. Dissolution of the fine comb tooth pattern of the IZO film can be prevented.
Also, even when the metal wiring and the transparent electrode formed on the upper layer cross over the step at the end of the IZO fine comb tooth pattern via the insulating film, the surroundings of the upper metal wiring and the transparent electrode can be secured to prevent disconnection. it can. In addition, short-circuit failure between the IZO fine interdigital electrode pattern and the metal wiring and transparent electrode located in the upper layer can be reduced.

FIG. 39 shows a comparison of measurement examples of X-ray diffraction lines of the IZO film of the present invention and the amorphous ITO film of the conventional example. Regarding the results of the IZO film formed at room temperature, in addition to the film after the sputtering, the results when the crystallization is accelerated by further performing a heat treatment are also described. IZO
As shown in FIG. 39 (a), the film was heated at 240 ° C. after sputtering.
No crystal peak was observed even after the heat treatment at 350 ° C., and it was found that a homogeneous film having no crystal component was obtained. On the other hand, in the conventional amorphous ITO film, as shown in FIG. 39 (b), in addition to a gradual amorphous peak in the film after sputtering, an indium oxide peak indicating the presence of a microcrystalline component was recognized. It can be seen that the fine crystal component is contained in the powder.

FIG. 40 shows an IZO film and an amorphous ITO.
An example of observation of a film surface SEM photograph during etching of a film is shown. As shown in FIG. 40 (a), the amorphous IZO film has almost no microcrystalline components as irregularities and residues on the etched surface of the film, and a uniform film can be formed as a whole.
It can be seen that the etching was performed uniformly. On the other hand, in the conventional amorphous ITO film, as shown in FIG. 40B, most of the film is in an amorphous state, but it can be seen that a microcrystalline component exists in the film. Further, it can be seen that many irregularities such as vacancies also exist in the amorphous portion of the film, and there are sparse portions of the film with a high etching rate. In the case of using amorphous ITO, the presence of the microcrystalline component and the sparse portion of the film causes non-uniformity at the time of etching, and causes defects such as etching residue and electrode thinning.

As described above with reference to FIG. 39, the amorphous IZO film exists as a stable amorphous film without being crystallized even when exposed to a high-temperature atmosphere. The IZO film is a transparent conductive oxide film like the ITO film, but the IZO film containing zinc is more excellent in resistance to a reducing plasma atmosphere than the ITO film containing tin. Therefore, even when the SiN film is formed on the IZO film at a high temperature of, for example, 350 ° C., the reduction reaction on the surface of the IZO film can be suppressed. Thereby, abnormal growth of the SiN film can be suppressed, and a film excellent in denseness can be obtained. Thus, even when SiN is used as the insulating film on the transparent conductive film, the use of the amorphous IZO film of the present invention as the transparent conductive film makes it possible to form a SiN film excellent in insulation and denseness. . Since pinholes can be reduced more densely than when formed on an ITO film, short-circuit failure between electrodes can be reduced even in a configuration in which a capacitance is formed between upper and lower transparent electrodes. Also, the Si formed on the IZO film
Even when the second transparent electrode located in the upper layer is further patterned on N, the immersion of the etching solution from the pinhole portion does not occur, and the amorphous IZ located in the lower layer is not formed.
No dissolution of the O film occurs.

Next, when the amorphous transparent conductive film of the present invention and electrodes and wirings made of an Al or Al alloy film are arranged on the same plane and the transparent conductive film is processed, damage to the Al film or the Al alloy film is caused. The advantage over the reduction effect will be described. Table 1 shows the etching rates of the transparent conductive film and the Al film with respect to various transparent conductive film etching solutions.

[0021]

[Table 1]

In the present embodiment, as an example, hydrobromic acid (48%, 60 ° C.) as a strong acid, and oxalic acid (2
wt%, 40 ° C.) and an amorphous IZO film, a polycrystalline ITO film, and an Al
The film etching rate was determined.

With hydrobromic acid used as an etchant for the polycrystalline ITO film, the etching rate ratio (selectivity) between the polycrystalline ITO film and the Al film was 1.2: 0.9. This indicates that when the surface of the Al film is exposed to hydrobromic acid, which is an etchant for the polycrystalline ITO film, the Al film is dissolved, and the pattern is easily lost or disconnected.
Also, when oxalic acid, which is a weak acid, is used as an etching solution for the polycrystalline ITO film, the etching rate of the polycrystalline ITO film itself becomes two orders of magnitude lower than when hydrobromic acid is used. It takes time and is not practical. In addition, when oxalic acid is used, the etching rate of the Al film tends to be higher than that of the polycrystalline ITO film, so that the pattern disappearance and disconnection during long-time etching become more remarkable.

On the other hand, it can be seen that the etching rate of the amorphous IZO film can secure a sufficiently high etching rate even when oxalic acid, which is a weak acid, is used.
The etching selectivity between the amorphous IZO film and the Al film when oxalic acid was used was 2.583: 0.005, indicating that the Al film was hardly etched by oxalic acid. This means that even when the surface of the Al film is exposed to oxalic acid during the etching of the amorphous IZO film, the Al film does not dissolve and the pattern does not disappear or break. That is, it is shown that the configuration in which the amorphous IZO film directly contacts the Al electrode wiring can be easily realized by applying the amorphous IZO film of the present invention. In addition, the damage to the photoresist film at the time of etching can be reduced as compared with the case where a halogen acid such as hydrochloric acid or hydrobromic acid or a strong acid such as nitric acid is used as in the case of a polycrystalline ITO film. Pattern precision can be improved, and finer processing can be performed.

Next, the superiority of the amorphous transparent conductive film of the present invention with respect to disconnection at a portion over a step is described.

FIG. 41 is a schematic plan view of the step over the step when the transparent electrode pattern is disposed over the step at the end of the wiring electrode pattern. Using this configuration, the disconnection state of the transparent electrode pattern at the step over the step was investigated.
As described above, in such a configuration, the wedge-shaped electrode thinning is likely to occur in the portion over the step as shown in FIG. When the width of the thinned electrode is large, disconnection is likely to occur. Conversely, by reducing or eliminating the width of the thinned electrode, disconnection at a portion over a step can be reduced or prevented.

The wedge-shaped electrode thinning occurs due to the difference in the side etching rate between the part (a) over the step and the part (b) over the non-step. Therefore, the redundancy against disconnection can be evaluated using both side etching rates. Specifically, if the side etching rates in (a) and (b) are the same, wedge-shaped electrode thinning does not occur, so it can be said that there is redundancy for disconnection. Here, it should be noted that when the etching rate in the depth direction of the film is high, there is a case where the side etching rate is not a problem even if it is high. Therefore, the side etching rate was evaluated using a value standardized by the etching rate in the depth direction of the film. As an example of the wiring pattern, for example, a metal such as Cr was formed simulatedly, and a transparent electrode pattern was formed so as to cross over it orthogonally.

Table 2 shows evaluation examples of the redundancy of the amorphous IZO film against disconnection according to the present invention. Specifically, in (a) the step crossing portion and (b) the non-stepping portion,
The ratio of the side etching rate to the etching rate of the amorphous IZO film (hereinafter simply referred to as the etching rate ratio) is shown in comparison with the conventional polycrystalline ITO film. As an etchant for patterning, for example, oxalic acid was used for the amorphous IZO film, and hydrobromic acid was used for the polycrystalline ITO film.

[0029]

[Table 2]

It can be seen that the etching rate ratio of the amorphous IZO film is slightly different from the etching rate ratio in the non-overlapping portion, although the overpassing portion is slightly fast. That is, the amorphous IZO film has almost no difference in the etching behavior between the crossing portion and the non-crossing portion.
It can be seen that there is redundancy for disconnection. On the other hand, in the conventional polycrystalline ITO film, not only the etching rate ratio of the non-crossing portion of the amorphous IZO film is larger than the etching rate ratio of the non-crossing portion of the amorphous IZO film, but also in the crossing portion. About 2 of etching rate ratio
Twice as large as the amorphous IZ of the present invention.
It can be seen that there is no redundancy for disconnection as compared with the O film.

This difference is due to the difference in homogeneity of the transparent conductive film. In the case where the transparent conductive film is the uniform amorphous film of the present invention, since there is no crystal grain unlike the polycrystalline ITO film, the film is present evenly over the step over the step. As a result, even during etching for forming a pattern, uniform etching with a substantially constant side etching rate can be realized between a step crossing portion and a non-step crossing portion, and wedge-shaped electrode thinning hardly occurs so as to cause disconnection. On the other hand, in the polycrystalline ITO film, since the growth direction of the crystal grains competes at the step portion, the crystal grains are extremely irregularly arranged at the portion over the step difference. Since the etching rate of the portion where the crystal grains are irregular is higher than that in the portion where the step does not cross the step,
A wedge-shaped electrode thinning occurs at a portion over the step.

In the above embodiment, a polycrystalline ITO film has been described as a conventional example.
Even in the TO film, since the film has an inherent non-uniformity as shown in FIG. 41, the electrode thinning similar to the polycrystalline ITO film is likely to occur.

Next, the redundant effect in the process when the coating type insulating film of the present invention is added between the upper and lower transparent electrodes will be described. By adding the coating type insulating film, the reliability of the interlayer insulating film between the upper and lower two transparent electrodes can be further improved.

FIGS. 42A and 42B are views showing a structure used to verify the effect of the coating type insulating film. FIG.
In No. 2, the insulating film on the two-layer transparent electrode was (a) a configuration of only a silicon nitride film, (b) a configuration in which a silicon nitride film and a coating type insulating film were stacked and arranged, and the upper transparent electrode was processed in that configuration. At this time, the size and number of pinholes generated in the lower transparent electrode by the etching solution permeated through the defective portion of the interlayer insulating film were evaluated.

Table 3 shows an example of the number of pinholes per unit area in the configuration of FIGS. 42 (a) and 42 (b), arranged for each pinhole diameter.

[0036]

[Table 3]

As can be seen at a glance from the results, the configuration (b) in which the silicon nitride film and the coating type insulating film are formed by lamination has a larger number of pinholes than the configuration (a) in which only the silicon nitride film is formed. It can be seen that it can be reduced to about 1/100 or more. This is due to pinholes, cracks, etc. generated in the silicon nitride film due to dust generation, flakes, etc. during the process.
This is due to the effect that the coating-type insulating film embeds and covers and repairs the poor rotation of the lower layer over the step. In this embodiment, the upper and lower transparent conductive films are made of the same material, but when different materials are used, for example, the lower transparent electrode is made of an amorphous IZO film, and the upper transparent conductive film is made of polycrystalline ITO. In this case, since the amorphous IZO film is more easily dissolved in the etching solution for the polycrystalline ITO film, the silicon nitride film and the coating type insulating film are stacked in the configuration of FIG. Needless to say, the effect is more remarkably exhibited in the formed structure (b).

Therefore, by using the coating type insulating film of the present invention as the interlayer insulating film between the upper and lower two transparent electrodes, the dissolution and disconnection of the lower transparent electrode during the processing of the upper transparent electrode can be greatly reduced. It can be seen that the yield can be significantly improved. Similarly, during processing of the upper transparent electrode, corrosion of wiring, electrodes, etc., made of a metal material located below the upper transparent electrode,
Dissolution can be similarly prevented.

It is needless to say that the above-described effect of covering the defective portion of silicon nitride can also reduce short-circuit failure due to insulation failure between the upper and lower transparent electrodes.

Further, the coating type insulating film has an effect of flattening a step of a base. As a result, it is possible to ensure the surroundings of the transparent electrode disposed in the upper layer, so that disconnection of the upper transparent electrode can also be prevented.

Here, as the coating type insulating film is thickened, the effect of embedding pinholes and cracks and the effect of planarization are improved, but the voltage applied between the lower transparent electrode and the upper transparent electrode is reduced. When the liquid crystal display device is formed by the lowering due to the coating type insulating film, improvement of the driving voltage becomes a problem. On the other hand, although the above-mentioned problem of voltage drop is solved by reducing the film thickness, the effect of embedding pinholes and cracks is reduced. From the above, the thickness of the coating type insulating film is 0.2 to 4.0 μm, and more preferably 0.2 to 2.0 μm.
The range of m is good.

Further, in the above embodiment, the effect of the combination with the coating type insulating film has been described by taking the silicon nitride film as an example. However, the same defects occur when other insulating films, for example, a silicon oxide film are used. Partial embedding effect was obtained.

In the above, the transparent conductive film was formed by changing the conditions in the DC sputtering method or the RF sputtering method. For example, an amorphous IZO film is made of IZO in which the amount of zinc added to indium is 10 at%.
A target was used, and Ar or 5% oxygen-added Ar was used as a sputtering gas (the amount of oxygen added was adjusted to an amount that minimizes the specific resistance of the obtained IZO film).
The sputtering power was 100 to 1000 W, the sputtering gas pressure was 0.27 to 1.3 Pa, the substrate temperature was room temperature to 350 ° C., and the film thickness was 50 to 300 nm. ITO was formed by changing the target to ITO. a-ITO
The film was formed using Ar, oxygen-added Ar, or water-added Ar of several percent as a sputtering gas. If the added amounts of oxygen and water are too large or too small, the specific resistance of the film and the microcrystalline component in the film are increased. Sputter power,
The sputtering gas pressure was the same as that of amorphous IZO, and the substrate temperature was not heated. The film thickness is 50-300
nm. The polycrystalline ITO film was formed by using Ar or 5% oxygen-added Ar as a sputtering gas and adjusting the oxygen addition amount. Sputtering power and sputtering gas pressure were the same as those of amorphous ITO. The substrate temperature was 180 to 350 ° C., and the film thickness was 50 to 300 nm.

In the above embodiment according to the principle of the present invention,
The amorphous IZO film has been described as an example, but amorphous indium germanium oxide or amorphous IZ
It has been confirmed that the same effects as those of the above-mentioned amorphous IZO film can be obtained with an amorphous oxide transparent conductive film mainly containing O and amorphous indium germanium oxide.

In the above embodiment according to the principle of the present invention,
The amount of zinc added to indium (X / In + X) in the amorphous IZO film (X / In + X): the number of atoms of In... Indium and the number of atoms of X... %. Further, from the viewpoint of not only the homogeneity of the amorphous transparent conductive film, but also the basic characteristics such as transparency and specific resistance, the film obtained in the range of the added amount has sufficiently practical characteristics.

The thickness of the amorphous IZO film is 50
The thickness was set to about 300 nm, but by setting it in this range, an amorphous IZO film having no coloring and high transmittance could be obtained. More desirably, when the thickness is in the range of 50 nm to 150 nm, an amorphous IZO film having no coloring and high transmittance can be obtained.

Further, by setting the forward taper angle of the pattern end portion of the amorphous IZO film to 10 ° to 80 °, it was possible to secure the circumference of the insulating film formed in the upper layer. More preferably, the forward taper angle of the pattern end is set to 30.
It is preferable that the angle be between 60 ° and 60 °.

A specific embodiment of the present invention will be described with reference to the drawings based on the knowledge obtained from the above examples. (Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS.

In FIGS. 1 to 10, SUB1 denotes a transparent insulating substrate on the side where
Represents a thin film transistor which is a switching element of a pixel,
CLA is a common signal wiring having a laminated structure of an Al film or an Al alloy film and a refractory metal film, a refractory metal alloy film, or a refractory metal silicide film, and CEA is amorphous indium zinc oxide, amorphous indium oxide. A common signal electrode made of germanium or an amorphous oxide transparent conductive film containing these as a main component is formed by GEA
GLA is an Al film or an Al alloy film and a refractory metal film, a high-melting metal alloy film, a refractory metal alloy film, or a high-melting metal silicide film. , A scanning signal wiring composed of a laminated structure of an alloy film of a high melting point metal or a silicide film of a high melting point metal, SI is a semiconductor layer, SD is a video signal electrode serving as a source / drain electrode of a thin film transistor,
Is the video signal wiring made of Cr or Cr alloy, PX
A denotes a pixel electrode made of amorphous indium zinc oxide, amorphous indium germanium oxide or an amorphous oxide transparent conductive film containing these as a main component, GI denotes a gate insulating film of the thin film transistor TFT, and PAS denotes a surface protection of the thin film transistor. Membrane, NSI
Denotes an electrode made of a silicon film doped with an impurity such as phosphorus to ensure contact between the source / drain electrode of the thin film transistor and the semiconductor layer, TH denotes a through hole,
BM is a light shielding pattern, CF is a color filter, OC
Denotes an overcoat film, and SUB2 denotes a transparent insulating substrate on the color filter side. Also, ORI1 and ORI are the alignment films, LC
Is a liquid crystal layer, POL1 and POL2 are polarizing plates, GTM is a terminal for scanning signal wiring, DTM is a terminal for video signal wiring, CT
M is a common signal wiring terminal, CB is a common signal wiring bus wiring, SL is a sealing material, TCA is amorphous indium zinc oxide, amorphous indium germanium oxide, or an amorphous oxide transparent containing these as a main component. Scanning signal wiring, common signal wiring,
And a pad electrode of a video signal wiring terminal.

FIG. 1 is a sectional view of an active matrix type liquid crystal display device according to a first embodiment of the present invention, which is a sectional view taken along a line AA 'shown in FIG. FIG. 2 is a front view of a transparent insulating substrate SUB1 on the side where a thin film transistor of a unit pixel is disposed in an active matrix type liquid crystal display device according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of the transparent insulating substrate SUB1 on the side where the thin film transistors are arranged along the line BB 'shown in FIG.

The transparent insulating substrate SUB1 on the side where the thin film transistors are disposed is called a TFT substrate, and the transparent insulating substrate SUB2 on the opposite side that is disposed opposite the TFT substrate via the liquid crystal LC is called a CF substrate.

As shown in FIG. 1, the CF substrate has its liquid crystal layer L
A light-shielding pattern BM is first formed on the surface on the C side so as to define each pixel area, and a color filter CF is formed in an opening that determines a substantial pixel area of the light-shielding pattern BM. Then, an overcoat film OC made of, for example, a resin film is formed to cover the light shielding pattern BM and the color filter CF.
An alignment film ORI2 is formed on the surface of C. TFT
Polarizing plates POL1 and POL2 are formed on outer surfaces of the substrate and the CF substrate (surfaces opposite to the liquid crystal layer LC side).

On the other hand, a common signal electrode CEA comprising a first transparent electrode and a pixel electrode PXA comprising a second transparent electrode are disposed on the TFT substrate side, and an interlayer insulating film between the two transparent electrodes is provided. , A gate insulating film GI, and a surface protective film PAS of the thin film transistor.

In this embodiment, not only the common signal electrode CEA, which is the first transparent conductive film, but also the pixel electrode PXA, which is the second transparent electrode, is made of the amorphous I electrode of the present invention.
The structure was a ZO film.

In this embodiment, as shown in FIG. 2, one thin film transistor TFT, one pixel electrode PXA, and one common signal electrode CEA are formed in a region divided by the scanning signal wiring GLA and the video signal wiring DL. Is composed. The pixel electrode PXA is connected via a through hole TH to one of the video signal electrodes SD serving as the source / drain electrodes of the thin film transistor TFT, and the other of the video signal electrode SD is connected to the video signal wiring DL. Further, the common signal electrode CEA is formed in the entire unit pixel region except at least the periphery of the pixel region. The common signal electrode CEA juxtaposed in the X direction is connected to the scanning signal lines GLA,
It is connected to a common signal line CLA formed of the same process and the same material as the scanning signal electrode GEA. Further, at least a part of the pixel electrode PXA is divided into a plurality of comb-like shapes or processed into a slit shape in the pixel.

In this embodiment, the width of the pixel electrode PXA processed into a slit shape and the width between the electrodes are, for example, 3 μm each.

As shown in FIG. 3, the thin film transistor TFT uses an inverted staggered thin film transistor. When a voltage equal to or higher than the threshold value of the thin film transistor TFT is applied to the gate electrode GEA, the semiconductor layer SI is turned on, and the video signal electrode SD serving as the source / drain electrode of the thin film transistor TFT is turned on. At that time, the video signal wiring DL
Is transmitted to the pixel electrode PXA. When the voltage of the gate electrode GEA is lower than the threshold voltage of the thin film transistor, the thin film transistor TFT
Are insulated between the video signal electrodes SD serving as the source / drain electrodes, the voltage applied to the video signal wiring DL is not transmitted to the pixel electrode, and the pixel electrode PXA is connected to the video signal electrode SD.
Hold the transmitted voltage when is on.

The through hole TH is formed on the surface protection film PAS of the thin film transistor. Through hole TH
Is formed to connect one of the video signal electrodes SD serving as the source / drain electrodes of the thin film transistor to the pixel electrode PXA. , Are electrically connected.

According to this embodiment, the common signal electrode CEA, which is the first transparent electrode, is directly connected over the common signal line CLA, and the common signal electrode CEA is connected to the amorphous indium oxide of the present invention. By using zinc, amorphous indium germanium oxide, or an amorphous oxide transparent conductive film containing these as a main component, in the step of patterning the common signal electrode CEA by etching, the common signal electrode CEA passes over the common signal wiring CLA. Since the pattern can be formed without wedge-shaped electrode thinning at the portion, the common signal electrode CE
The disconnection of A can be reduced, and the yield and reliability can be improved. Also, the common signal electrode line C
Since the end shape of the EA can be ensured to be a forward tapered shape, it is possible to prevent the gate insulating film GI from having a throwing failure at a portion over the common signal wiring CEA,
Thereby, a gate insulating film GI having excellent insulating properties can be formed. Furthermore, since the coverage of the gate insulating film GI can be ensured, the coverage of the surface protection film PAS formed on the gate insulating film GI can be secured, and further, the pixel electrode PXA as the second transparent electrode is formed of a thin film transistor. Disconnection due to poor throwing power at a portion over the step portion of the surface protective film PAS can also be reduced.

According to this embodiment, as the gate insulating film,
In particular, even when the SiN film is used, the common signal electrode CEA is made of the amorphous indium zinc oxide,
Since the gate insulating film GI is composed of amorphous indium germanium oxide or an amorphous oxide transparent conductive film containing these as a main component, a dense gate insulating film GI with no abnormal growth and excellent density is formed on the common signal electrode CEA at a high temperature. be able to. This prevents the lower layer common signal line CLA, common signal electrode CEA, scanning signal line GLA, scanning signal electrode GEA, and video signal line DL from melting when the pixel electrode PXA is processed, and superimposes the pixel electrode PXA and common signal electrode CEA. Short-circuit failure in the region where the light-emitting device is to be operated can be reduced.

According to the present embodiment, the common signal electrode C
By using EA as the amorphous indium zinc oxide, the amorphous indium germanium oxide, or the amorphous oxide transparent conductive film containing these as a main component, the EA can be processed with a weak acid having little damage to the wiring. The scanning signal line GLA and the common signal line CLA existing on the same plane as the signal electrode CEA
However, the pattern of the common signal electrode CEA can be formed without dissolving and disconnecting with an etching solution at the time of processing the common signal electrode CEA.

As described above, since the etching process can be performed without damaging the wiring, an Al or Al alloy film, which is a low-resistance wiring material and has poor chemical resistance to the etching solution for the transparent conductive film, is formed of the common signal electrode CEA. Scanning signal line GLA and common signal line CL located on the same plane as
It is also possible to use it as A. However, Al and A
In the structure in which the l alloy film and the indium oxide-based transparent conductive film as an oxide are in direct contact with each other to form a connection portion, at the interface between Al and the transparent conductive film, oxygen in the transparent conductive film moves to the Al side, It is known that an oxide of aluminum, which is an insulating film, is formed and electrical connection failure is likely to occur. Therefore, the scanning signal wiring GLA and the common signal wiring CLA are actually
When Al or an Al alloy is applied to at least a part of the interface on the side where the Al or Al alloy film forms a contact with the transparent conductive film, a layer for preventing oxygen diffusion, specifically Cr
It is more preferable to form a stacked electrode and wiring structure provided with a layer made of a high melting point metal such as Mo or Mo, an alloy film of the high melting point metal, or a silicide film of the high melting point metal.

In the present embodiment, the amorphous IZO film of the present invention is applied to the pixel electrode PXA as the second transparent electrode located in the upper layer.
Damage to the photoresist film when etching the amorphous transparent conductive film can be similarly reduced as compared with the case where a halogen acid such as hydrochloric acid or hydrobromic acid or a strong acid such as nitric acid is used. Therefore, the patterning accuracy of the transparent conductive film itself can be further improved, and when combined with the effect of uniform etching of the amorphous transparent conductive film itself, fine processing, specifically, comb processing or slit processing of the pixel electrode PXA is performed. Etc. become easier.

Next, the shape of the substrate end portion, the electric circuit, and the shape of the terminal portion connected to the external drive circuit of the liquid crystal display device in this embodiment will be described.

FIG. 4 is a schematic diagram of an electric circuit of an active matrix type liquid crystal display device according to an embodiment of the present invention. 5A and 5B are schematic cross-sectional views of an edge portion of a substrate of an active matrix type liquid crystal display device according to an embodiment of the present invention. FIG.
(B) is a schematic diagram of the end on the side where the liquid crystal sealing port is arranged.

As shown in the electric circuit of FIG. 4, each of the scanning signal wirings GLA extending in the x direction and juxtaposed in the y direction.
Are sequentially supplied with a scanning signal (voltage signal) by a vertical scanning circuit via a scanning signal wiring terminal GTM. The thin film transistor TFT in each pixel region, which is arranged along the scanning signal line GLA, is driven by the scanning signal. In accordance with the timing of the scanning signal, the video signal is supplied from the video signal drive circuit to each video signal wiring DL extending in the y direction and juxtaposed in the x direction via the video signal wiring terminal DTM. Is done.
This video signal is supplied to the thin film transistor TF of each pixel region.
Via T, it is transmitted to the pixel electrode PXA. In each pixel region, a common signal electrode CEA formed together with the pixel electrode PXA is applied with a common voltage branched from the common signal wiring bus wiring CB via a common signal wiring terminal CTM. Electrode PXA and common signal electrode CE
An electric field is generated between A. The light transmittance of the liquid crystal is controlled by an electric field (lateral electric field) having a component which is predominantly parallel to the transparent insulating substrate SUB1 among the electric fields. In the figure, R, R,
The symbols G and B indicate that a red filter, a green filter, and a blue filter are formed in each pixel region.

For fixing the TFT substrate to the CF substrate,
As shown in FIG. 5, sealing is performed by a sealing material SL formed around the CF substrate. The sealing material SL also has a function as an encapsulating material for enclosing liquid crystal between the transparent insulating substrates SUB1 and SUB2. ing. Outside the sealing material SL, around the TFT substrate, and in the area not covered by the CF substrate, the scanning signal wiring terminals GTM,
Video signal wiring terminal DTM, common signal wiring terminal CTM
Are formed. FIG. 5 illustrates the scanning signal wiring GLA terminal GTM among them. Each terminal is, for example, a TCP (Tape Carrier Package) or a COG (Ch) via an anisotropic conductive film in which conductive particles are dispersed in an adhesive.
The connection is made to the external drive circuit described above with reference to FIG. In addition, a part of the sealing material SL has a liquid crystal sealing opening (not shown), and after the liquid crystal is sealed from this opening, sealing is performed by the liquid crystal sealing material.

FIG. 6 is a plan view of a main part of a terminal GTM for a scanning signal line GLA of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG.
1 shows a cross-sectional view along the line indicated by. FIG. 7 is a plan view (a) of a main part of a video signal wiring terminal DTM portion of the active matrix type liquid crystal display device according to the first embodiment,
(B) A cross-sectional view along the line indicated by AA 'is shown.

In the scanning signal wiring terminal GTM portion, as shown in FIG. 6, first, an extended portion of the scanning signal wiring GLA is formed in a region where the scanning signal terminal portion is formed on the transparent insulating substrate SUB1. Further, the gate insulating film GI covering the scanning signal line GLA and the surface protection film P of the thin film transistor TFT
AS are sequentially stacked, and a part of the extended portion of the scanning signal line GLA is exposed by the through holes TH provided in the gate insulating film GI and the surface protective film PAS. The pad electrode TCA is formed on the same material and in the same process as when the pixel electrode PXA is formed thereon, thereby forming the scanning signal wiring terminal GTM. Normally, the terminal exposed portion of the liquid crystal display device is made of a transparent conductive film material having excellent moisture resistance, chemical resistance, and corrosive property, instead of a metal material. Since the outermost surface is made of an amorphous IZO film having excellent moisture resistance, the reliability of the exposed terminal portion can be sufficiently ensured.

In the present embodiment, the scanning signal wiring GLA
And the common signal line CLA are formed of the same material and in the same process. The common signal wiring terminal CTM is also formed of the same material and in the same process as the scanning signal wiring GLA terminal GTM, and thus necessarily has the same configuration. In this case, as shown in FIG. 4, the common signal wiring terminal CTM is drawn out in the direction opposite to the scanning signal wiring terminal GTM.

As shown in FIG. 7, the terminal DTM for video signal wiring first has a gate insulating film G on a transparent insulating substrate SUB1.
After I is formed, an extension of the video signal wiring DL is formed in a region where the video signal wiring terminal DTM is formed.
After that, a through hole TH is formed in a part of a region where a pad electrode TCA is formed in a later step in a region where a surface protection film PAS of the thin film transistor TFT is formed and a terminal DTM for a video signal wiring is formed in a later step. It is opened. Thereafter, the pad electrode TCA is formed in the same process using the material used when forming the pixel electrode PXA, and the terminal DTM for video signal wiring is formed. This pad electrode TC
A is electrically connected to the video signal wiring DL via the through hole TH. With this structure, the video signal wiring terminal DTM, like the scanning signal wiring terminal GTM, has excellent moisture resistance, chemical resistance, and corrosion resistance, and the reliability of the exposed terminal portion can be sufficiently ensured.

Next, in the first embodiment, a specific example of a forming method will be described with reference to FIGS. 8 to 10 by using cross-sectional views of main parts in each manufacturing process of a TFT substrate.

FIG. 8 is a diagram showing a process flow for realizing the configuration of the first embodiment of the present invention. FIG. 9 shows FIG.
When the TFT substrate was manufactured according to the process flow of
FIG. 10 is a cross-sectional view taken along the line AA ′ in FIG. 2. FIG. 10 is a cross-sectional view taken along the line BB ′ in FIG. FIG.

In Example 1, (A) to (A)
(F), through the six-stage photolithography process, TF
The T substrate SUB1 is completed. Hereinafter, description will be made in the order of steps. Step (A) A transparent insulating substrate SUB1 is prepared, and an Al or Al alloy film is formed on the entire surface thereof by, for example, a sputtering method to a thickness of 100 to 500 nm, preferably 150 to 350 n.
m, and a refractory metal film, a refractory metal alloy film, or a refractory metal silicide film thereon for 5 to 200 n.
m, preferably 10 to 100 nm. Next, the Al film,
Selectively etch the refractory metal film collectively in a self-aligned manner,
In the pixel area, the scanning signal electrode GEA and the scanning signal wiring GL are provided.
A and the common signal wiring CLA, and an extension of the scanning signal wiring GLA is formed in the scanning signal wiring terminal GTM formation region. Step (B) An amorphous IZO film serving as a lower first transparent conductive film is formed on the entire surface of the transparent insulating substrate SUB1 by sputtering, for example, to a thickness of 50 to 300 nm, preferably 50 to 300 nm.
It is formed with a thickness of 150 nm. Next, the amorphous IZO film is etched by using the photolithography technique to form a common signal electrode CEA in the pixel region. Step (C) The entire surface of the transparent insulating substrate SUB1 is, for example, plasma CV
By the method D, the silicon nitride film to be the gate insulating film GI is formed to a thickness of about 200 to 700 nm, preferably 300 to 500 nm.
It is formed with a thickness of nm. Further, the gate insulating film GI
An amorphous silicon film is formed on the entire surface by a plasma CVD method, for example, to a thickness of 50 to 300 nm, preferably 1 nm.
An amorphous silicon film having a thickness of 100 to 200 nm and doped with phosphorus as an n-type impurity is 10 to 10 nm.
The layers are sequentially laminated to a thickness of 0 nm, preferably 20 to 60 nm. Next, the amorphous silicon film is etched by using the photolithography technique to form the semiconductor layer SI of the thin film transistor TFT in the pixel region. Step (D) A Cr film or a Cr alloy film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method.
The thickness is set to 500 nm, preferably 150 to 350 nm.
Next, using a photolithography technique, the Cr film is etched, and a video signal electrode SD and a video signal wiring DL serving as a source / drain electrode of the thin film transistor TFT are provided in the pixel region. DT
An extension of the video signal wiring DL is formed in the M formation region. Thereafter, using the pattern obtained by etching the Cr film as a mask, the amorphous silicon film doped with phosphorus as an n-type impurity is etched. Step (E) A silicon nitride film serving as a surface protection film PAS of the thin film transistor TFT is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a plasma CVD method to have a thickness of 200 nm to 900 nm.
m, preferably 300 to 500 nm.
Next, using photolithography technology, the surface protective film P
The AS is etched to form a through hole TH in the pixel region for exposing a part of the source / drain electrode SD of the thin film transistor TFT. At the same time, the scanning signal wiring GLA and the common signal wiring terminals GTM and CTM are formed through the through-holes TH to the gate insulating film GI located below the surface protection film PAS in the region where the terminals GTM and CTM for the common signal wiring are formed. And common signal line CLA terminal G
A through hole TH for exposing a part of the pad electrode TCA of TM and CTM is formed, and a through hole TH for exposing an extended portion of the video signal wiring DL is formed in a video signal wiring terminal DTM formation region. Step (F) An amorphous IZO film serving as an upper second transparent electrode is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method to a thickness of 50 to 300 nm, preferably 50 to 300 nm.
It is formed to a thickness of 50 nm. Next, the amorphous IZO film is etched using a photolithography technique, and a pixel electrode PX connected to a source / drain electrode of the thin film transistor TFT via a through hole TH in the pixel region.
A, and a scanning signal line, a common signal line,
In addition, a pad electrode TCA for connection is formed in a region where the video signal wiring terminals GTM, CTM, and DTM are formed.

By the steps described above, the TFT substrate side is completed.

On the other hand, on the CF substrate side, a color filter CF produced by a dyeing method and a light-shielding pattern BM made of a Cr-based or organic material are formed. Thereafter, an overcoat film serving as a flattening layer is formed, and the TFT substrate and C
A liquid crystal display device is obtained by attaching an F substrate, sealing a liquid crystal layer LC between the substrates, and disposing polarizing plates POL1 and POL2 outside the two substrates. (Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS.

In FIGS. 11 to 17, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description will be omitted.

In FIGS. 11 to 17, PXP denotes a pixel electrode made of a polycrystalline ITO film, and TCP denotes video signal wiring, scanning signal wiring, and common signal wiring terminals DTM,
GTM, CTM pad electrode, CLC is Cr or Cr
Each shows a common signal wiring made of an alloy film.

FIG. 11 is a sectional view of an active matrix type liquid crystal display device according to a second embodiment of the present invention, and is a sectional view taken along the line AA 'shown in FIG. . FIG. 12 is a front view of a transparent insulating substrate SUB1 on the side where a thin film transistor of a unit pixel is arranged in an active matrix type liquid crystal display device according to a second embodiment of the present invention.

In the present embodiment, B-
The cross-sectional view of the transparent insulating substrate SUB1 on the side where the thin film transistor is arranged along the line indicated by B 'is the amorphous indium zinc oxide, the amorphous indium germanium oxide of Example 1, or the oxide transparent conductive film containing these as a main component. Is changed to a pixel electrode PXP made of a polycrystalline ITO film, and the other structure is the same, so that the description is omitted.

In this embodiment, as shown in FIG. 11, a pixel electrode PXP as a second transparent electrode composed of two upper and lower transparent conductive films, and a common signal electrode CE as a first transparent electrode.
The interlayer insulating film between A is a surface protective film P of the thin film transistor.
AS.

In this embodiment, as shown in FIG.
Signal electrode CE which is provided side by side and extends in the X direction
A is the same material as the video signal wiring DL and the video signal electrode SD.
They are connected by a common signal line CLC formed in the same step. In this embodiment, the pixel electrode PXP composed of the second transparent electrode has a configuration using a polycrystalline ITO film.

In this embodiment, the common signal line CLC
A common signal electrode CEA, which is a first transparent electrode, is directly connected over the upper part. The common signal wiring CEA is made of amorphous indium zinc oxide, amorphous indium germanium oxide or amorphous indium germanium oxide of the present invention. By using an amorphous oxide transparent conductive film, a pattern of the common signal electrode CEA can be formed without causing wedge-shaped electrode thinning at a portion over the common signal line CLC, so that disconnection of the common signal line can be reduced. The yield can be improved, and the reliability of the process can be improved. In addition, since the end portion of the common signal electrode CEA can be secured in a forward tapered shape, it is possible to prevent the surface protection film PAS of the thin film transistor from rotating around the portion over the common signal line CEA, and to provide a surface having excellent insulation properties. The protective film PAS can be formed. Further, since the rotation of the surface protective film PAS can be secured, by preventing defects, a portion where the pixel electrode PXP, which is the second transparent electrode formed on the surface protective film PAS, climbs over the step portion of the gate insulating film. Disconnection due to poor throwing power can be prevented.

According to the present embodiment, even when a SiN film is used as the surface protective film of the thin film transistor, the formation temperature at the time of forming the surface protective film PAS can be increased, so that the density without abnormal growth can be improved. And a common signal line CLC, a common signal electrode CEA, and a common signal line CLA when the pixel electrode PXP is formed.
It is possible to prevent the scanning signal electrode GEA, the scanning signal line GLA, and the video signal line DL from melting, and to reduce a short circuit failure in a region where the pixel electrode PXP and the common signal electrode CEA overlap.

According to this embodiment, the patterning of the common signal electrode CEA can be performed with a weak acid which causes little damage to the wiring. Therefore, the scanning signal wiring GLA, common signal wiring CLC, It is possible to prevent the video signal wiring DL from being dissolved and disconnected by being exposed to the etching solution at the time of processing the common signal electrode CEA.

FIG. 13 is a schematic diagram of an electric circuit according to this embodiment. The common signal electrodes CEA extending in the Y direction and provided in the X direction are connected by a common signal line CLC formed of the same process and the same material as the video signal line DL.
The other configuration is the same as that of the first embodiment, and the description is omitted.

FIG. 14 is a plan view of a main part of a scanning signal wiring terminal GTM portion of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG. 2 shows an example of a cross-sectional view along the line A. FIG. 15 is a plan view (a) of a main part of a video signal wiring terminal DTM portion of the active matrix type liquid crystal display device according to the first embodiment,
(B) A cross-sectional view along the line indicated by AA 'is shown.

In the scanning signal wiring terminal GTM, as shown in FIG. 14, first, an extension of the scanning signal wiring GLA is formed in a region on the transparent insulating substrate SUB1 where the scanning signal terminal is formed. A gate insulating film GI and a surface protection film PAS of the thin film transistor TFT are sequentially laminated so as to cover the scanning signal wiring GLA, and a through-hole TH provided in the gate insulating film GI and the surface protection film PAS forms the scanning signal wiring GLA. A part of the extension is exposed. A pad electrode TCP is formed on the same material and in the same process as when the pixel electrode PXP is formed, thereby forming the scanning signal wiring terminal GTM. Normally, the exposed portions of the terminals of the liquid crystal display device are not made of a metal material but made of a transparent conductive film material having excellent moisture resistance, chemical resistance, and corrosiveness. Since the outermost surface is made of a polycrystalline ITO film having excellent moisture resistance, the reliability of the exposed terminal portion can be sufficiently ensured.

As shown in FIG. 15, first, a gate insulating film GI is formed on a transparent insulating substrate SUB1 and then a video signal wiring terminal DTM is formed in a region where a video signal wiring DL terminal is formed. A DL extension is formed. Further, the surface protection film P of the thin film transistor TFT covers the pad electrode TCA and the video signal wiring DL.
AS is formed, and a part of the extending portion of the video signal wiring DL is exposed by the through hole TH provided in the surface protection film PAS. A pad electrode TCP is formed on the pixel electrode PXP.
Are formed in the same process using the same material as that used to form the video signal wiring DL terminal GTM.

Next, in the second embodiment, a specific example of a forming method will be described with reference to FIGS.

FIG. 16 is a diagram showing a process flow for realizing the configuration of the second embodiment of the present invention. FIG. 17 is a sectional view taken along the line AA 'in FIG. 12 when a TFT substrate is manufactured according to the process flow of FIG.

In Example 1, (A) to (A)
(F), through the six-stage photolithography process, TF
The T substrate SUB1 is completed. Hereinafter, description will be made in the order of steps. Step (A) A transparent insulating substrate SUB1 is prepared, and an Al or Al alloy film is formed on the entire surface thereof by, for example, a sputtering method to a thickness of 100 to 500 nm, preferably 150 to 350 n.
m, a high melting point metal, a high melting point metal alloy film, or a high melting point metal silicide film of 5 to 200 nm, preferably 10 to 200 nm.
１００100 nm is continuously formed. Next, using a photolithography technique, the Al or Al alloy film and the high-melting-point metal or the alloy film of the high-melting-point metal are collectively selectively etched in a self-aligned manner, and the scanning signal electrodes GEA, An extended portion of the scanning signal wiring GLA is formed in the scanning signal wiring GLA and in the scanning signal wiring terminal GTM forming region. Step (B) The entire surface of the transparent insulating substrate SUB1 is, for example, plasma CV
By the method D, the silicon nitride film to be the gate insulating film GI is formed to a thickness of about 200 to 700 nm, preferably 300 to 500 nm.
It is formed with a thickness of nm. Further, the gate insulating film GI
An amorphous silicon film is formed on the entire surface by a plasma CVD method, for example, to a thickness of 50 to 300 nm, preferably 1 nm.
An amorphous silicon film having a thickness of 100 to 200 nm and doped with phosphorus as an n-type impurity is 10 to 10 nm.
The layers are sequentially laminated to a thickness of 0 nm, preferably 20 to 60 nm. Next, the amorphous silicon film is etched using photolithography technology to form a semiconductor layer SI of the thin film transistor TFT in the pixel region. Step (C) A Cr or Cr alloy film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method for 100 to 100 μm.
The thickness is set to 500 nm, preferably 150 to 350 nm.
Next, using a photolithography technique, the Cr film is etched, and a video signal electrode SD serving as a source / drain electrode of the thin film transistor TFT, a common signal line CLA, and an extension of the video signal electrode SD are provided in the pixel region. And a video signal wiring terminal DTM.
An extension of the video signal wiring DL is formed in the formation region.
Thereafter, using the pattern obtained by etching the Cr film as a mask, the amorphous silicon film doped with phosphorus as an n-type impurity is etched. Step (D) An amorphous IZO film serving as a lower first transparent electrode is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method to a thickness of 50 to 300 nm, preferably 50 to 300 nm.
It is formed with a thickness of 50 nm. Next, the amorphous IZO film is etched using photolithography technology,
The common signal electrode CEA is formed in the pixel area. Step (E) A silicon nitride film serving as a surface protection film PAS of the thin film transistor TFT is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a plasma CVD method to have a thickness of 200 nm to 900 nm.
m, preferably 300 to 500 nm.
Next, using photolithography technology, the surface protective film P
The AS is etched to form a through hole TH in the pixel region for exposing a part of the source / drain electrode SD of the thin film transistor TFT. At the same time, in the scanning signal wiring terminal GTM formation region, a part of the extended portion of the scanning signal wiring GLA is penetrated through the through hole TH to the gate insulating film GI located under the surface protection film PAS. Is formed, and a through hole TH for exposing a part of the extension of the video signal wiring and the common signal wiring is formed. Step (F) The entire surface of the transparent insulating substrate SUB1 is subjected to, for example, a sputtering method to form a polycrystalline I to be an upper second transparent electrode.
The TO film has a thickness of 50 to 300 nm, preferably 50 to 200 n.
m. Next, using photolithography technology,
The polycrystalline ITO film is etched to form a pixel electrode PXP connected to the source / drain electrode SD of the thin film transistor TFT via a through hole TH in the pixel region, and to form a scanning signal line, a common signal line, and an image. A connection pad electrode TCP is formed in the signal wiring terminal GTM, CTM, DTM formation region.

Through the steps described above, the TFT substrate side is completed. (Embodiment 3) A third embodiment of the present invention will be described with reference to FIGS.

In FIGS. 18 to 23, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description will be omitted. AO is an insulating film made of Al oxide formed on Al or an Al alloy used for the scanning signal wiring GLA, the common signal wiring CLA, and the scanning signal electrode GEA, and TCC is an alloy of a high melting point metal and a high melting point metal. A pad electrode made of a film or a silicide film of a high melting point metal. As a mutual diffusion preventing layer for compensating electrical contact between a wiring made of an Al or Al alloy film and a transparent electrode made of an oxide transparent conductive film. Function.

FIG. 18 is a sectional view of an active matrix type liquid crystal display device according to a first embodiment of the present invention, and is a sectional view taken along a line AA 'shown in FIG. 19 described later. . FIG. 20 is a surface view of the transparent insulating substrate SUB1 on the side where the thin film transistor of the unit pixel is arranged in the active matrix type liquid crystal display device according to the first embodiment of the present invention. FIG. 20 is a cross-sectional view of the transparent insulating substrate SUB1 on the side where the thin film transistors are arranged along the line BB 'shown in FIG.

In the third embodiment, as shown in FIG. 18, the interlayer insulating film between the pixel electrode PXA and the common signal electrode CEA made of upper and lower transparent conductive layers is a gate insulating film G.
I, composed of two layers of a surface protection film PAS of a thin film transistor. The Al oxide AO is formed at least in a part other than a region where the common signal electrode CEA and the common signal wiring CLA are connected via the pad electrode TCC, and the gate insulating film G
It has a function as an insulating film together with I.

In this embodiment, the common signal line C
LA and the common signal electrode CEA are connected via a through hole opened in the Al oxide AO, but the common signal line CLA and the common signal electrode CE
A, a high melting point metal such as Cr which becomes an oxygen diffusion preventing layer
A pad electrode TC made of a refractory metal alloy film or a refractory metal silicide film is arranged.
It is connected via C.

In the present embodiment, as in the first embodiment, both the common signal electrode CEA as the first transparent electrode and the second transparent electrode PXA are formed as the amorphous IZO film of the present invention. Further, the common signal wiring CLA was formed in the same process and with the same material as the scanning signal wiring GLA and the scanning signal electrode GEA.

In this embodiment, the same effects as in the first embodiment can be obtained by applying the amorphous indium zinc oxide, the amorphous indium germanium oxide, or the oxide transparent conductive film containing these as a main component. Is obtained. In the step of patterning the common signal electrode CEA, it is possible to prevent wedge-shaped electrode thinning at a portion over the Al oxide AO. Disconnection of the common signal line CLA made of an Al film or an Al alloy film can be reduced, and yield and process reliability can be improved. In addition, since the end portion of the common signal electrode CEA can be ensured to have a forward tapered shape, it is possible to prevent the gate insulating film GI and the surface protection film PAS of the thin film transistor from having poor rotation around the portion over the common signal line CEA. Thus, a gate insulating film GI having excellent insulating properties and a surface protective film PAS of a thin film transistor can be formed. Furthermore, since the surroundings of the thin film transistor protective film PAS can be secured,
It is possible to prevent disconnection at a portion where the pixel electrode PXA, which is the second transparent electrode formed on the surface protection film PAS of the thin film transistor, crosses a step portion of the surface protection film PAS.

In this embodiment, as shown in FIG. 20, the thin film transistor TFT has a laminated structure of an Al oxide and a gate insulating film GI as an insulating film of the gate electrode GEA. Thus, a gate insulating film having excellent insulating properties can be formed. The other configuration is the same as that of the first embodiment, and the description is omitted.

Next, in the third embodiment, a specific example of a forming method will be described with reference to cross-sectional views of a main part in each manufacturing process of the TFT substrate shown in FIGS.

FIG. 21 is a diagram showing a process flow for realizing the configuration of the third embodiment of the present invention. FIG.
23 and FIG. 23 respectively show A in FIG. 19 when a TFT substrate is manufactured in accordance with the process flow of FIG.
It is sectional drawing which follows the line shown by -A ', and is sectional drawing which follows the line shown by BB'. In the third embodiment, the TFT substrate SUB1 is completed through eight stages of photolithography steps (A) to (H). Hereinafter, description will be made in the order of steps. Step (A) A transparent insulating substrate SUB1 is prepared, and an Al or Al alloy film is formed to a thickness of 100 to 500 nm, preferably 150 to 350 nm over the entire surface by, for example, a sputtering method.
It is formed with a film thickness of. Next, using a photolithography technique, the Al alloy film is etched, and the scanning signal electrode GEA, the scanning signal wiring GLA, and the common signal wiring CLA are formed in the pixel region, and the scanning signal wiring terminal GTM is formed in the pixel signal region. Forms an extension of the scanning signal line GLA. Step (B) Using photolithography technology, a region other than the region where an Al oxide is formed, specifically, a scanning signal line GLA, a terminal forming region for a common signal line CLA, and a common signal line GLA and a common signal electrode CLA A resist pattern is formed at the connection part of. Thereafter, the transparent insulating substrate SUB1 and the platinum electrode are immersed in an anodic oxidizing solution containing tartaric acid as a main component and having a pH adjusted to near neutrality, and a voltage is applied between the transparent insulating substrate SUB1 and the platinum electrode to form Al or An Al oxide AO is formed by anodizing the surface of the Al alloy film. Step (C) A high-melting-point metal, a high-melting-point metal alloy film, or a high-melting-point metal silicide film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method.
nm, preferably 10 to 100 nm.
Next, using photolithography technology, at least A
(1) Etching is performed so as to leave a Cr alloy film in a part of the region where the oxide is not formed.
And pad electrode TCC in the common signal wiring terminal formation area.
To form Step (D) An amorphous IZO film serving as a lower first transparent electrode is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method to a thickness of 50 to 300 nm, preferably 50 to 300 nm.
It is formed with a thickness of 50 nm. Next, the amorphous IZO film is etched using photolithography technology,
The common signal electrode CEA is formed in the pixel area. Step (E) The entire surface of the transparent insulating substrate SUB1 is, for example, plasma CV
By the method D, the silicon nitride film to be the gate insulating film GI is formed to a thickness of about 200 to 700 nm, preferably 300 to 500 nm.
It is formed with a thickness of nm. Further, the gate insulating film GI
An amorphous silicon film is formed on the entire surface by a plasma CVD method, for example, to a thickness of 50 to 300 nm, preferably 1 nm.
An amorphous silicon film having a thickness of 100 to 200 nm and doped with phosphorus as an n-type impurity is 10 to 10 nm.
The layers are sequentially laminated to a thickness of 0 nm, preferably 20 to 60 nm. Next, the amorphous silicon film is etched using photolithography technology to form a semiconductor layer SI of the thin film transistor TFT in the pixel region. Step (F) A Cr or Cr alloy film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method.
The thickness is set to 500 nm, preferably 150 to 350 nm.
Next, using a photolithography technique, the Cr film is etched, and in the pixel region, a video signal electrode SD serving as a source / drain electrode of the thin film transistor TFT and a video signal wiring which is an extension of the video signal electrode SD are provided. The extension portion of the video signal wiring DL is formed in the area for forming the video signal wiring terminal DTM. Thereafter, using the pattern obtained by etching the Cr film as a mask, the amorphous silicon film doped with phosphorus as an n-type impurity is etched. Step (G) A silicon nitride film serving as a surface protective film PAS of the thin film transistor TFT is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a plasma CVD method to a thickness of 200 nm to 900 nm.
m, preferably 300 to 500 nm.
Next, using photolithography technology, the surface protective film P
The AS is etched to form a through hole TH in the pixel region to expose a part of the drain electrode of the thin film transistor TFT. At the same time, in the scanning signal wiring terminal GTM formation region, through the through hole TH to the gate insulating film GI located under the surface protection film PAS, the pad electrode T for the scanning signal wiring terminal GTM is formed.
A through hole TH for exposing a part of CA1;
The video signal wiring D is formed in the video signal wiring terminal DTM formation area.
A through hole TH for exposing the extending portion of L is formed. Step (H) An amorphous IZO film serving as an upper second transparent electrode is formed on the entire surface of the transparent insulating substrate SUB1 by sputtering, for example, to a thickness of 50 to 300 nm, preferably 50 to 1 nm.
It is formed to a thickness of 50 nm. Next, the amorphous IZO film is etched using the photolithography technique, and a pixel electrode PXA connected to the drain electrode of the thin film transistor TFT is formed in the pixel region via the through hole TH.

By the steps described above, the TFT substrate side is completed. (Embodiment 4) A fourth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description will be omitted.

In this embodiment, a sectional view of the active matrix type liquid crystal display device, a surface view of the transparent insulating substrate SUB1 on the side where the thin film transistor of the unit pixel of the active matrix type liquid crystal display device is arranged, a sectional view of the thin film transistor, Since the process flow for realizing the shape of the end, the electric circuit, and the configuration is the same as that of the first embodiment, the description is omitted.

FIG. 24 is a plan view of a main part of a scanning signal wiring terminal GTM portion of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG. FIG. FIGS. 25A and 25B are a main part plan view of a video signal wiring terminal DTM portion of the active matrix type liquid crystal display device according to the first embodiment, and FIGS.
FIG. 4 shows a cross-sectional view along the line indicated by −A ′.

The terminal GTM for the scanning signal wiring is shown in FIG.
As shown in (1), first, an extension of the scanning signal wiring GLA is formed in a region on the transparent insulating substrate SUB1 where a scanning signal terminal portion is formed. A gate insulating film GI and a surface protection film PAS of the thin film transistor TFT are sequentially laminated so as to cover the scanning signal wiring GLA.
In addition, a part of the extending portion of the scanning signal wiring GLA is exposed by the through hole TH provided in the surface protection film PAS to form the scanning signal wiring terminal GTM.

As shown in FIG. 25, after the gate insulating film GI is formed on the transparent insulating substrate SUB1, the video signal wiring terminal DTM is formed in the region where the video signal wiring terminal is formed. A DL extension is formed.
Further, the thin film transistor T covers the video signal line DL.
FT surface protective film PAS is sequentially laminated, and the surface protective film P
The extension of the video signal wiring DL is exposed by the through hole TH provided in the AS, and the video signal wiring terminal DT
M is formed.

In this embodiment, the surface of the exposed portion of the scanning signal wiring terminal GTM and the video signal wiring terminal DTM is not covered and protected by the transparent conductive oxide film. (Embodiment 5) A fifth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and duplicate description will be omitted.

In the fifth embodiment, TCAP is a pad electrode made of a polycrystalline transparent conductive film formed by selectively crystallizing a part of a pad electrode made of an amorphous IZO film of the present invention by laser annealing or the like.

FIG. 26 shows a scanning signal line GLA of an active matrix type liquid crystal display device according to an embodiment of the present invention.
(A) and (b) A-
FIG. 4 shows a cross-sectional view along the line indicated by A ′. FIG. 27 is a plan view of a main part of a video signal wiring terminal DTM portion of the active matrix type liquid crystal display device according to the first embodiment (a).
And (b) a cross-sectional view along the line indicated by AA '.

The scanning signal wiring terminal GTM is shown in FIG.
As shown in (1), first, an extension of the scanning signal wiring GLA is formed in a region on the transparent insulating substrate SUB1 where a scanning signal terminal portion is formed. A gate insulating film GI and a surface protection film PAS of the thin film transistor TFT are sequentially laminated so as to cover the scanning signal wiring GLA, and a through-hole TH provided in the gate insulating film GI and the surface protection film PAS forms the scanning signal wiring GLA. A part of the extension is exposed. On top of this, the pad electrode TCAP is provided with the amorphous I of the present invention.
When the pixel electrode PXA, which is the second transparent electrode made of a ZO film, is formed, the same material and the same process are used. Then, the TCAP of the pad electrode formed in the scanning signal wiring GLA terminal GTM portion is crystallized by local annealing such as laser annealing, lamp annealing, and electron beam annealing to form a polycrystalline IZO film, and the scanning signal wiring GLA terminal G
A TM is formed. It is more desirable that the exposed portions of the terminals of the liquid crystal display device be made of a transparent conductive film material having excellent moisture resistance, chemical resistance, and corrosiveness, rather than a metal material. Since the outermost surface of GTM is composed of a polycrystalline IZO film with excellent moisture resistance,
The reliability of the exposed terminal portion can be sufficiently ensured.

The terminal DTM for video signal wiring is shown in FIG.
As shown in (1), first, after the gate insulating film GI is formed on the transparent insulating substrate SUB1, the extension of the video signal wiring DL is formed in a region where the video signal wiring terminal is formed. Further, the surface protection film PAS of the thin film transistor TFT is sequentially laminated so as to cover the video signal wiring DL, and the extending portion of the video signal wiring DL is exposed by the through hole TH provided in the surface protection film PAS. The pad electrode T
The CAP is formed in the same material and in the same process as when the pixel electrode PXA as the second transparent electrode made of the amorphous IZO film of the present invention is formed. This pad electrode TCAP
The pad electrode T formed on the scanning signal wiring terminal GTM
It is selectively crystallized and polycrystallized in the same step as CAP.

In the fifth embodiment, as shown in FIG. 28, more specifically, after a six-stage photolithography process of (A) to (F) and a selective crystallization process of the amorphous IZO film, T
The FT substrate SUB1 is completed. This step is a step in which the step of selective crystallization of the pad electrode pattern made of the amorphous IZO film of the present invention is added to the end of the step of the second embodiment, so that detailed description is omitted. (Embodiment 6) A sixth embodiment to which the coating type insulating film of the present invention is applied will be described with reference to FIGS.

In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description will be omitted.

In FIGS. 29 to 36, OIL is an interlayer insulating film made of the coating type insulating film of the present invention.

FIG. 29 is a cross-sectional view of an active matrix type liquid crystal display device according to a first embodiment of the present invention, and is a cross-sectional view taken along a line AA 'shown in FIG. 30 described later. . FIG. 30 is a front view of the transparent insulating substrate SUB1 on the side on which the thin film transistor of the unit pixel is arranged in the active matrix type liquid crystal display device according to the first embodiment of the present invention, and FIG. Transparent insulating substrate S on the side where thin film transistors are arranged along the line indicated by -B '
FIG. 4 shows a cross-sectional view of UB1.

In the sixth embodiment, the interlayer insulating film between the pixel electrode PXA and the common signal electrode CEA, which are composed of two layers of transparent conductive films, is composed of a gate insulating film GI and a surface protective film PAS of a thin film transistor. And an application-type insulating film OIL.

According to the present embodiment, by disposing the coating type insulating film OIL between the two transparent conductive films, it is possible to further improve the structure of the gate insulating film GI and the surface protective film PAS of the thin film transistor. The reliability of the interlayer insulating film can be improved. When the second transparent electrode in the upper layer is made of a polycrystalline ITO film and the pixel electrode PXP formed of the second transparent electrode is formed by etching, the dissolution of the common signal wiring CLA, the common signal electrode CEA, and the video signal wiring DL is also performed. The effect of prevention can be further enhanced. Further, it is more effective when an Al or Al alloy film is used as the electrode wiring material.

Further, according to the present embodiment, by disposing the coating type insulating film OIL between the two transparent conductive films, the step formed by the pattern disposed below the coating type insulating film OIL can be reduced. Then, the coating type insulating film OIL is flattened. By the planarization, the step over which the pixel electrode PXP arranged in the upper layer can get over can be reduced, so that the disconnection of the pixel electrode PXP at the step over the step can be prevented.

As shown in FIG. 32, through holes TH are formed so as to open over the surface protection film PAS of the thin film transistor and the coating type insulating film OIL. Pixel electrode
PXA goes over the step of the through hole TH and becomes the video signal electrode SD which becomes the source / drain electrode of the thin film transistor.
And is electrically connected.

In the present embodiment, as shown in FIG. 30, the common signal electrode CEA is also processed into a slit like the pixel electrode PXA. The pattern of the common signal electrode CEA is alternately arranged with the insulating film interposed therebetween so as to be located in the gap of the slit portion of the pixel electrode PXA, and the common signal line CEA and the pixel electrode PXP partially overlap each other. To form a capacitor. The slit-shaped electrode width and the interelectrode width of the common signal electrode CEA and the pixel electrode PXP were, for example, each 3 μm.

With the configuration of this embodiment, the parasitic capacitance between the common signal electrode CEA and the pixel electrode PXP can be reduced, and the signal delay due to the parasitic capacitance can be reduced.

In this embodiment, the electric circuit and the TF
Since the fixing of the T substrate to the CF is the same as that in the first embodiment, the description is omitted.

FIGS. 35 (a) and 35 (b) are main part plan views of a scanning signal line GL terminal GTM portion of an active matrix type liquid crystal display device according to an embodiment of the present invention, and FIG. 35 (b) AA '.
1 shows a cross-sectional view along the line indicated by. FIG. 36 is a plan view (a) of a main portion of a video signal wiring terminal DTM portion of an active matrix liquid crystal display device according to a sixth embodiment;
(B) A cross-sectional view along the line indicated by AA 'is shown.

As shown in FIG. 32, the scanning signal wiring terminal GTM portion is first provided in the area where the scanning signal terminal portion is formed on the transparent insulating substrate SUB1 with the extending portion of the scanning signal wiring GLA and the connection pad electrode. TCA is formed. The connection pad electrode TCA is formed of the same material and in the same process as when the common signal electrode CEA is formed. Pad electrode T
The CA is formed at the end of the scanning signal line GLA so as to cover the scanning signal line GLA. further,
A gate insulating film GI and a surface protection film PAS of the thin film transistor TFT are sequentially laminated so as to cover the pad electrode TCA and the scanning signal wiring GLA, and a through hole TH provided in the gate insulating film GI and the surface protection film PAS.
Thereby, a part of the pad electrode TCA is exposed. Thereafter, a coating type insulating film OIL is formed thereon, and a part of the pad electrode TCA is exposed by a through hole provided in the coating type insulating film OIL. On top of that, the pad electrode TC
P is formed of the same material and in the same process as when the pixel electrode PXP was formed, and forms the scanning signal wiring terminal GTM. Also in this embodiment, since the outermost surface of the scanning signal wiring terminal GTM is formed of an amorphous IZO film having excellent moisture resistance, the reliability of the exposed terminal portion can be sufficiently ensured. When the through hole TH is opened, a dry etching method using a fluorine-based etching gas is used. However, the through-hole opening is formed of an amorphous IZO film having excellent etching resistance to the fluorine-based etching gas. Since they are arranged, the reliability in the process of opening the through holes can be sufficiently ensured.

As shown in FIG. 33, first, a gate insulating film GI is formed on a transparent insulating substrate SUB1, and then a video signal wiring terminal DTM is formed in a region where a video signal wiring terminal is formed. A DL extension is formed.
Thereafter, a through-hole TH is formed in a part of a region where a pad electrode TCP is formed in a later step, in a region where a surface protection film PAS of the thin film transistor TFT is formed and a terminal DTM for a video signal wiring is formed. It is opened. A coating type insulating film OIL is formed on the surface protective film PAS of the thin film transistor, and a pad electrode T formed in a later step in a region where the video signal wiring terminal DTM is formed.
A through hole TH is opened in a part of the region where the CP is formed.

Further, the pad electrode TC is formed in the same step by using the material used for forming the above-described pixel electrode PXP.
P is formed. This pad electrode TCP is electrically connected to video signal wiring DL via through hole TH. By adopting this structure, the terminal DTM for the video signal wiring also has moisture resistance,
Since it is made of a transparent conductive film material having excellent chemical resistance and corrosiveness, the reliability of the exposed terminal portion can be sufficiently ensured.

Next, in the sixth embodiment, a specific example of a forming method will be described with reference to FIGS. 34 to 36, using cross-sectional views of relevant parts in each manufacturing process of a TFT substrate.

FIG. 34 is a diagram showing a process flow for realizing the configuration of the sixth embodiment of the present invention. FIG. 35 is a cross-sectional view taken along the line AA 'in FIG. 30 when a TFT substrate is manufactured according to the process flow of FIG. 34. FIG. 36 is a cross-sectional view of the TFT according to the process flow of FIG. B- in FIG. 30 when the substrate was manufactured.
It is sectional drawing which follows the line shown by B '.

In Example 6, specifically, (A) to
(G) through the seven-stage photolithography process
The T substrate SUB1 is completed. Hereinafter, description will be made in the order of steps. Step (A) A transparent insulating substrate SUB1 is prepared, and an Al or Al alloy film is formed on the entire surface thereof by, for example, a sputtering method to a thickness of 100 to 500 nm, preferably 150 to 350 n.
m, a high melting point metal or an alloy film of a high melting point metal
00 nm, preferably 10 to 100 nm is continuously formed. Next, using photolithography technology, the Al,
Alternatively, the Al alloy film and the high melting point metal or the alloy film of the high melting point metal are collectively selectively etched in a self-aligned manner, and the scanning signal electrode GE, the wiring GLA, and the common signal wiring CLA are provided in the pixel region. Terminal G for scanning signal wiring
An extension of the scanning signal wiring GLA is formed in the TM formation region. Step (B) An amorphous IZO film serving as a lower transparent conductive film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method to have a thickness of 50 to 300 nm, preferably 50 to 150 nm.
It is formed with a thickness of nm. Next, using a photolithography technique, the amorphous IZO film is etched, and a slit-shaped common signal electrode CEA is formed in the pixel region.
Further, in the scanning signal wiring terminal GTM forming region and the common signal wiring terminal CTM forming region, pad electrodes TCA for the scanning signal wiring terminal GTM and the common signal wiring terminal CTM are formed, respectively. Step (C) The entire surface of the transparent insulating substrate SUB1 is, for example, plasma CV
By the method D, the silicon nitride film to be the gate insulating film GI is formed to a thickness of about 200 to 700 nm, preferably 300 to 500 nm.
It is formed with a thickness of nm. Further, the gate insulating film GI
An amorphous silicon film is formed on the entire surface by a plasma CVD method, for example, to a thickness of 50 to 300 nm, preferably 1 nm.
An amorphous silicon film having a thickness of 100 to 200 nm and doped with phosphorus as an n-type impurity is 10 to 10 nm.
The layers are sequentially laminated to a thickness of 0 nm, preferably 20 to 60 nm. Next, the amorphous silicon film is etched by using the photolithography technique to form the semiconductor layer SI of the thin film transistor TFT in the pixel region. Step (D) A Cr film is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a sputtering method to have a thickness of 100 to 500 nm, preferably 150 to 350 nm. Next, using a photolithography technique, the Cr film is etched, and in the pixel region, a video signal electrode SD serving as a source / drain electrode of the thin film transistor TFT and a video signal wiring DL serving as an extension of the video signal electrode SD. Further, in the region for forming the video signal wiring terminal DTM, an extension of the video signal wiring DL is formed. Thereafter, using the pattern obtained by etching the Cr film as a mask, the amorphous silicon film doped with phosphorus as an n-type impurity is etched. Step (E) A silicon nitride film serving as a surface protection film PAS of the thin film transistor TFT is formed on the entire surface of the transparent insulating substrate SUB1 by, for example, a plasma CVD method to have a thickness of 200 nm to 900 nm.
m, preferably 300 to 500 nm.
Next, using photolithography technology, the surface protective film P
The AS is etched to form a through hole TH in the pixel region to expose a part of the drain electrode of the thin film transistor TFT. Along with this, scanning signal wiring,
In the region where the common signal wiring terminals GTM and CTM are formed, the scanning signal wiring and the common signal wiring terminals GTM and CTM are pierced through the through holes TH to the gate insulating film GI located below the surface protective film PAS. A through hole TH for exposing a part of the pad electrode TCA for CTM is provided.
The video signal wiring D is formed in the video signal wiring terminal DTM formation area.
A through hole TH for exposing the extending portion of L is formed. Step (F) A polyimide-based polymer, an acrylic-based polymer,
Various organic resins, such as epoxy polymers and benzylcyclobutene polymers, or Si soluble in organic solvents
Is formed with a thickness of 200 nm to 4 μm, preferably 200 nm to 1.5 μm, which is an inorganic polymer containing, for example, an insulating film such as an SOG film. Next, using photolithography technology, scan signal wiring,
Common signal wiring and video signal wiring terminals GTM, C
Through holes TH are opened in the TM, DTM, and a portion connecting the pixel electrode PXP and the source / drain electrode SD. Step (G) Over the entire surface of the transparent insulating substrate SUB1, for example, by a sputtering method, a polycrystalline ITO to become an upper transparent conductive film
The film is formed to have a thickness of 50 to 300 nm, preferably 50 to 150 nm. Next, using a photolithography technique, the polycrystalline ITO film is etched, and a pixel electrode PXP connected to the drain electrode of the thin film transistor TFT is formed in the pixel region via a through hole TH.
A connection pad electrode TCP is formed in the scanning signal wiring terminal GTM formation region, and a connection pad electrode TCA is formed in the video signal wiring terminal DTM formation region.

By the steps described above, the TFT substrate side is completed.

In this embodiment, as the coating type insulating film, various organic resins such as polyimide, acrylic polymer, epoxy polymer, and benzylcyclobutene polymer, or organic solvents can be used, for example, by spin coating. Inorganic polymer containing soluble Si, such as SO
Although the G film and the like were used, the above-described effects were obtained in all cases.

In this embodiment, the through hole TH of the coating type insulating film, the gate insulating film GI, and the protective film PAS was formed by using another photolithography process. Using the through hole pattern of the coating type insulating film as a mask, the gate insulating film G
I. The through holes of the protective film PAS may be formed in a self-aligned manner. In this case, the gate insulating film GI and the protective film PAS
The photolithography step for forming the through hole can be omitted, and the process can be simplified. (Embodiment 7) A seventh embodiment of the present invention will be described with reference to FIG.

In this embodiment, the same components and materials as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment shows an embodiment in which a bent portion is provided in the pixel electrode PXA of the first embodiment. In this embodiment, the first embodiment described above is applied to a so-called multi-domain liquid crystal display device. Here, the multi-domain method means that, in an electric field (lateral electric field) generated in the spreading direction of the liquid crystal, regions having different directions of the horizontal electric field are formed in each pixel region, and the twist direction of the liquid crystal molecules in each region is changed. By reversing (LC1, LC2 in FIG. 37), for example, the coloring difference that occurs when the display area is viewed from the left and right,
The effect of canceling out is given. More specifically, in FIG. 37, each of the strip-shaped pixel electrodes PXA extending in one direction and juxtaposed in a direction intersecting the one direction is connected to the one direction at an angle θ (a P-type liquid crystal and an alignment film ORI1). When the rubbing direction is positioned as the direction of the video signal wiring DL, 5 to 4
After being extended at an angle of 0 °, the angle (−
2θ) to form a zigzag shape by repeatedly bending and extending the pixel electrode PXA having the above-described configuration on the common signal electrode CEA in an upper layer via an insulating film. The effects of the multi-domain system described above can be obtained. And, in particular, the pixel electrode PX
It is confirmed that the electric field generated between the common signal electrode CEA in the vicinity of the bent portion of A and the electric field generated between the common signal electrode CEA in other portions of the pixel electrode PXA are generated exactly in the same manner. And the pixel electrode PXA
In the vicinity of the bent portion, there is an effect that a problem such as a decrease in light transmittance does not occur. (Conventionally, this is called a so-called disclination region, in which the direction of twist of liquid crystal molecules is random and an opaque portion is generated.)
In the present embodiment, the pixel electrode PXA is
Although it is formed so as to extend in the y direction in the figure, it may be arranged so as to extend in the x direction in the figure and provided with a bent portion to obtain a multi-domain effect.

It is needless to say that the desired effects described above can be obtained by applying the transparent electrode structure of the present invention to such a multi-domain system.

In all of the above-described embodiments, an example was described in which an amorphous IZO film was used as a transparent electrode constituting material of the present invention. Instead of the amorphous IZO film, an amorphous indium germanium oxide or an amorphous IZO film Needless to say, the same effect can be obtained with an amorphous oxide transparent conductive film containing amorphous indium germanium oxide as a main component.

The Al alloy films described in Examples 1 to 7 are different from Al in that Si, Cu, Ti, Ta, Mo, C
r, Ni, Y, La, Nd, Gd, Tb, Pd, Zr,
It is a metal film containing at least one of W and Dy.

The refractory metal films described in Examples 1 to 7 are made of Ti, V, Cr, Zr, Nb, Mo, Hf, T
In either a or W, the refractory metal alloy film is an alloy film composed of a combination of the refractory metal films, and the refractory metal silicide film is an intermetallic compound of the refractory metal film and Si. is there.

An Al or Al alloy film and a high-melting-point metal film, an alloy film of a high-melting-point metal described in the first to seventh embodiments,
Alternatively, instead of an electrode composed of a laminated film composed of a refractory metal silicide film or a wiring, a single layer film composed of a refractory metal film, a refractory metal alloy film, or a refractory metal silicide film, or A similar effect can be obtained by using a laminated film of the above.

Although Cr is used as an example of the video signal wiring DL and the common signal wiring CLC described in the first to seventh embodiments, other than Cr, for example, a sputtering or vapor deposition method may be used. Ti, V, Cr,
Refractory metals such as Zr, Nb, Mo, Hf, Ta, or W, alloy films thereof, or refractory metal silicide films thereof, or Al, Al alloy which is a low-resistance wiring material, or a laminated film made of these materials It may be composed of

In all of the above embodiments, examples in which the structure of the transparent conductive film of the present invention is applied to a liquid crystal display device using an inverted staggered TFT as a switching element have been described. However, the present invention is not limited to this. However, the present invention is also applicable to a case where a TFT having a different structure such as a positive stagger type TFT or a coplanar type TFT is used.

In all of the above embodiments, the role of the upper and lower two-layered transparent electrodes is shown only in each case in each embodiment, but one is a common signal electrode, the other is a pixel electrode, and the common signal electrode is used. If the transparent electrode disposed in the lower layer of the electrode and the pixel electrode is the amorphous indium zinc oxide, the amorphous indium germanium oxide, or the amorphous oxide transparent conductive film containing these as main components, the present invention It goes without saying that the effect of does not change.

In all of the above embodiments, the material of the transparent electrode disposed on the upper layer is not particularly limited. For example, it may be made of the same material as the amorphous indium zinc oxide, indium germanium oxide, or an oxide transparent conductive film containing these as a main component, or may be made of a polycrystalline ITO film, which is disposed in a lower layer. You may. In that case,
As described in the above embodiments, the effects associated with each of them can be obtained.

In all the above embodiments, an amorphous silicon film is used as a silicon film constituting an electrode NSI made of a semiconductor and a silicon film doped with impurities. For example, the amorphous silicon film is heat-treated or laser-processed. A polycrystalline silicon film crystallized by annealing may be used.

In all of the above embodiments, the gate insulating film and the protective insulating film use a silicon nitride film formed by, for example, a plasma CVD method or a sputtering method. It may be composed of a film.

In all of the above embodiments, the common signal wiring is formed of the same material and in the same process as either the scanning signal wiring or the video signal wiring, but a process for forming only the common signal wiring is newly added. May be added.

In the application example of the coating type insulating film shown in the sixth embodiment, the effects of the present invention can be obtained by applying the coating type insulating film in the first to fifth and seventh embodiments. Needless to say.

Even when the comb-shaped or slit-shaped processed shape of the common signal electrode shown in the sixth embodiment is applied to the first to fifth and seventh embodiments, the effect of the present invention can be obtained. Needless to say.

As an application example of the multi-domain system shown in the seventh embodiment, a configuration in which a bent portion is provided in an upper transparent electrode is shown by taking the configuration of the first embodiment as an example, but in the second to sixth embodiments as well. Similarly, by providing a bent portion in the upper transparent electrode, it goes without saying that a multi-domain effect is imparted in addition to the effects of the transparent electrode configuration of the present invention described above.

According to the structure of this embodiment, (1) the reliability of the insulating film on the first transparent electrode disposed in the lower layer is improved (2) the disconnection of the second transparent electrode disposed in the upper layer is reduced ( 3) Wiring that is disposed on the same plane as the first transparent electrode disposed in the lower layer without interposing an insulating film and is directly connected to the first transparent electrode, and prevents the electrode from melting. (4) Connection in the above (3) It is possible to reduce the disconnection of the first transparent electrode when overcoming the step formed in the portion.

[0154]

As described above, a high-performance liquid crystal display device having a high transmittance can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an active matrix type liquid crystal display device according to a first embodiment of the present invention, and is a cross-sectional view taken along a line AA ′ shown in FIG.

FIG. 2 is a surface view of a transparent insulating substrate on the side where a thin film transistor of a unit pixel is arranged in the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the transparent insulating substrate side on the side where the thin film transistors are arranged, taken along line BB ′ shown in FIG. 2;

FIG. 4 is a schematic diagram showing an electric circuit of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of an edge portion of a substrate of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 6 is a plan view (a) of a main part of a scanning signal wiring terminal GTM portion of an active matrix type liquid crystal display device according to an embodiment of the present invention, and (b) is along a line indicated by AA '. Sectional view.

FIGS. 7A and 7B are a main part plan view of a video signal wiring terminal DTM portion of the active matrix type liquid crystal display device according to the first embodiment, and FIG. 7B is a cross-sectional view taken along line AA ′. FIG.

FIG. 8 is a view showing a process flow for realizing the configuration of the first embodiment of the present invention.

9 is a cross-sectional view taken along the line AA 'in FIG. 2 when a TFT substrate is manufactured according to the process flow of FIG.

FIG. 10 is a sectional view taken along the line BB 'in FIG. 2 when a TFT substrate is manufactured according to the process flow of FIG.

FIG. 11 is a cross-sectional view showing a second embodiment of the present invention, and is a cross-sectional view including a counter substrate taken along a line AA ′ shown in FIG. 12 described later.

FIG. 12 is a front view of a unit pixel of a TFT substrate side of an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 13 is a schematic diagram showing an electric circuit of an active matrix type liquid crystal display device according to a second embodiment of the present invention.

FIG. 14 shows a scanning signal wiring terminal GTM of an active matrix type liquid crystal display device according to a second embodiment of the present invention.
FIG. 2A is a plan view of a main part of a portion, and FIG. 2B is a cross-sectional view taken along line AA ′.

FIG. 15 shows a video signal wiring terminal DTM of an active matrix type liquid crystal display device according to a second embodiment of the present invention.
FIG. 2A is a plan view of a main part of a portion, and FIG. 2B is a cross-sectional view taken along line AA ′.

FIG. 16 is a diagram showing a process flow for realizing the configuration of the second embodiment of the present invention.

FIG. 17 is a sectional view taken along the line AA ′ in FIG. 12 when a TFT substrate is manufactured according to the process flow of FIG. 16;

FIG. 18 is a cross-sectional view showing a third embodiment of the present invention, and is a cross-sectional view including a counter substrate taken along a line AA ′ shown in FIG. 19 described later.

FIG. 19 is a surface view of a unit pixel on a TFT substrate side of an active matrix liquid crystal display device according to a third embodiment of the present invention.

FIG. 20 is a cross-sectional view of the TFT substrate side taken along line BB ′ shown in FIG. 20 according to the third embodiment of the present invention.

FIG. 21 is a diagram showing a process flow for realizing the configuration of the third embodiment of the present invention.

FIG. 22 is a sectional view taken along the line AA ′ in FIG. 18 when a TFT substrate is manufactured according to the process flow in FIG. 21;

FIG. 23 is a sectional view taken along the line BB ′ in FIG. 18 when a TFT substrate is manufactured according to the process flow of FIG. 21;

FIG. 24 shows a scanning signal wiring terminal GTM of an active matrix liquid crystal display device according to a fourth embodiment of the present invention.
FIG. 2A is a plan view of a main part of a portion, and FIG. 2B is a cross-sectional view taken along line AA ′.

FIG. 25 is a terminal DTM for video signal wiring of an active matrix type liquid crystal display device according to a fourth embodiment of the present invention.
FIG. 2A is a plan view of a main part of a part, and FIG.

FIG. 26 shows a scanning signal wiring terminal GTM of an active matrix type liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 2A is a plan view of a main part of a portion, and FIG. 2B is a cross-sectional view taken along line AA ′.

FIG. 27 is a terminal DTM for video signal wiring of an active matrix type liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 2A is a plan view of a main part of a part, and FIG.

FIG. 28 is a view showing a process flow for realizing the configuration of the fifth embodiment of the present invention.

FIG. 29 is a cross-sectional view of an active matrix type liquid crystal display device according to a sixth embodiment of the present invention, and is a cross-sectional view taken along the line AA ′ shown in FIG. 30 described later.

FIG. 30 is a surface view of a transparent insulating substrate side on a side where a thin film transistor of a unit pixel is arranged in an active matrix type liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 31 is a cross-sectional view of the transparent insulating substrate on the side where the thin film transistor is arranged, taken along the line BB ′ shown in FIG. 30;

FIG. 32 shows a scanning signal wiring terminal GT of an active matrix type liquid crystal display device according to a sixth embodiment of the present invention.
FIG. 2A is a plan view of a main part of an M portion, and FIG.

FIG. 33 shows a video signal wiring terminal DT of an active matrix type liquid crystal display device according to a sixth embodiment of the present invention.
FIG. 2A is a plan view of a main part of an M portion, and FIG.

FIG. 34 is a diagram showing a process flow for realizing the configuration of the sixth example of the present invention.

FIG. 35 is a sectional view taken along the line AA ′ in FIG. 30 when a TFT substrate is manufactured according to the process flow in FIG. 34;

FIG. 36 is a sectional view taken along the line BB ′ in FIG. 30 when a TFT substrate is manufactured according to the process flow of FIG. 34;

FIG. 37 is a sectional view of an active matrix type liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 38 is an observation example at the time of processing a fine comb tooth pattern of an amorphous IZO film.

FIG. 39 shows measurement examples of X-ray diffraction spectra of an amorphous IZO film and an amorphous ITO film.

FIG. 40 is an SEM photograph observation example of the amorphous IZO film and the surface of the amorphous ITO film during etching.

FIG. 41 is a schematic plan view when a transparent electrode pattern is arranged over a wiring pattern.

FIG. 42 is a configuration diagram for verifying the effect of the coating type insulating film.

[Explanation of symbols]

SUB1... Transparent insulating substrate on which the TFT is disposed, TF
T: a thin film transistor which is a switching element of a pixel,
CLA: Single layer film of Al or Al alloy film, or A
1 or Al alloy film and high melting point metal film, high melting point metal alloy film, or high melting point metal silicide film laminated common signal wiring, CLC ... Cr or Cr alloy film common signal wiring, CEA ... amorphous A common signal electrode made of indium zinc oxide, amorphous indium germanium oxide, or an oxide transparent conductive film containing these as a main component, a single layer film of GEA... Al or Al alloy film, or an Al or Al alloy film and a high melting point metal film , A scanning signal electrode having a laminated structure of a refractory metal alloy film or a refractory metal silicide film, GLA.
a single-layer film of an Al or Al alloy film, or a scanning signal wiring having a laminated structure of an Al or Al alloy film and a high-melting metal film, an alloy film of a high-melting metal, or a silicide film of a high-melting metal; zinc,
Pixel electrode made of amorphous indium germanium oxide or an oxide transparent conductive film containing these as a main component, PXP ... Pixel electrode made of a polycrystalline ITO film, SI ...
Semiconductor layer, SD: video signal electrode serving as source / drain electrode of thin film transistor TFT, DL: video signal wiring, G
I: a gate insulating film of a thin film transistor; PAS: a surface protective film of a thin film transistor; NSI: an electrode made of a silicon film doped with an impurity such as phosphorus to ensure contact; TH: a through hole; OIL: a coating type insulating film;
BM: light shielding pattern, CF: color filter, SUB2
... Transparent insulating substrate on the color filter CF side, ORI1, ORI2
... Alignment film, LC ... Liquid crystal layer, POL1,2 ... Polarizer, GT
M: scanning signal wiring terminal, DTM: video signal wiring terminal, CTM: common signal wiring terminal, CB: common signal wiring bus wiring, SL: sealing material, TCA: amorphous indium zinc oxide, amorphous indium germanium oxide, Alternatively, a pad electrode composed of an oxide transparent conductive film containing these as a main component, a TCP pad electrode composed of a polycrystalline ITO film, a TCAP amorphous indium zinc oxide, an amorphous indium germanium oxide, or a transparent oxide containing these as a main component By selectively crystallizing the conductive film, electrical connection is compensated for at a connection portion between a pad electrode made of a polycrystallized film, a wiring made of a TCC ... Al film or an Al alloy film, and the oxide transparent conductive film. Pad electrode to be used.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kenichi Onizawa 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiki Kaneko 3300 Hayano, Mobara-shi, Chiba Shares Hitachi, Ltd. Display Group (72) Inventor Masuyuki Ota 3300 Hayano, Mobara-shi, Chiba Prefecture Hitachi, Ltd. Display Group (72) Inventor Masahiro Ishii 3300, Hayano, Mobara-shi, Chiba Prefecture F-term in Hitachi, Ltd. Display Group (Reference) 2H092 GA14 GA17 GA25 GA34 GA42 GA48 GA51 GA60 HA03 HA04 HA12 JA26 JA35 JA40 JA44 JA46 JB24 JB33 KA04 KA05 KA18 KB04 KB13 KB24 MA05 MA08 MA10 MA13 MA27 5C094 AA21 AA42 AA43 BA03 BA43 CA19 EA04 EA05 EA07

Claims (27)

[Claims] 1. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal wirings and a plurality of video signal wirings intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a part of each of the pixel electrodes and the common signal electrode, the second transparent electrode disposed on the liquid crystal layer side via an insulating film among the pixel electrode and the common signal electrode has a slit shape or a comb shape. A liquid crystal display device processed into a shape, a first wiring using a metal material, or a first electrode,
Of the pixel electrode and the common electrode, the first transparent electrode on the side closer to the first substrate is connected to and stacked on at least a part of the first wiring or the first electrode, In a configuration in which a first wiring or the first electrode is disposed on a side closer to the first substrate with respect to the first transparent electrode, the first transparent electrode may be made of amorphous indium zinc oxide or amorphous indium zinc oxide. A liquid crystal display device comprising indium germanium oxide or an amorphous oxide transparent conductive film containing these as a main component. 2. The liquid crystal display device according to claim 1, wherein the first wiring or the first electrode comprises a high melting point metal film, a high melting point metal alloy film, or a high melting point metal silicide film. A liquid crystal display device, which is an electrode or a wiring formed of a single-layer film. 3. The liquid crystal display device according to claim 1, wherein at least a part of the first wiring or the first electrode is formed of a laminated film composed of two or more different metal films or alloy films. A metal film on the side closest to the liquid crystal layer of the two or more laminated films is a refractory metal, a refractory metal alloy film, or a refractory metal silicide film. A second conductive film, wherein the first transparent electrode and the first wiring or the first electrode are connected at least in a part of a region where the second conductive film is arranged. Liquid crystal display device. 4. The liquid crystal display device according to claim 3, wherein at least one of the conductive films other than the second conductive film among the two or more metal films is an Al or Al alloy film. A liquid crystal display device characterized by the above-mentioned. 5. The liquid crystal display device according to claim 3, wherein the first wiring or the first wiring is etched by self-aligningly etching a multilayer film forming the first wiring or the first electrode. A liquid crystal display device comprising: a first electrode; 6. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal wirings and a plurality of video signal wirings intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a part of each of the pixel electrodes and the common signal electrode, the second transparent electrode disposed on the liquid crystal layer side via an insulating film among the pixel electrode and the common signal electrode has a slit shape or a comb shape. A liquid crystal display device processed into a shape, formed of an Al or Al alloy film,
A first conductive film in which an Al oxide film is formed on at least a part of the outermost surface of the alloy film, and at least A of the first conductive film
a second melting point metal film, a high melting point metal alloy film, or a high melting point metal silicide film, which is disposed in a part of the region where the oxide is not formed and is connected to the first conductive film; A first electrode formed using at least two types of conductive films, or a first wiring, and a first electrode disposed on the first substrate side of the pixel electrode and the common signal electrode. The transparent electrode, at least the high melting point metal film, the high melting point metal alloy film, or the high melting point metal film by stacking in a part of the region where the alloy film of the silicide film of the melting point metal is arranged, The first wiring or the first electrode is connected to the alloy film of the high melting point metal or the alloy film of the silicide film of the melting point metal, and the side closer to the first substrate with respect to the first transparent electrode. In the configuration located at The liquid crystal display device, wherein the first transparent electrode is an amorphous indium zinc oxide, an amorphous indium germanium oxide, or an amorphous oxide transparent conductive film containing these as a main component. 7. The liquid crystal display device according to claim 2, wherein the refractory metal film is made of Ti, V, Cr, Zr, Nb, M
o, Hf, Ta, or W, wherein the alloy film of the refractory metal is an alloy film of the refractory metal film,
The refractory metal silicide film is
And a liquid crystal display device comprising: 8. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal wirings and a plurality of video signal wirings intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a part of each of the pixel electrodes and the common signal electrode, the second transparent electrode disposed on the liquid crystal layer side via an insulating film among the pixel electrode and the common signal electrode has a slit shape or a comb shape. A liquid crystal display device processed in a shape, wherein a first transparent electrode on a side closer to a first substrate among the pixel electrode and the common signal electrode is made of amorphous indium zinc oxide, amorphous indium germanium oxide, or A liquid crystal display device comprising an amorphous oxide transparent conductive film containing these as main components. 9. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal lines and a plurality of video signal lines intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a part of each is formed of a transparent conductive film, and a second electrode disposed on the liquid crystal layer side of the pixel electrode and the common signal electrode is processed into a slit shape or a comb shape. A liquid crystal display device, wherein, of the pixel electrode and the common signal electrode, a first transparent electrode disposed closer to a first substrate has an amorphous indium zinc oxide functioning as the common electrode; An amorphous indium-germanium oxide or an amorphous oxide transparent conductive film containing these as a main component, which is disposed closer to the first substrate with respect to the common electrode, without passing through the common electrode and an insulating film. A liquid crystal display device wherein a directly connected common signal line is formed in the same process and with the same material as a scanning signal line. 10. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal lines and a plurality of video signal lines intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a portion of each of the pixel electrodes and the common signal electrode, a second electrode disposed on the liquid crystal layer side via an insulating film between the pixel electrode and the common signal electrode has a slit shape or a comb-like shape. A liquid crystal display device that is processed into a shape, wherein the first transparent electrode disposed on the side closer to the first substrate among the pixel electrode and the common signal electrode is an amorphous having a function as the common electrode. Indium zinc oxide, amorphous indium germanium oxide or an amorphous oxide transparent conductive film containing these as a main component,
A common signal line, which is arranged closer to the first substrate with respect to the common electrode and directly connected to the common electrode without using an insulating film, is formed in the same step and with the same material as the video signal line. Characteristic liquid crystal display device. 11. A pair of substrates, a liquid crystal layer sandwiched between the substrates, and a first substrate of the pair of substrates includes a plurality of scanning signal wirings and a plurality of video signal wirings intersecting them in a matrix. And a plurality of thin film transistors formed corresponding to respective intersections of these wirings, and at least one pixel corresponding to each area surrounded by the plurality of scanning signal wirings and the video signal wirings Each pixel has a common signal electrode connected over a plurality of pixels, and a pixel electrode connected to a corresponding thin film transistor, and the common signal electrode and the pixel electrode are partially An electric field is formed in the liquid crystal layer by a voltage applied to the common signal electrode and the pixel electrode, and the pixel electrode and the common signal electrode are superimposed. At least a portion of each of the pixel electrodes and the common signal electrode, a second electrode disposed on the liquid crystal layer side via an insulating film between the pixel electrode and the common signal electrode has a slit shape or a comb-like shape. A liquid crystal display device that is processed into a shape, wherein a first transparent electrode disposed on a side closer to a first substrate among the pixel electrode and the common signal electrode is an amorphous having a function as the pixel electrode. Indium zinc oxide, amorphous indium germanium oxide or an amorphous oxide transparent conductive film containing these as a main component,
The liquid crystal display device according to claim 1, wherein the pixel electrode is directly connected to a source / drain electrode of the thin film transistor disposed closer to the first substrate than the pixel electrode without using an insulating film. 12. The liquid crystal display device according to claim 1, wherein at least a part of the insulating film disposed between the first transparent electrode and the second transparent electrode. A liquid crystal display device comprising a material formed by printing, spin coating, or the like, and more specifically, an organic resin insulating film or a coating type insulating film containing Si. 13. The liquid crystal display device according to claim 12, wherein an insulating film disposed on the first transparent electrode and the second transparent electrode is a gate insulating film of a thin film transistor in addition to the coating type insulating film. A liquid crystal display device having a stacked structure including at least one of an insulating film having a film function and a surface protective film of a thin film transistor. 14. The liquid crystal display device according to claim 12, wherein the coating type insulating film is a photo image forming type. 15. The liquid crystal display device according to claim 13, wherein the insulating films disposed on the first transparent electrode and the second transparent electrode are self-aligned collectively by using a pattern of a coating type insulating film. A liquid crystal display device characterized in that through holes are opened by mechanical processing. 16. The liquid crystal display device according to claim 12, wherein said coating type insulating film has a thickness of 0.2 μm to 4.0 μm, more preferably 0.2 μm to 2.0 μm. A liquid crystal display device characterized by the above-mentioned. 17. The liquid crystal display device according to claim 1, wherein the second transparent electrode is made of amorphous indium zinc oxide, amorphous indium germanium oxide, or an amorphous oxide containing these as a main component. A liquid crystal display device comprising a transparent conductive film. 18. The liquid crystal display device according to claim 1, wherein a terminal connected to at least one of the scanning signal wiring, the video signal wiring, and the common signal wiring. The exposed portion of the portion, or a part of the outermost surface of the exposed portion is made of the same material, at least one of the scanning signal wiring, the video signal wiring, and the common signal electrode, a metal film or an alloy film formed in the same step, or A liquid crystal display device, characterized in that it is a first terminal lead pad electrode made of a laminated film of the above. 19. The liquid crystal display device according to claim 1, wherein a terminal is connected to at least one of the scanning signal wiring, the video signal wiring, and the common signal wiring. The exposed portion of the portion, or a portion of the outermost surface of the exposed portion, is made of the same material, a metal film, an alloy film, or A first terminal lead pad electrode made of these laminated films, and formed on the first terminal lead pad electrode in the same step and with the same material as the first transparent electrode or the second transparent electrode. A liquid crystal display device having a configuration in which the formed second terminal lead-out pad electrodes are stacked. 20. The liquid crystal display device according to claim 19, wherein the second terminal lead-out pad electrode formed of a transparent electrode disposed at the terminal portion is formed of an amorphous transparent conductive film, and selectively crystallized. A liquid crystal display device characterized in that a polycrystalline transparent conductive film is obtained by forming the film. 21. The liquid crystal display device according to claim 1, wherein the second transparent electrode is formed of a polycrystalline transparent conductive film, and wherein the scanning signal wiring, the video signal wiring, and the common electrode are connected to each other. An exposed portion of a terminal portion connected to at least one of the external driving circuits of the signal wiring, or a part of the outermost surface of the exposed portion is formed of a material and a process when forming the second transparent electrode. A liquid crystal display device comprising a third terminal lead-out pad electrode. 22. The liquid crystal display device according to claim 21, wherein the third terminal lead-out pad electrode made of the polycrystalline transparent conductive film, and the scanning signal line, the video signal line, and the common signal line. When connecting at least any one of the above, the third terminal lead-out pad electrode and the second terminal lead-out pad electrode are connected, and the second terminal lead-out pad electrode and the scanning signal wiring, the image A liquid crystal display device, wherein a signal wiring is connected to at least one of the extending portions of the common signal wiring. 23. The liquid crystal display device according to claim 1, wherein the amount of zinc or germanium contained in the first transparent conductive film is in the range of 3 to 30 at% with respect to indium. A liquid crystal display device, comprising: 24. The liquid crystal display device according to claim 1, wherein the first transparent conductive film has a taper angle of 1 at a pattern end.
A liquid crystal display device having a range of 0 to 80 °, more preferably 30 to 60 °. 25. The liquid crystal display device according to claim 1, wherein indium zinc oxide is used as the amorphous transparent conductive film, and the thickness of the indium zinc oxide is 50 to 150.
A liquid crystal display device characterized by having a thickness of nm. 26. The liquid crystal display device according to claim 1, wherein the first transparent electrode is processed into a comb shape or a slit shape. 27. The liquid crystal display device according to claim 1, wherein at least a part of the insulating film disposed between the first transparent electrode and the second transparent electrode is a silicon nitride film. A liquid crystal display device, comprising: