JP2002050682A - Method for manufacturing semiconductor device and reticle mask - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which polishing can be effected with high planarity, without increasing the number of steps when a trench element isolation is formed by polishing an insulation film. SOLUTION: A trench 104a for element isolation A and a trench 104b for alignment mask B are formed on the surface side of a semiconductor substrate 101. A silicon oxide film (insulation film) 106 is formed on the semiconductor substrate 101 for filling the trenches 104a and 104b. Simultaneously with removal of the silicon oxide film 106 on the trench 104b through etching down to a specified depth, a part of the silicon oxide film 106 in an active region 105 between the trenches 104a and 104b is removed, by etching in order to make uniform the progress of polishing the silicon oxide film 106 in the plane of the semiconductor substrate 101 in the subsequent polishing steps. Finally, the silicon oxide film 106 on the active region 105 is removed through CMP polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for forming a trench element isolation and a reticle mask used in the method.

[0002]

2. Description of the Related Art In recent ULSI, as semiconductor devices become more highly integrated and sophisticated, there is an increasing demand for miniaturization of gate electrodes and element isolation regions of MOS transistors and reduction of the distance between them. It's getting tougher. Among them, the miniaturization of the gate electrode largely depends on the performance of the exposure device used in the lithography process.However, regarding the miniaturization of the element isolation region and the reduction of the distance between the element isolation region and the gate electrode, other advanced lithography techniques have been used. Shallow trench iso
lation (hereinafter referred to as STI) technology is also attracting attention.

[0003] Local isolation of silicon (LOCOS) technology using a thermal oxide film has been used for device isolation of LSI. Since the LOCOS element isolation is formed by thermally oxidizing the silicon substrate itself using the silicon nitride film as a mask, the LOCOS element isolation has a great advantage that the process is simple, the problem of the oxide film stress is small, and the quality of the generated oxide film is good. . For this reason, the LSI process has been used while being repeatedly improved in the LSI process where technological innovation is intense. However, it is said that LSIs having a design rule of 0.25 μm or later have a limit from the viewpoint of miniaturization.

[0004] Specifically, during thermal oxidation, the oxidation reaction spreads in the lateral direction and a so-called bird's beak occurs.
The element isolation pitch is wider by the bird's beak than the opening width of the silicon nitride film serving as a mask. In order to control the bird's beak, it is effective to not form a so-called pad oxide film formed below the silicon nitride film serving as an oxidation mask. However, when a silicon nitride film is formed directly on a silicon substrate without forming a pad oxide film, there is a problem that a stress of the silicon nitride film causes crystal defects in the silicon substrate.
Therefore, it is very difficult to solve the bird's beak problem and the crystal defect problem at the same time with the LOCOS element isolation technology.

[0005] As an element isolation technique replacing the LOCOS element isolation technique, there is the STI technique described above. S
In the TI technology, a trench is formed by etching, and an element is formed by embedding an insulator in the trench. Therefore, a dimensional conversion difference from a design dimension is small, and it is suitable in principle for miniaturization. . After the insulator is embedded, the etch-back method or chemical mechanical polishing (Chemical Mechanical Po
lithing (hereinafter referred to as CMP), which is advantageous in that the surface flatness required for performing highly accurate lithography can be obtained.

Next, an example of the STI technique will be described below. As shown in FIG. 2A, a pad oxide film 202 and a silicon nitride film 203 are formed on the surface of a silicon substrate 201, and a trench 204 is formed in the silicon substrate 201 by using lithography and etching. Here, the surface layer portion of the substrate 201 separated by the trench 204 becomes the active region 205. Next, CVD (chemical
The trench 204 is buried with an insulating film 206 by a vapor deposition method. Thereafter, as shown in FIG. 2B, the surplus insulating film 206 on the silicon substrate 201 is removed by CMP using the silicon nitride film 203 as a stopper to planarize the surface. As described above, the trench 20
The STI 207 in which the insulating film 206 is buried in the substrate 4 is obtained. When part of the trench 204 is used as an alignment mark in lithography to be performed later, the insulating film 206 in the trench 204 used as the alignment mark is removed by etching after performing CMP.

Incidentally, as is well known, the polishing rate in CMP greatly depends on the surface shape of the film to be polished, and the polishing rate on the surface of the insulating film 206 having a small area covering an isolated active region (hereinafter, referred to as an isolated active region 205a). Since a higher polishing pressure acts on the surface of the insulating film 206 having a large area covering a dense active region (hereinafter, referred to as a dense active region 205b), the polishing speed is increased. For this reason, if the polishing is performed until the polishing of the other portion having a low polishing rate is completed, the isolated active region 205a is overpolished, and the silicon nitride film 203 and the silicon substrate 201 which are the polishing stoppers are polished. The characteristics of the transistor formed in the isolated active region 205a are adversely affected. On the other hand, when the silicon nitride film 203 and the pad oxide film 202 are removed in the dense active region 205b due to a low polishing rate, a step is formed between the surface of the substrate 201 and the surface of the buried insulating film 206 in the element isolation region (STI207). h is formed,
This becomes a problem when processing the gate electrode later.

Therefore, as a method of avoiding and reducing the dependence of the polishing rate on the underlying pattern density, formation of a dummy active region or formation of a dummy active region on a region where active regions are dense as shown by a two-dot chain line in FIG. Of the buried insulating film 206 is removed in advance by dry etching or the like, and then CMP is performed. According to such a method,
The uniformity of the polished area in the surface of the substrate 201 is improved,
The polishing rate can be made uniform within the surface of the substrate 201.

[0009]

However, in the method of forming a dummy active region, it is necessary to prepare a reticle mask to which an exposure pattern for forming a dummy active region is added at the time of lithography for forming a trench. Yes, it takes time. In the method of removing a part of the buried insulating film in advance, a lithography step of forming a resist pattern serving as a mask during dry etching and a dry etching step are added, and the number of manufacturing steps is increased.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of easily performing excellent flatness polishing without increasing the number of steps.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: isolating an element by embedding an insulating film in a trench; and forming an alignment mark utilizing a step in the trench. Is formed on the surface side of the semiconductor substrate. After forming a trench for element isolation and a trench for alignment mark on the surface side of the semiconductor substrate and forming an insulating film in a state where these trenches are buried, these trenches are formed. Before removing the insulating film on the semiconductor substrate in between by polishing, the insulating film on the trench serving as an alignment mark is etched away to a predetermined depth, and at the same time, the progress of the polishing of the insulating film in the next polishing step is performed on the semiconductor substrate surface. A step of etching and removing a part of the insulating film between the trenches in order to make the inside uniform. .

In such a manufacturing method, the removal of the insulating film portion for making the progress of polishing uniform is performed at the same time as the removal of the insulating film in the trench for forming the alignment mark. For this reason, it is not necessary to add an independent etching step only for removing the insulating film portion for making the progress of polishing uniform. Then, in the next step, the insulating film is polished with good flatness.

A reticle mask of the present invention is a reticle mask used for lithography for forming a resist pattern used as a mask when a part of the above-mentioned insulating film is removed by etching. An exposure pattern is provided so that a resist pattern that opens on the trench and on a wide portion between the trenches is formed.

By performing lithography using such a reticle mask, a resist pattern having openings on the alignment mark trenches and on the wide portions between the trenches is formed. Then, the insulating film is etched using the resist pattern as a mask, thereby simultaneously removing the insulating film portion on the trench and the insulating film portion on the wide portion between the trenches.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the manufacturing process of the semiconductor device described here, element isolation (ie, STI: shallow trench isolation) in which an insulating film is buried in a trench is performed.
And an alignment mark using a step of the trench on the surface side of the semiconductor substrate. The alignment mark is used as an alignment mark when a resist pattern is formed on a semiconductor substrate in a later lithography step.

First, as shown in FIG. 1A, 5n is formed on a semiconductor substrate 101 made of silicon by a thermal oxidation method.
A pad oxide film 102 having a thickness of m to 20 nm is formed, and then a silicon nitride film 103 having a thickness of 50 to 250 nm is formed by a low pressure CVD (chemical vapor deposition) method. This silicon nitride film 103 is used as a polishing stopper in polishing performed later.

Next, a resist pattern (not shown) is formed on the silicon nitride film 103. This resist pattern is formed by subjecting a photoresist layer formed on the silicon nitride film 103 to pattern exposure using a stepper using KrF excimer laser light as exposure light, followed by development processing.

Thereafter, using this resist pattern as a mask, the silicon nitride film 103, the pad oxide film 102, and the surface layer of the semiconductor substrate 101 are etched. Thus, a plurality of trenches 104a used as element isolation and a plurality of trenches 104b serving as alignment marks are formed on the front surface side of the semiconductor substrate 101. The trench 104a and the trench 104b have a depth of about 380 nm from the surface of the semiconductor substrate 101, for example. Then, the portion of the semiconductor substrate 101 between the trenches 104a and 104b is defined as an active region 105 which is an element forming portion.

After that, an insulating film (here, silicon oxide film) 106 having a thickness of, for example, about 700 nm is formed on the semiconductor substrate 101 while the trenches 104a and 104b are buried.
Form on top. Here, for example, high-density plasma CVD
A silicon oxide film 106 is formed by a method.

Next, a resist pattern (not shown) is formed on the silicon oxide film 106. In the lithography for forming this resist pattern, a wide portion between the trenches 104a and 104b, that is, on the large-area active region 105 and the small-area active region 1 is used.
Exposure is performed so that a resist pattern having an opening is formed on a portion where only the active regions 05 are densely arranged (only the large-area active region 105 is shown in the drawing) and further on the alignment mark trench 104b. Pattern exposure is performed using a reticle mask provided with a pattern.

Then, as shown in FIG. 1B, the silicon oxide film 106 is partially removed by etching using the resist pattern formed by such pattern exposure and subsequent development processing as a mask. Here, the silicon oxide film 106 on the wide portion between the trenches 104a and 104b, that is, on the large-area active region 105 and the portion where the active regions 105 are densely arranged is removed, and the polishing is performed at the next polishing. In addition, the polishing proceeds uniformly in the surface of the semiconductor substrate 101, so that the occurrence of partial overpolishing or insufficient polishing is prevented. At the same time, the silicon oxide film 106 on the alignment pattern trench 104b is also removed.

At this time, the etching amount (etching depth)
E indicates that at least the trenches 10 for the alignment pattern are sufficiently large at the time of lithography to be performed later that the alignment using the alignment marks can be sufficiently performed.
4b is set so that a minimum step h1 (step between the surface of the semiconductor substrate 101 and the surface of the silicon oxide film 106) appears.

That is, the silicon oxide film 10 above the trench 104b (including the inside of the trench 104b)
6 is H, the depth of the trench 104b is D, the amount of film reduction until the subsequent lithography process is R, and the minimum step capable of sufficiently performing alignment is h1, and the etching amount E here is Is in a range where E ≧ H− (D−h1) −R, and when polishing is performed later, the semiconductor substrate 1
01 is set to such a value that polishing proceeds uniformly in the plane No. 01 and occurrence of partial overpolishing or insufficient polishing is prevented. Here, the amount of film reduction R up to the subsequent lithography step refers to a process such as removal of the pad oxide film 102, removal of the sacrificial oxide film, removal of the gate oxide film, etc., after this etching until the subsequent lithography process. Through this process, the silicon oxide film 106 remaining inside the trench 104b is removed.

That is, the etching amount E of the silicon oxide film 106 is set to an etching amount necessary for flattening the next polishing within a range in which the minimum step h1 of the trench 104b is secured before the subsequent lithography process. It is sufficient that the silicon oxide film 106 remains in the trench 104b.

After the above, as shown in FIG. 1C, the silicon oxide film 106 which has been partially etched away is polished by a CMP method from the surface side. Then, the portion of the silicon oxide film 106 on the semiconductor substrate 101 between the trenches 104a and 104b, that is, the active region 105
The upper silicon oxide film 106 is removed, and the trench 10 is removed.
The silicon oxide film 106 is left in 4a and 104b.

As described above, the element isolation A in which the inside of the trench 104a is buried with the silicon oxide film 106 and the alignment mark B utilizing the step of the trench 104b are formed on the surface side of the semiconductor substrate 101. At this point, the step of the trench 104b in the alignment mark B may not be sufficient for use in alignment (ie, may not reach the minimum step h1). However, the silicon oxide film 106 in the trench 104b is reduced by various processes before the subsequent lithography process, and the minimum step h1 required for alignment is secured.

According to the above-described manufacturing method, the silicon oxide film 10 on the active region 105 which has a large area and is densely arranged
Since CMP polishing is performed in a state where six portions are removed by etching, the layer to be polished (that is, the silicon oxide film 1) is removed.
06) The polishing can be uniformly promoted in the surface of the semiconductor substrate 101 without depending on the density of the underlying pattern. Therefore, it is possible to prevent occurrence of partial overpolishing or insufficient polishing.

Further, in addition to this, partial etching and removal of the silicon oxide film 106 for uniform polishing are performed simultaneously with etching and removal of the silicon oxide film 106 in the trench 104b serving as an alignment mark. Therefore, the silicon oxide film 10 on the active region 105
There is no need to add a separate step to remove the six parts. As a result, it is possible to perform CMP polishing with good flatness without increasing the number of steps.

Further, the etching amount when the silicon oxide film 106 is partially removed by etching is set in a wide range in which the minimum step h1 required for alignment can be secured, so that the uniformity of the next CMP polishing can be improved. Can also be set in consideration of That is, since the setting range of the etching amount of the silicon oxide film 106 is wider than that in the case where the entire silicon oxide film 106 in the trench 104b serving as an alignment mark is removed, the silicon oxide film 106 on the active region 105 has an excessive amount. Inconveniences such as rapid etching can be prevented. Therefore, the alignment can be sufficiently performed using the alignment mark B utilizing the step of the trench, and the next CMP polishing can be performed without depending on the density of the underlying pattern.

[0030]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the removal of the insulating film for making the progress of polishing uniform in the plane is performed for forming the alignment mark. By performing the polishing simultaneously with the removal of the insulating film in the trench, the flatness can be improved without adding an independent process only for the partial removal of the insulating film to make the progress of the polishing uniform in the plane. Good polishing can be performed. Therefore, the number of manufacturing steps of the semiconductor device can be reduced. Further, by using the reticle mask of the present invention, the above-described method of manufacturing a semiconductor device of the present invention can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional process view illustrating a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a sectional process view illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

101: semiconductor substrate, 104a: trench (for element isolation), 104b: trench (for alignment mark),
106: silicon oxide film (insulating film), A: element isolation, B
…Alignment mark

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Osamu Yamaya 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H095 BB02 BE03 5F032 AA34 AA44 AA66 AA77 BA02 CA17 DA02 DA03 DA22 DA33 DA53

Claims (3)

[Claims] 1. A step of forming a trench for element isolation and a trench for an alignment mark on the surface side of a semiconductor substrate, and forming an insulating film on the semiconductor substrate in a state where these trenches are buried; At the same time that the insulating film on the trench is removed by etching to a predetermined depth, a part of the insulating film between the trenches is removed in order to make polishing progress of the insulating film in the next polishing process uniform within the semiconductor substrate surface. A method of manufacturing a semiconductor device, comprising: a step of removing by etching; and a step of removing the insulating film on the semiconductor substrate between the trenches by polishing. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of etching and removing the insulating film, exposure alignment can be sufficiently performed by a step of the trench serving as the alignment mark in a lithography step performed later. A method of manufacturing the semiconductor device, wherein an etching amount of the insulating film is set within a range where the insulating film on the trench is removed. 3. A reticle mask used in lithography for forming a resist pattern on an insulating film formed on a front surface side of a semiconductor substrate in a state in which a trench for element isolation and a trench for alignment mark are buried. A reticle mask provided with an exposure pattern so as to form a resist pattern having openings on the alignment mark trench and on a wide portion between the trenches.