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JP2002057242A - Area array type semiconductor package - Google Patents

Area array type semiconductor package

Info

Publication number
JP2002057242A
JP2002057242A JP2000239113A JP2000239113A JP2002057242A JP 2002057242 A JP2002057242 A JP 2002057242A JP 2000239113 A JP2000239113 A JP 2000239113A JP 2000239113 A JP2000239113 A JP 2000239113A JP 2002057242 A JP2002057242 A JP 2002057242A
Authority
JP
Japan
Prior art keywords
area array
semiconductor package
type semiconductor
solder
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000239113A
Other languages
Japanese (ja)
Inventor
Hiroshi Kondo
浩史 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2000239113A priority Critical patent/JP2002057242A/en
Publication of JP2002057242A publication Critical patent/JP2002057242A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
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    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】 【課題】より高密度実装に適応することができるエリア
アレイ型半導体パッケージを提供する。 【解決手段】絶縁性材料からなる保持部材２の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子１が搭載され、保持部材２の他面側にエリ
アアレイ状に配置された電極４が形成されたエリアアレ
イ型半導体パッケージにおいて、電極４上に各々突起部
９が設けられ、この突起部表面は、少なくともはんだ材
料が溶融し合金化して接合することが可能な材料からな
る。 (57) [Problem] To provide an area array type semiconductor package adaptable to higher density mounting. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and arranged in an area array on the other surface of the holding member. In the area array type semiconductor package in which the formed electrodes 4 are formed, the projections 9 are provided on the electrodes 4 respectively, and the surface of the projections is made of at least a material which can be joined by melting and alloying the solder material. Become.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、電極をマトリック
ス状にもつエリアアレイ型半導体パッケージに関し、特
にＬＧＡ(Land Grid Array)パッケージに関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an area array type semiconductor package having electrodes in a matrix, and more particularly to an LGA (Land Grid Array) package.

【０００２】[0002]

【従来の技術】従来、電極をマトリックス状にもつエリ
アアレイ型半導体パッケージとしては、１９９１年ごろ
モトローラ社より提案されたＢＧＡ(Ball Grid Array)
パッケージが知られている。このＢＧＡパッケージは、
従来のＱＦＰ(Quad Flat Package)の抱える２つの課題
の解決を目指したものであり、その課題の１つは、ＩＣ
パッケージが多ピン化するに従い、端子ピッチが微細化
され端子リードの強度不足により端子平坦性が悪化し、
リフロー時のはんだ付け性が悪化し歩留まりが低下する
というものと、もう一つは、微細なピッチでクリームは
んだを印刷しなければならなくなり、はんだブリッジに
よるショートや、はんだ不足によるオープンの発生と言
った印刷工程での歩留まりの低下であった。2. Description of the Related Art Conventionally, as an area array type semiconductor package having electrodes in a matrix form, a BGA (Ball Grid Array) proposed by Motorola in around 1991 was used.
Packages are known. This BGA package is
It aims to solve the two problems of the conventional QFP (Quad Flat Package), and one of the problems is IC
As the number of pins in the package increases, the terminal pitch becomes finer and the terminal flatness deteriorates due to insufficient strength of the terminal leads.
The other problem is that the solderability during reflow deteriorates and the yield decreases, and the other is that cream solder must be printed at a fine pitch, resulting in short circuits due to solder bridges and openness due to insufficient solder. The yield in the printing process was reduced.

【０００３】そこで、まずこのＢＧＡの製造方法を説明
する。ＢＧＡは、ＢＴレジンを主材料とする厚み０．３
〜０．７ｍｍの両面（２層）あるいは多層プリント基板
の一方の面に半導体素子（ＩＣチップ）をマウントし、
マウントされたプリント基板の面に設けられた配線パタ
ーンと半導体素子の電極部とをワイヤーボンディングに
より接続し、その後トランスファーモールディング法あ
るいはポッティング法により半導体素子が搭載されてい
るプリント基板の片面側のみをオーバーモールディング
して、半導体素子を封止し、その後、プリント基板の他
面にマトリックス状に設けられた電極部の上に粘着性フ
ラックスを転写し、その上にはんだボールを搭載した
後、リフロー工程によりはんだボールを溶融させ電極部
と接合させて完成する。その際、はんだボールは、溶融
時の表面張力により略球形状に突出した形を保ったまま
電極部と接合し、冷却され固まったときも球形状の形状
を保っている。[0003] First, a method of manufacturing this BGA will be described. BGA has a thickness of 0.3 with BT resin as the main material.
A semiconductor element (IC chip) is mounted on both sides (two layers) of about 0.7 mm or one side of a multilayer printed circuit board,
Connect the wiring pattern provided on the surface of the mounted printed circuit board to the electrode of the semiconductor element by wire bonding, and then use transfer molding or potting to cover only one side of the printed circuit board on which the semiconductor element is mounted. Molding, sealing the semiconductor element, then transferring the adhesive flux on the electrode part provided in a matrix on the other surface of the printed circuit board, mounting the solder ball on it, and performing the reflow process The solder ball is melted and joined to the electrode part to complete. At this time, the solder ball is bonded to the electrode portion while maintaining a substantially spherical shape due to the surface tension at the time of melting, and maintains a spherical shape even when cooled and solidified.

【０００４】このＢＧＡは、マトリックス状に電極を有
することから、１．５，１．２７，１．０ｍｍと比較的
緩い電極ピッチであっても多ピン化に対応できるもので
あった。Since the BGA has electrodes in a matrix, the BGA can cope with an increase in the number of pins even when the electrode pitch is relatively loose, such as 1.5, 1.27, and 1.0 mm.

【０００５】しかしながら、さらなる電子機器の高密度
実装をはかっていくためには、ＩＣパッケージの小型化
をより一層進めなければならず、それには、ＢＧＡより
もさらに電極ピッチを０．８，０．５ｍｍへと狭ピッチ
化していかなければならない。However, in order to achieve further high-density mounting of electronic equipment, it is necessary to further reduce the size of the IC package, which requires an electrode pitch of 0.8, 0. The pitch must be reduced to 5 mm.

【０００６】そこで、ＵＳＰ５５９２０２５に示される
ようなプリント基板ではなくフィルムの片面に配線パタ
ーンを持ち、この上に半導体素子をマウントし、ワイヤ
ーボンディングにより半導体素子とフィルム上の配線パ
ターンを接続し、フィルムの他面側から配線パターンが
露出する様にφ０．１〜０．５ｍｍの穴をあけ、この露
出した配線パターン部分を電極部としてはんだボールを
搭載する新しいＢＧＡタイプのパッケージ構造が提案さ
れ、ＦＢＧＡ(Fine pith Ball Grid Array)とよばれて
きている。Therefore, instead of a printed board as shown in US Pat. No. 5,592,025, a wiring pattern is provided on one side of a film, a semiconductor element is mounted thereon, and the semiconductor element and the wiring pattern on the film are connected by wire bonding. A new BGA type package structure has been proposed in which a hole of φ0.1 to 0.5 mm is drilled so that the wiring pattern is exposed from the other surface side, and the exposed wiring pattern portion is used as an electrode portion to mount solder balls. Fine pith Ball Grid Array).

【０００７】このパッケージ構造では、ＴＡＢ(Tape Au
tomated Bonding)フィルムの製造工程を使うことによ
り、ＢＧＡより微細な配線パターンを形成できること
と、片面のみのパターンでありかつ厚み０．０４〜０．
０８ｍｍのフィルムを使っていることから、スルーホー
ル形成をせずに他面側からフィルムに穴をあけるだけで
裏面側からみて露出している電極部を形成でき、ＢＧＡ
のような基板の上下面に配線を持つ時に必要となる配線
接続のためのスペースを必要としない。そのため、電極
ピッチが１ｍｍ未満のパッケージに採用される様になっ
てきた。In this package structure, TAB (Tape Au
By using a manufacturing process of a tomated bonding film, it is possible to form a wiring pattern finer than BGA, and it is a pattern on only one side and has a thickness of 0.04 to 0.
Since an 08mm film is used, it is possible to form an exposed electrode part as viewed from the back side only by making a hole in the film from the other side without forming a through-hole.
This does not require a space for wiring connection required when wiring is provided on the upper and lower surfaces of the substrate. For this reason, it has come to be used for packages having an electrode pitch of less than 1 mm.

【０００８】さらに、実装後のパッケージの取り付け高
さを低くしたいという要求から、図２１，図２２に示す
ようなＢＧＡのはんだボールを取り除いたＬＧＡ(Land
GridArray)と呼ばれるパッケージも使用されるようにな
って来た。Further, in order to reduce the mounting height of the package after mounting, the LGA (Land) from which the BGA solder balls are removed as shown in FIGS.
A package called GridArray) has also been used.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、上記従
来例におけるＬＧＡでは、以下のような問題点があっ
た。However, the conventional LGA has the following problems.

【００１０】一つには、電極ピッチが狭ピッチとなるこ
とにより、電極部の面積が小さくなり接続強度が小さく
なり、プリント基板との接合をおこなった後の接合信頼
性が低下する。On the one hand, when the electrode pitch is narrow, the area of the electrode portion is reduced, the connection strength is reduced, and the bonding reliability after bonding to the printed circuit board is reduced.

【００１１】２つめには、はんだボールを介在せず、半
導体素子であるＩＣチップとプリント基板とが接続され
ているため、熱膨張係数の異なるＩＣチップ（Ｓｉ：α
＝３ｐｐｍ）とプリント基板（ＦＲ４：α＝１３〜１７
ｐｐｍ）の距離が近くなり両者の熱膨張係数のミスマッ
チによる熱応力が、接合強度の小さくなった接合部に直
接かかり、接合信頼性が低下する。Second, since an IC chip as a semiconductor element and a printed circuit board are connected without interposing a solder ball, an IC chip (Si: α) having a different coefficient of thermal expansion is used.
= 3 ppm) and printed circuit board (FR4: α = 13 to 17)
ppm), the thermal stress due to the mismatch between the thermal expansion coefficients of the two is directly applied to the joint having reduced joint strength, and the joint reliability is reduced.

【００１２】さらに、ＬＧＡでは、ＦＢＧＡなどのよう
にはんだボールによる基板とチップの間の間隔を広げ、
熱応力を吸収する緩衝部分を持たないことから、より強
い熱応力がはんだ接合部にかかることになる。Further, in the case of the LGA, the distance between the substrate and the chip is increased by solder balls, such as FBGA,
Since there is no buffer portion for absorbing the thermal stress, a stronger thermal stress is applied to the solder joint.

【００１３】３つめに、プリント基板と接合する際に
は、フラックス入りのクリームはんだがプリント基板の
各電極部上に印刷された上に、ＬＧＡパッケージが搭載
されリフロー炉で加熱され接合される。その接合の際に
は、フラックスの活性化作用でパッケージ電極部表面や
プリント基板電極部表面の酸化膜が除去され接合される
のであるが、はんだが加熱され溶融した際に、はんだ内
に気化したフラックスの溶剤分が混入しボイドとなる。
このボイドがはんだ内に留まると微細な接合面積が大幅
に低下し、接合信頼性を大幅に低下させる。Third, when bonding with a printed circuit board, a flux-containing cream solder is printed on each electrode portion of the printed circuit board, and then an LGA package is mounted thereon and heated and joined in a reflow furnace. At the time of the bonding, the oxide film on the surface of the package electrode and the surface of the printed circuit board was removed by the activation of the flux, and the bonding was performed.However, when the solder was heated and melted, it was vaporized in the solder. The solvent content of the flux is mixed to form voids.
If these voids remain in the solder, the fine bonding area is significantly reduced, and the bonding reliability is significantly reduced.

【００１４】４つめとしては、ＬＧＡは、電極部がパッ
ケージの保持体である基板（インターポーザー）から突
出していないため、実装される基板に反りやねじれ、う
ねりがあるとリフロー時に印刷されたクリームはんだ
と、ＬＧＡの電極とが、接することができず未接合とな
る。Fourth, since the LGA does not protrude from the substrate (interposer) serving as a package holder, if the substrate to be mounted is warped, twisted, or undulated, the cream printed during reflow is used. The solder and the electrode of the LGA cannot be in contact with each other and are not joined.

【００１５】従って、本発明は上述した課題に鑑みてな
されたものであり、その目的は、より高密度実装に適応
することができるエリアアレイ型半導体パッケージを提
供することである。Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an area array type semiconductor package which can be adapted to higher density mounting.

【００１６】[0016]

【課題を解決するための手段】上述した課題を解決し、
目的を達成するために、本発明に係わるエリアアレイ型
半導体パッケージは、絶縁性材料からなる保持部材の少
なくとも片面に導電性材料からなる配線が形成され、こ
の面上に半導体素子が搭載され、前記保持部材の他面側
にエリアアレイ状に配置された電極が形成されたエリア
アレイ型半導体パッケージにおいて、前記電極上に各々
突起部が設けられ、この突起部表面は、少なくともはん
だ材料が溶融し合金化して接合することが可能な材料か
らなることを特徴としている。Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, the area array type semiconductor package according to the present invention is configured such that a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface, In an area array type semiconductor package in which electrodes arranged in an area array shape are formed on the other surface side of the holding member, projections are respectively provided on the electrodes, and at least the surface of the projections is formed by melting the solder material and forming an alloy. It is characterized by being made of a material that can be formed and joined.

【００１７】また、本発明に係わるエリアアレイ型半導
体パッケージは、絶縁性材料からなる保持部材の少なく
とも片面に導電性材料からなる配線が形成され、この面
上に半導体素子が搭載され、前記保持部材の他面側にエ
リアアレイ状に配置された複数の電極が形成されたエリ
アアレイ型半導体パッケージにおいて、前記電極上に各
々突起部が設けられ、この突起部表面は、少なくともは
んだ材料が溶融し合金化して接合することが可能な材料
からなり、かつ、前記突起部は、少なくとも一部の頂上
部に平坦な部分が形成されていることを特徴としてい
る。In the area array type semiconductor package according to the present invention, a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface. In the area array type semiconductor package in which a plurality of electrodes arranged in an area array shape are formed on the other surface side, a protrusion is provided on each of the electrodes. The protrusion is made of a material that can be formed and joined, and the protrusion has a flat portion formed on at least a part of the top.

【００１８】また、本発明に係わるエリアアレイ型半導
体パッケージは、絶縁性材料からなる保持部材の少なく
とも片面に導電性材料からなる配線が形成され、この面
上に半導体素子が搭載され、前記保持部材の他面側にエ
リアアレイ状に配置された複数の電極が形成されたエリ
アアレイ型半導体パッケージにおいて、前記エリアアレ
イ状に配置された電極の各々の外周部に突起部が設けら
れ、該突起部の表面は、少なくともはんだ材料が溶融し
合金化して接合することが可能な材料からなることを特
徴としている。In the area array type semiconductor package according to the present invention, a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface. In the area array type semiconductor package in which a plurality of electrodes arranged in an area array are formed on the other surface side, a projection is provided on an outer peripheral portion of each of the electrodes arranged in the area array, and the projection is provided. Is characterized in that at least the surface is made of a material that can be joined by melting and alloying a solder material.

【００１９】また、本発明に係わるエリアアレイ型半導
体パッケージは、絶縁性材料からなる保持部材の少なく
とも片面に導電性材料からなる配線が形成され、この面
上に半導体素子が搭載され、前記保持部材の他面側にエ
リアアレイ状に配置された複数の電極が形成されたエリ
アアレイ型半導体パッケージにおいて、前記電極の各々
に複数の凹凸が設けられ、これら凹凸の表面は、少なく
ともはんだ材料が溶融し合金化して接合することが可能
な材料からなることを特徴としている。In the area array type semiconductor package according to the present invention, a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface. In an area array type semiconductor package in which a plurality of electrodes arranged in an area array shape are formed on the other surface side, a plurality of irregularities are provided on each of the electrodes, and at least the surface of these irregularities is formed by melting a solder material. It is characterized by being made of a material that can be joined by alloying.

【００２０】また、本発明に係わるエリアアレイ型半導
体パッケージは、絶縁性材料からなる保持部材の少なく
とも片面に導電性材料からなる配線が形成され、この面
上に半導体素子が搭載され、前記保持部材の他面側にエ
リアアレイ状に配置された複数の電極が形成されたエリ
アアレイ型半導体パッケージにおいて、前記電極上に各
々階段状の突起部が設けられ、該突起部の表面は、少な
くともはんだ材料が溶融し合金化して接合することが可
能な材料からなることを特徴としている。In the area array type semiconductor package according to the present invention, a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface. In the area array type semiconductor package in which a plurality of electrodes arranged in an area array are formed on the other surface side, a step-like projection is provided on each of the electrodes, and the surface of the projection is at least a solder material. Is made of a material that can be melted, alloyed, and joined.

【００２１】また、本発明に係わるエリアアレイ型半導
体パッケージは、絶縁性材料からなる保持部材の少なく
とも片面に導電性材料からなる配線が形成され、この面
上に半導体素子が搭載され、前記保持部材の他面側にエ
リアアレイ状に配置された複数の電極が形成されたエリ
アアレイ型半導体パッケージにおいて、前記エリアアレ
イ状に配置された電極のうち、少なくともパッケージコ
ーナー部に配置された電極が、前記保持部材の表面より
突出しており、この突出した表面は、少なくともはんだ
材料が溶融し合金化して接合することが可能な材料から
なることを特徴としている。Further, in the area array type semiconductor package according to the present invention, a wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, and a semiconductor element is mounted on this surface. In an area array type semiconductor package in which a plurality of electrodes arranged in an area array are formed on the other surface side, among the electrodes arranged in the area array, at least an electrode arranged in a package corner portion is the electrode. The protrusion protrudes from the surface of the holding member, and the protruding surface is made of a material that can be joined by melting and alloying at least the solder material.

【００２２】[0022]

【発明の実施の形態】以下、本発明の好適な実施形態に
ついて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below.

【００２３】まず、実施形態の概要について説明する。First, an outline of the embodiment will be described.

【００２４】本実施形態では、ＬＧＡタイプのエリアア
レイ型半導体パッケージの保持部材である基板の接合用
電極部に突起形状を持つことを特徴とする。This embodiment is characterized in that the bonding electrode portion of the substrate, which is the holding member of the LGA type area array type semiconductor package, has a projection shape.

【００２５】このように、電極面上に突出するように電
極を設けたことにより、溶融したはんだ内を上昇してき
たボイドは、突起電極面に達すると突起電極面に沿って
外側に排出されていき、はんだ外へ排出される。As described above, since the electrodes are provided so as to protrude above the electrode surface, the voids which have risen in the molten solder are discharged to the outside along the projecting electrode surface when they reach the projecting electrode surface. It is discharged out of the solder.

【００２６】また、はんだと接合される電極面積は、突
起形状となることで単純な平面での電極面積から大幅に
増加することから、電極が微細ピッチとなっても接合面
積を従来より大きくとれて、接合強度を高くすることが
可能となり接合信頼性を高くすることが可能となる。Further, since the area of the electrode to be joined to the solder is significantly increased from the electrode area on a simple plane due to the projection shape, the joining area can be made larger than before even if the electrodes have a fine pitch. Therefore, the joining strength can be increased, and the joining reliability can be enhanced.

【００２７】突起形状としては、電極面上に突出してい
れば形状は問わない。たとえば、円柱状や円錐状などが
あるがボイドの排出性と、はんだの接合部形状に急峻な
変化点を持たないことから滑らかな球形状が好ましい。The shape of the projection is not limited as long as it protrudes on the electrode surface. For example, there is a columnar shape or a conical shape, but a smooth spherical shape is preferable because the void discharging property and the solder joint shape do not have a sharp change point.

【００２８】また、いっぽうで上記のようななだらかな
形状のときは、はんだ接合部に入ったクラックが突起部
表面に沿って進行するが、突起形状を階段状や、のこぎ
り状とすることにより、接合部内部の形状が急激に変わ
っていることにより進行したクラックが、一時的に止ま
り、見かけ上のクラック進行の速さを遅くすることが可
能となり、完全破断にいたるまでの時間を長くできる。On the other hand, in the case of a gentle shape as described above, the cracks entering the solder joints progress along the surface of the projection, but by making the shape of the projection stepwise or saw-like, Cracks that have progressed due to abrupt changes in the shape of the inside of the joint temporarily stop, making it possible to slow the apparent rate of progress of the cracks, thereby increasing the time until complete fracture.

【００２９】さらに、熱変形時には、パッケージコーナ
ー部が、反り返りはんだ接合部にかかる応力の方向成分
に基板に対して垂直方向の成分が含まれる。突起部を階
段状やのこぎり状にした場合は、この応力方向に対し
て、基板に対して垂直方向にも接合部分を持つことによ
り、強い接合強度をもつことができ接合信頼性をより高
めることが可能である。Further, at the time of thermal deformation, a component in a direction perpendicular to the substrate is included in the direction component of the stress applied to the warped solder joint at the package corner. When the projection is stepped or saw-toothed, by having a joint in the direction perpendicular to the substrate with respect to this stress direction, strong joint strength can be achieved and joint reliability can be further improved. Is possible.

【００３０】さらに、これら突起を設ける電極部は全て
の電極でなくてもかまわない。特に熱応力が高いパッケ
ージコーナー部や、外周部のみに突起部を設けることに
より、必要な部分のみ接合強度を高めることができる。
このように部分的に突起部を持たせたことより、その他
の電極部はパッケージを水平面上に置いた場合、接する
ことがないことからパッケージの取り扱い中に電極部を
こすったり、傷をつけたりすることがなくなり接合信頼
性を低下させる外乱要因を排除することができる。その
際、突起電極は傷をつけるかもしれないが、接合面積が
大きいので接合強度の大幅な低下には結びつかない。Further, the electrode portions provided with these projections need not be all electrodes. In particular, by providing the projecting portion only at the package corner portion or the outer peripheral portion where the thermal stress is high, the joining strength can be increased only at a necessary portion.
Since the projections are partially provided in this manner, the other electrode portions do not touch when the package is placed on a horizontal surface, so that the electrode portions are rubbed or damaged during handling of the package. As a result, disturbance factors that lower the bonding reliability can be eliminated. At this time, the protruding electrode may be damaged, but does not lead to a significant decrease in bonding strength because the bonding area is large.

【００３１】一方、突起電極の頂点部をフラットにする
ことにより、ＬＧＡを実装する基板へマウンターにより
搭載する際、上記の単純な半球状の突起のように基板と
の接触が点接触でないことから、突起電極で滑ることが
なくなり、リフローにより接合するまでの間のパッケー
ジの位置安定性、特に、リフロー中での溶融したはんだ
に接している間での位置安定性が増大し、製造工程中の
位置ずれによる不良発生を防ぐことができる。On the other hand, when the apex of the protruding electrode is flattened, when the LGA is mounted on the substrate on which the LGA is mounted by using a mounter, the contact with the substrate is not point contact as in the case of the simple hemispherical protrusion. The position stability of the package before joining by reflow is eliminated, and the position stability during contact with the molten solder during reflow is increased. It is possible to prevent the occurrence of defects due to the displacement.

【００３２】このような突起部の高さとしては、０．０
１〜０．２ｍｍが望ましい。その理由としては、パッケ
ージとしてのＬＧＡの水平平坦性（コプラナリティ）が
０．０１〜０．０５ｍｍであるため、少なくともこの水
平平坦性以上の突起高さがないと、接合時に突起の一部
が接合される基板に接しない場合が発生する恐れが高く
なる。また、突出高さが０．２ｍｍより大きくなってく
ると、ハンダボール（直径φ０．３〜０．５ｍｍ）を用
いたＢＧＡタイプのパッケージに対して実装後のパッケ
ージ取り付け高さの優位性がなくなってくる。The height of such projections is 0.0
1 to 0.2 mm is desirable. The reason for this is that the horizontal flatness (coplanarity) of the LGA as a package is 0.01 to 0.05 mm. There is a high possibility that a case in which the substrate does not contact the substrate may occur. Further, when the protrusion height becomes larger than 0.2 mm, the superiority of the package mounting height after mounting to a BGA type package using solder balls (φ0.3 to 0.5 mm) is lost. Come.

【００３３】以下に、本実施形態の構成要素について具
体的説明をおこなう。The components of the present embodiment will be specifically described below.

【００３４】本実施形態における保持部材である基板
は、電気的絶縁性を有する材料であれば、有機材料、無
機材料を問わない。The substrate serving as the holding member in the present embodiment is not limited to an organic material or an inorganic material as long as the material has electrical insulation.

【００３５】有機材料としては、ポリイミド樹脂、エポ
キシ樹脂、ＢＴ樹脂、アラミド樹脂などがあり、半導体
素子の電極部とフィルム上に設けられた配線とを電気的
に接続する工程の温度から、一般には、高Ｔｇ温度の有
機樹脂材料が含浸されたガラスクロス材が使用され、そ
の厚みは、２０〜５００μｍである。Examples of the organic material include a polyimide resin, an epoxy resin, a BT resin, an aramid resin, and the like. Generally, the temperature of the step of electrically connecting the electrode portion of the semiconductor element and the wiring provided on the film depends on the temperature. A glass cloth material impregnated with an organic resin material having a high Tg temperature is used, and its thickness is 20 to 500 μm.

【００３６】また、無機材料としては通常のセラミック
基板の材料であるアルミナ（Ａｌ2Ｏ3）、窒化アルミ
（ＡｌＮ）などが使用される。As the inorganic material, alumina (Al 2 O 3 ), aluminum nitride (AlN), or the like, which is a material of a normal ceramic substrate, is used.

【００３７】配線材料としては、電気的導電性を有し、
かつはんだがぬれる性質を有していれば、材質は特には
問わない。具体的にはＣｕが一般には使用されており、
その厚みは１０〜２０μｍであり、半導体素子と配線と
をワイヤーボンディングにより接続する場合にはＣｕ上
の一部または全面にＮｉ／Ａｕ層をメッキにより２〜１
０μｍ／０．１〜１μｍ程度被覆する。The wiring material has electrical conductivity,
The material is not particularly limited as long as the solder has wettability. Specifically, Cu is generally used,
The thickness is 10 to 20 μm. When connecting the semiconductor element and the wiring by wire bonding, a Ni / Au layer is plated on a part or the entire surface of Cu by plating.
Coating is performed at about 0 μm / 0.1 to 1 μm.

【００３８】また、セラミック基板の場合は、Ｗペース
トを印刷し焼成後その表面に上記と同様にＮｉ／Ａｕメ
ッキする。In the case of a ceramic substrate, W paste is printed and fired, and the surface thereof is plated with Ni / Au in the same manner as described above.

【００３９】突起電極を形成する材料としては、導電性
材料でありかつ、はんだがぬれる材料であればよく、例
えばＣｕ、はんだ、Ｓｎ、Ｎｉ、Ａｕがあげられる。As a material for forming the protruding electrode, any material may be used as long as it is a conductive material and a material to which the solder can be wet, and examples thereof include Cu, solder, Sn, Ni, and Au.

【００４０】この突起電極の形成方法としては、保持部
材である基板の片面に形成された配線を介し、電解メッ
キにより形成できる。また、電極部にはんだペーストを
印刷し、リフローすることで電極上に溶融させて形成さ
せてもよい。さらに、セラミック基板の場合は、導体ペ
ーストを電極上に印刷し、焼成をすることにより形成
し、その後その表面をＮｉ／Ａｕで金メッキすることで
形成してもよい。さらに、上記の方法を複数回繰り返す
ことにより突起高さを高くしたり、印刷版の開口形状を
かえることにより、凹凸や階段状の突起部を形成するこ
とが可能である。以下、実施形態について、具体的に説
明する。As a method of forming the protruding electrode, the protruding electrode can be formed by electrolytic plating via a wiring formed on one surface of the substrate as a holding member. Alternatively, a solder paste may be printed on the electrode portion and may be melted and formed on the electrode by reflow. Further, in the case of a ceramic substrate, the conductive paste may be printed on the electrodes, fired, and then formed by gold plating the surface with Ni / Au. Further, by repeating the above method a plurality of times, it is possible to increase the height of the projections, or to change the shape of the opening of the printing plate, thereby forming irregularities or step-like projections. Hereinafter, embodiments will be specifically described.

【００４１】（第１の実施形態）図１は、本発明の第１
の実施形態に係わるエリアアレイ型半導体パッケージの
模式的断面図であり、図２は、エリアアレイ型半導体パ
ッケージをプリント基板に接合した状態を示す模式的断
面図である。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of the area array type semiconductor package according to the embodiment, and FIG. 2 is a schematic cross-sectional view showing a state where the area array type semiconductor package is joined to a printed circuit board.

【００４２】図１及び図２において、１は半導体素子で
あるＩＣチップ、２は絶縁性材料からなるガラスエポキ
シ基板、３はガラスエポキシ基板の両面に形成された配
線を電気的につなぐスルーホール部、４はパッケージと
基板との電気的接続を行うためのパッケージの電極部、
５は保護レジスト、６は半導体素子１をガラスエポキシ
基板２上に固定保持するボンディングペースト、７はＡ
ｕワイヤー、８はモールド樹脂、９は高融点はんだから
なる突起部、１０はパッケージと基板の電極部を接合す
るはんだ、１１はプリント基板である。In FIGS. 1 and 2, 1 is an IC chip as a semiconductor element, 2 is a glass epoxy substrate made of an insulating material, and 3 is a through hole portion for electrically connecting wirings formed on both sides of the glass epoxy substrate. 4 is an electrode part of the package for making electrical connection between the package and the substrate,
5, a protective resist; 6, a bonding paste for fixing and holding the semiconductor element 1 on the glass epoxy substrate 2;
u wire, 8 is a mold resin, 9 is a protrusion made of high melting point solder, 10 is solder for joining the package and the electrode of the board, and 11 is a printed board.

【００４３】まず、本実施形態によるエリアアレイ型半
導体パッケージの製造方法を説明する。First, the method for fabricating the area array type semiconductor package according to the present embodiment will be explained.

【００４４】本実施形態においては、まず、通常のプリ
ント基板の製造方法と同様に、両面に銅箔が設けられた
ガラスエポキシ基板の所望の位置にドリルにて貫通穴を
形成し、無電解めっき、電解めっきによりスルーホール
３を形成後、このスルーホール内を樹脂により埋め込
み、再度無電解めっき、電解めっきをおこなった後に、
それぞれの面に所望のパターンを露光、エッチングによ
り形成する。その後、基板との接続用電極部４をもつ面
上に保護レジスト５を塗布、露光、現像し電極部４のみ
が露出する基板を形成する。In this embodiment, first, a through hole is formed at a desired position on a glass epoxy substrate having copper foils on both sides by a drill in the same manner as in a normal printed circuit board manufacturing method. After forming the through hole 3 by electrolytic plating, the inside of the through hole is filled with a resin, and after performing electroless plating and electrolytic plating again,
A desired pattern is formed on each surface by exposure and etching. After that, a protective resist 5 is applied, exposed, and developed on the surface having the electrode portion 4 for connection with the substrate to form a substrate in which only the electrode portion 4 is exposed.

【００４５】つぎに、このプリント基板上にダイボンデ
ィングペースト６を塗布し、その上に半導体素子１を載
せ、ダイボンディングペーストを加熱硬化し、半導体素
子１をプリント基板２上に固着させる。そして、ワイヤ
ーボンディングを用いてＡｕワイヤー７により、半導体
素子１の電極部とプリント基板２の半導体素子１が搭載
された面に設けられた電極部とを接続する。Next, a die bonding paste 6 is applied on the printed board, the semiconductor element 1 is mounted thereon, and the die bonding paste is heated and cured to fix the semiconductor element 1 on the printed board 2. Then, the electrode part of the semiconductor element 1 and the electrode part provided on the surface of the printed circuit board 2 on which the semiconductor element 1 is mounted are connected by the Au wire 7 using wire bonding.

【００４６】その後、半導体素子１とＡｕワイヤー７を
外界から保護するために、トランスファーモールドでモ
ールド樹脂８により、半導体素子１を封止する。Thereafter, in order to protect the semiconductor element 1 and the Au wire 7 from the outside, the semiconductor element 1 is sealed with a molding resin 8 by transfer molding.

【００４７】その後、プリント基板２の電極部４上に印
刷版を用いてクリームはんだを印刷し、リフロー工程に
より印刷したはんだの融点以上に加熱し、印刷されたは
んだを溶融させ、電極４と接合させる。その際、本実施
形態においては、電極部４のピッチを０．８ｍｍ、電極
部サイズを直径φ０．４ｍｍとしたので、使用した印刷
版の寸法は、厚さｔ＝０．１５ｍｍ、開口径φ０．４ｍ
ｍにし、転写されたペースト量は、約０．０１９ｍｍ3
で、はんだ量としては、その約５０％である０．０１ｍ
ｍ3となる。溶融したはんだは、電極部４のＣｕにぬれ
広がるが、供給されたはんだ量に対して電極部面積が小
さく、かつ保護レジスト５で水平方向へのぬれ広がりを
規制されていることと、はんだの表面張力により、平坦
に約０．０６ｍｍ〜０．０８ｍｍの厚さで盛り上がるの
ではなく、電極部４の中心部が凸になるような形にな
る。本実施形態の場合では、突起頂点部の高さは、０．
１〜０．２ｍｍとなった。この高さを調整したい場合
は、印刷するはんだ量を変えるだけでよく、開口径、版
厚のいずれか、あるいは両方にて調整する。Thereafter, cream solder is printed on the electrode portion 4 of the printed circuit board 2 using a printing plate, and the solder is heated to a melting point of the printed solder by a reflow process to melt the printed solder and join the electrode 4. Let it. In this case, in the present embodiment, the pitch of the electrode portions 4 was 0.8 mm, and the electrode portion size was 0.4 mm in diameter. Therefore, the dimensions of the printing plate used were a thickness t = 0.15 mm and an opening diameter φ0. .4m
m, and the transferred paste amount is about 0.019 mm 3
The amount of solder is about 50% of that, 0.01 m
m 3 . The molten solder wets and spreads on the Cu of the electrode portion 4, but the area of the electrode portion is small with respect to the supplied amount of solder, and the wetting and spreading of the solder in the horizontal direction is controlled by the protective resist 5; Due to the surface tension, the electrode portion 4 does not swell flatly with a thickness of about 0.06 mm to 0.08 mm, but has a shape in which the central portion of the electrode portion 4 becomes convex. In the case of the present embodiment, the height of the apex of the protrusion is 0.1 mm.
1 to 0.2 mm. To adjust the height, it is only necessary to change the amount of solder to be printed, and the height is adjusted by either one or both of the opening diameter and the plate thickness.

【００４８】このようにして、電極部４上に突起部９を
形成する。Thus, the projection 9 is formed on the electrode 4.

【００４９】なお、本実施形態では、後に述べるプリン
ト基板１１と上記の半導体パッケージとの接合に共晶は
んだ（融点１８３℃）を使い、接合する際のリフロー温
度が２０５〜２４０℃になるので、この温度で溶融しな
いはんだ材を用いて突起部９を作る。In this embodiment, eutectic solder (melting point: 183 ° C.) is used for joining the printed board 11 and the above-mentioned semiconductor package, which will be described later, and the reflow temperature at the time of joining becomes 205 to 240 ° C. The projection 9 is formed using a solder material that does not melt at this temperature.

【００５０】例えば、Ｓｎ：２３２℃、Ｓｎ−５Ａｇ：
２３４〜２４０℃、Ｓｎ−３．５Ａｇ：２２１℃、Ｓｎ
−６Ａｇ：２２１〜２４５℃、Ｓｎ−３．５Ａｇ−０．
５Ｃｕ：２１６〜２１８℃などが使用可能であり、これ
以外にも多数の合金が使用できる。ただし、この突起部
に使用する合金材料としては、後のはんだ付けの際に共
晶系はんだと溶融しなければならない。For example, Sn: 232 ° C., Sn-5Ag:
234 to 240 ° C, Sn-3.5Ag: 221 ° C, Sn
-6Ag: 221-245 ° C, Sn-3.5Ag-0.
5Cu: 216 to 218 ° C. can be used, and many other alloys can be used. However, the alloy material used for this projection must be melted with the eutectic solder at the time of subsequent soldering.

【００５１】このようにして製作された半導体パッケー
ジが、図１に示されるものである。The semiconductor package manufactured as described above is shown in FIG.

【００５２】このようにして製作された半導体パッケー
ジは、プリント基板１１上に設けられた半導体パッケー
ジに対応する位置の電極上にはんだペーストを印刷した
後に、マウンターにて印刷されたはんだペースト上に突
起電極部が対向するように位置あわせ後搭載され、リフ
ロー炉によりはんだペーストの融点以上で、突起電極９
を構成する材料の融点以下に加熱することで、はんだペ
ーストを溶融させ、突起電極９とプリント基板１１の電
極の両方とはんだ１０を接合させる。In the semiconductor package manufactured in this manner, after the solder paste is printed on the electrode at the position corresponding to the semiconductor package provided on the printed circuit board 11, the projection is formed on the solder paste printed by the mounter. It is mounted after positioning so that the electrode portions face each other.
Is heated to a temperature equal to or lower than the melting point of the material constituting the solder paste, thereby melting the solder paste and joining the solder 10 to both the bump electrodes 9 and the electrodes of the printed circuit board 11.

【００５３】このようにして接合された半導体パッケー
ジは、動作ＯＮ／ＯＦＦ時の半導体素子の温度変化に伴
い、すでに述べたように半田接合部の上下部分に熱応力
が加わるが、従来のＬＧＡ型半導体パッケージに対し、
大幅に接合面積が増加しているため、熱応力に対して強
い耐性をもつ。In the semiconductor package joined in this manner, thermal stress is applied to the upper and lower portions of the solder joint as described above with the temperature change of the semiconductor element at the time of operation ON / OFF. For semiconductor packages,
Since the joining area is greatly increased, it has strong resistance to thermal stress.

【００５４】さらに、接合端から接合端までの距離は、
従来では電極部の直径が最も長い接合端から接合端まで
の直線的な距離であったが、本実施形態では、突起の頂
点を通る曲線になっており、長くなっている。したがっ
て、はんだ接合部にクラックが入ったとしても、クラッ
クが進行し、接合部を完全に破断するまでの時間が長く
なり、同一のピッチ、電極サイズであれば、信頼性がよ
り高くなる。Further, the distance from the joint end to the joint end is
Conventionally, the diameter of the electrode portion was a linear distance from the longest joint end to the joint end, but in the present embodiment, it is a curve passing through the apex of the protrusion and is longer. Therefore, even if a crack is formed in the solder joint, the crack progresses, and the time until the joint is completely broken becomes longer. If the pitch and the electrode size are the same, the reliability becomes higher.

【００５５】さらに、本実施形態においては、エリアア
レイ型半導体パッケージをプリント基板１１に接合する
場合、プリント基板１１の電極上に印刷されたクリーム
はんだのフラックスから発生するフラックスボイドが、
溶融中のはんだ内を上昇し、突起電極に達すると突起電
極面に沿って外に排出されることから、接合部にフラッ
クスボイドのない高品質の接合をおこなえる。Further, in the present embodiment, when the area array type semiconductor package is joined to the printed circuit board 11, the flux void generated from the flux of the cream solder printed on the electrode of the printed circuit board 11 is:
Since the solder rises in the molten solder and reaches the protruding electrode and is discharged to the outside along the protruding electrode surface, high-quality bonding without a flux void at the bonding portion can be performed.

【００５６】そのため、接合後の接合信頼性を飛躍的に
向上させることが可能となる。Therefore, it is possible to dramatically improve the bonding reliability after bonding.

【００５７】（第２の実施形態）図３は、本発明の第２
の実施形態を示す模式的断面図であり、同図において１
２は突起部９の頂点に形成されたフラット部である。(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
1 is a schematic sectional view showing an embodiment of the present invention, and FIG.
Reference numeral 2 denotes a flat portion formed at the top of the protrusion 9.

【００５８】本実施形態では、第１の実施形態で示した
エリアアレイ型半導体パッケージの製造方法において、
突起部の形成までの工程は、第１の実施形態と同様に製
造される。In the present embodiment, in the method of manufacturing the area array type semiconductor package shown in the first embodiment,
The steps up to the formation of the protrusion are manufactured in the same manner as in the first embodiment.

【００５９】つぎに、本実施形態では加熱プレスにより
突起部９が形成された電極部を加熱、加圧することで、
突起部を形成する材料を軟化させ突起部９の頂上部にフ
ラット部１２を形成する。Next, in the present embodiment, the electrode portion on which the protrusions 9 are formed is heated and pressed by a heating press, whereby
The material forming the protrusion is softened to form a flat portion 12 on the top of the protrusion 9.

【００６０】その後の工程は、第１の実施形態と同じで
ある。The subsequent steps are the same as in the first embodiment.

【００６１】本実施形態では、図３に示すように、突起
部９に平坦部１２を有することにより、半導体パッケー
ジをプリント基板１１上にマウントし、接合するまで第
１の実施形態の様な曲面同士の点接触ではなく、平面と
平面の接触となる。In the present embodiment, as shown in FIG. 3, the projection 9 has the flat portion 12 so that the semiconductor package is mounted on the printed circuit board 11 and has a curved surface as in the first embodiment until it is joined. It is not a point contact between each other but a plane-to-plane contact.

【００６２】そのため、電極部に接合させるリフロー工
程において加熱された際、はんだペーストが軟化、溶融
しはんだの保持力が低下し、ベルトの振動、温風風圧な
どの外乱要因により、パッケージの位置ずれの発生を防
ぐことが可能となる。Therefore, when heated in the reflow step of joining to the electrode portion, the solder paste softens and melts, and the solder holding force is reduced, and the package is misaligned due to disturbance factors such as belt vibration and hot air pressure. Can be prevented from occurring.

【００６３】図４に示すように電極部４の表面に突出す
る部分をもつことで、はんだ１０との接合面積がより大
きくなり接合強度が高くなり、接合信頼性をより高くす
ることが可能となるのは、第１の実施形態と同様であ
る。As shown in FIG. 4, by having a protruding portion on the surface of the electrode portion 4, the bonding area with the solder 10 is increased, the bonding strength is increased, and the bonding reliability can be further improved. This is the same as in the first embodiment.

【００６４】（第３の実施形態）図５は、本発明の第３
の実施形態を示す模式的平面図であり、図６、図７は本
発明の第３の実施形態を示す模式的断面図である。(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 6 and FIG. 7 are schematic cross-sectional views showing a third embodiment of the present invention.

【００６５】本実施形態においては、配線と接続用電極
部が形成されたセラミック基板１５に半導体素子１をフ
リップチップ接続にて接合したＬＧＡパッケージであ
る。The present embodiment is an LGA package in which the semiconductor element 1 is bonded to the ceramic substrate 15 on which the wiring and the connection electrode portion are formed by flip-chip connection.

【００６６】本実施形態では、通常のセラミック基板１
５の焼成後に電極部４の外局部にリング状になるように
導体ペースト１３（例えばＷ）を印刷し、再度焼成した
後、導体部を電気メッキして、バリア層のＮｉと表面層
のＡｕを設ける。In this embodiment, the ordinary ceramic substrate 1
After the firing of 5, the conductive paste 13 (for example, W) is printed in a ring shape on the outer portion of the electrode portion 4 and fired again. Then, the conductive portion is electroplated to obtain Ni of the barrier layer and Au of the surface layer. Is provided.

【００６７】その後、完成したセラミック基板１５に半
導体素子１をフリップチップ接合し、半導体素子１とセ
ラミック基板１５の間にアンダフィル樹脂１４を注入、
加熱硬化させ半導体パッケージを製作する。Thereafter, the semiconductor element 1 is flip-chip bonded to the completed ceramic substrate 15, and an underfill resin 14 is injected between the semiconductor element 1 and the ceramic substrate 15.
Heat and cure to produce a semiconductor package.

【００６８】本実施形態では、電極部４に凹部をもった
ことで、より接合面積が広くなり接合強度が高くなるだ
けでなく、横方向に対して凹凸を持った接合であること
から、電極形状によるアンカー効果が生まれより接合強
度が高くなり、接合信頼性が上がる。In the present embodiment, since the electrode portion 4 has a concave portion, not only the bonding area is increased and the bonding strength is increased, but also the bonding has unevenness in the lateral direction. Anchoring effect is generated by the shape, and the joining strength is increased and the joining reliability is increased.

【００６９】また、パッケージとプリント基板の熱膨張
係数差によるパッケージの反りといった基板に垂直方向
の変位・力がコーナー部の電極を含めてかかる際、垂直
方向に対しての接合面積をもつことから、この基板に垂
直方向の応力に対して極めて高い接合信頼性を持つこと
になり、パッケージとしての接合信頼性がより向上す
る。Further, when a vertical displacement / force such as warpage of the package due to a difference in thermal expansion coefficient between the package and the printed board is applied to the substrate including the electrodes at the corners, the substrate has a bonding area in the vertical direction. Therefore, the substrate has extremely high bonding reliability against stress in the direction perpendicular to the substrate, and the bonding reliability as a package is further improved.

【００７０】（第４の実施形態）図８は、本発明の第４
の実施形態を示す模式的平面図であり、図９、図１０は
本発明の第３の実施形態を示す模式的断面図である。(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 9 and FIG. 10 are schematic cross-sectional views illustrating a third embodiment of the present invention.

【００７１】本実施形態においては、第３の実施形態と
同様に配線と接続用電極部が形成されたセラミック基板
１５に半導体素子１をフリップチップ接続にて接合した
ＬＧＡパッケージである。This embodiment is an LGA package in which the semiconductor element 1 is joined by flip-chip connection to a ceramic substrate 15 on which wiring and connection electrode portions are formed as in the third embodiment.

【００７２】本実施形態においては、電極部４の外周部
だけでなく、中心部にも突起部１３を有している。In the present embodiment, the projections 13 are provided not only at the outer peripheral portion of the electrode portion 4 but also at the central portion.

【００７３】製造方法としては、第３の実施形態の突起
を設ける印刷時の版の開口部に、各電極中心部にも開口
を有したものを用いるだけでよく、それ以降の工程も第
３の実施形態と同じである。As a manufacturing method, it is only necessary to use a plate having an opening at the center of each electrode in the plate opening at the time of printing in which the projections of the third embodiment are provided. This is the same as the embodiment.

【００７４】本実施形態においては、図１０に示すよう
にＬＧＡパッケージの電極部４に突起部１３が増えたこ
とにより、さらに接合面積が増大し、接合強度が増し、
接合信頼性が向上する。In this embodiment, as shown in FIG. 10, the number of protrusions 13 on the electrode portion 4 of the LGA package increases, so that the bonding area further increases, and the bonding strength increases.
The joining reliability is improved.

【００７５】さらに、図１０に示すようなはんだ接合部
の接合断面は、凹凸を有しており横方向の変形に対し
て、アンカー効果により横方向の高い接合強度が得られ
る。そのため、振動、落下といった単純な機械強度にお
いても優れた効果が得られる。Further, the joint section of the solder joint as shown in FIG. 10 has irregularities, and high lateral joint strength can be obtained by an anchor effect against lateral deformation. Therefore, excellent effects can be obtained even with simple mechanical strength such as vibration and dropping.

【００７６】（第５の実施形態）図１１は、本発明の第
５の実施形態を示す模式的断面図であり、図１２は本発
明による第５の実施形態によるパッケージとプリント基
板とを接合した模式的断面図である。(Fifth Embodiment) FIG. 11 is a schematic sectional view showing a fifth embodiment of the present invention, and FIG. 12 is a diagram for joining a package and a printed circuit board according to the fifth embodiment of the present invention. FIG.

【００７７】本実施形態においては、第３の実施形態と
同様に、各電極部４の上に電極部の大きさより小さい開
口を持つ版により１段目の導体ペーストを印刷、焼成
し、次に最初の開口径より小さい開口径をもつ第２の版
により２段目を形成する。なお、２段目を形成する際、
１段目を完全に焼成せず、仮硬化させその上に２段目を
印刷した後、１段目と２段目を焼成してもよい。In the present embodiment, as in the third embodiment, the first-stage conductor paste is printed and fired on a plate having an opening smaller than the size of the electrode portion on each electrode portion 4 and then baked. The second stage is formed by a second plate having an opening diameter smaller than the first opening diameter. When forming the second stage,
The first stage and the second stage may be calcined after the first stage is preliminarily cured and printed on the second stage without completely firing.

【００７８】その後、メッキにより表面にＮｉ／Ａｕ層
を形成する。Thereafter, a Ni / Au layer is formed on the surface by plating.

【００７９】本実施形態によれば、図１２に示すように
電極部に設けられた突起１６は階段状となっており、熱
応力により発生するクラックは、電極部４の端部から横
方向に進み１段目の側部に突き当たり、横方向への進行
を阻止される。According to the present embodiment, as shown in FIG. 12, the projections 16 provided on the electrode portion are stepped, and cracks generated by thermal stress are generated in the lateral direction from the end of the electrode portion 4. When the vehicle collides with the side of the first stage, the vehicle is prevented from moving in the lateral direction.

【００８０】その後、温度上昇、下降が繰り返されると
止まっていたクラック端部のクラック部が大きくなり１
段目の側壁部を越え、再び横方向へ進行できるようにな
り、今度は、２段目の側壁に突き当たり進行が止まる。
以降は、同じ繰り返しになる。Thereafter, when the temperature was repeatedly increased and decreased, the crack portion at the end of the crack, which had stopped, became large, and
After passing over the side wall of the second stage, the vehicle can travel in the lateral direction again.
Thereafter, the same repetition is performed.

【００８１】このように、本実施形態では、突起電極の
側壁にクラックが突き当たると、その段を乗り越えてク
ラックが進行するまでに時間がかかることから、接合信
頼性を向上させることができる。As described above, in the present embodiment, if a crack hits the side wall of the bump electrode, it takes time until the crack progresses over the step, so that the bonding reliability can be improved.

【００８２】さらに、プリント基板１１にパッケージが
接合され熱膨張係数差がある場合に発生するパッケージ
コーナー部の反りといった垂直方向の応力に対しての垂
直方向の接合面積を多く得ることができるので、接合信
頼性を向上させることができる。Further, since a package can be bonded to the printed circuit board 11 and a large vertical bonding area can be obtained with respect to vertical stress such as warpage of a package corner generated when there is a difference in thermal expansion coefficient. Joint reliability can be improved.

【００８３】接合面積の増大により接合強度が向上する
ことから、さらに電極部面積を小型にすることも可能と
なり、より微細ピッチの接合が高い信頼性をもって行え
る。そのため、より一層のパッケージの小型化や、多ピ
ン化に対応することが可能となる。Since the bonding strength is improved by increasing the bonding area, the area of the electrode portion can be further reduced, and bonding at a finer pitch can be performed with high reliability. Therefore, it is possible to cope with further downsizing of the package and increase in the number of pins.

【００８４】（第６の実施形態）図１３は、本発明の第
６の実施形態を示す模式的平面図であり、図１４、図１
５は本発明の第６の実施形態を示す模式的断面図であ
る。(Sixth Embodiment) FIG. 13 is a schematic plan view showing a sixth embodiment of the present invention.
FIG. 5 is a schematic sectional view showing a sixth embodiment of the present invention.

【００８５】本実施形態においては、第３の実施形態と
同様に配線と接続用電極部が形成されたセラミック基板
１５に半導体素子１をフリップチップ接続にて接合した
ＬＧＡパッケージである。This embodiment is an LGA package in which the semiconductor element 1 is joined by flip-chip connection to a ceramic substrate 15 on which wiring and connection electrode portions are formed as in the third embodiment.

【００８６】本実施形態においては、パッケージコーナ
ー部の電極部４のみが突起部を有している。突起の形成
方法は、第１の実施形態のはんだペーストを用いて、電
極部４上にて加熱溶融させることで、曲面状の突起部を
得ている。In this embodiment, only the electrode portion 4 at the package corner has a projection. In the method of forming the protrusions, the solder paste of the first embodiment is used to heat and melt on the electrode portions 4 to obtain curved protrusions.

【００８７】本実施形態では、最も大きな熱応力のかか
る部分であるコーナー部のみに突起部９を設けている。
このようにすることで、１つには、突起部形成数を減ら
しコストダウンが図られるだけでなく、電極部の一部の
みに突起を形成したことで、その他の電極部表面がハン
ドリング中に接触し、汚染されたり、傷がついたりする
ことを防ぐことができる。そのため、不安定な接合状態
で接合される電極部の数が減り、安定した接合が得られ
る。In this embodiment, the protruding portions 9 are provided only at the corners where the greatest thermal stress is applied.
In this way, for one thing, not only is the number of projections formed reduced and cost is reduced, but also because the projections are formed only on a part of the electrode parts, the surface of the other electrode parts is handled during handling. Contact, contamination and scratching can be prevented. Therefore, the number of electrode portions to be joined in an unstable joining state is reduced, and stable joining is obtained.

【００８８】また、図１６、図１７、図１８に示すよう
な第５の実施形態と同様の階段状の突起を設けても同様
の効果を得ることができるのは、自明である。It is self-evident that the same effect can be obtained by providing a step-like projection similar to that of the fifth embodiment as shown in FIG. 16, FIG. 17, and FIG.

【００８９】また、図１９に示すように、コーナー部の
電極部の大きさは、他の電極部より大きければ、より大
きな効果を得ることができるし、電極部形状に関しても
円形である必然性は、低く四角を含め多角形であっても
よい。As shown in FIG. 19, if the size of the electrode portion at the corner portion is larger than that of the other electrode portions, a greater effect can be obtained, and the shape of the electrode portion need not be circular. Alternatively, it may be a polygon including a low square.

【００９０】さらに、図２０に示すように、コーナー部
だけでなく、応力の大きい領域の電極部に突起を設ける
ことも可能である。Further, as shown in FIG. 20, it is also possible to provide projections not only at the corners but also at the electrodes in the region where the stress is large.

【００９１】図２０では、突起部はパッケージコーナー
部に重点的に配置してあるが、それ以外に高い応力発生
個所としては、Ｓｉチップ端部の下にある電極部があ
る。このチップ端に該当する電極部としては、完全にチ
ップ端部に電極部が相当していなくてもよく、端部周辺
にある電極部をさしている。なお、どちらかというとチ
ップ端部から外側の電極部の方が、チップ端部の内側の
電極部よりかかる熱応力値は、大きくなる。In FIG. 20, the protruding portions are arranged intensively at the package corners, but other high stress generating portions are the electrode portions below the ends of the Si chip. As the electrode portion corresponding to the chip end, the electrode portion may not completely correspond to the chip end portion, but refers to the electrode portion around the end portion. It is to be noted that the thermal stress applied to the electrode part outside the chip end is larger than that of the electrode part inside the chip end.

【００９２】したがって、突起部を設けるとすれば、チ
ップ端部から内側より、外側のほうに設けることが接合
信頼性を高める効果がより得られることになる。Therefore, if the protrusions are provided, the provision of the protrusions on the outer side rather than on the inner side from the end of the chip has the effect of improving the bonding reliability.

【００９３】以上説明したように、上記の第１乃至第６
の実施形態によれば、プリント基板と接合する際にはん
だとの接合面積を増やすことが可能となり、接合強度を
大きくすることが可能となる。As described above, the above-described first to sixth embodiments
According to the embodiment, it is possible to increase a bonding area with solder when bonding with a printed board, and to increase bonding strength.

【００９４】また、パッケージ側接合部に集まるフラッ
クスボイドを排出でき、安定した接合を行える。Further, flux voids gathered at the package-side joint can be discharged, and stable joining can be performed.

【００９５】さらに、突起電極を包み込むようにはんだ
が接合されることから、はんだ形状の急激な変曲部をも
たず応力が集中しにくくなることから、接合信頼性を高
くすることが可能となる。Furthermore, since the solder is joined so as to enclose the protruding electrodes, stress does not easily concentrate without a sharp inflection of the solder shape, so that the joining reliability can be improved. Become.

【００９６】突起部に平坦部を設けると、はんだを接合
する際のパッケージの位置安定性が向上し、安定した接
合特性をもったエリアアレイ型半導体パッケージを製造
することが可能となり、製造歩留まりが上がり、コスト
ダウンが可能となる。By providing a flat portion on the protrusion, the positional stability of the package at the time of joining the solder is improved, and an area array type semiconductor package having stable joining characteristics can be manufactured, and the manufacturing yield is reduced. And cost can be reduced.

【００９７】階段状の突起電極を有することにより、ク
ラックの進行を遅らせることが可能となり、より高信頼
性の半導体パッケージを得ることが可能となる。The provision of the step-like projecting electrodes makes it possible to delay the progress of cracks, and to obtain a more reliable semiconductor package.

【００９８】特定の位置のみに突起を設けることが可能
であることから、露出する電極の数を減らすことが可能
となり、ハンドリング時の汚染、傷を最小限に抑え、接
合安定性を高く保ち、かつ接合信頼性に関しても高くす
ることが可能となる。Since the projection can be provided only at a specific position, it is possible to reduce the number of exposed electrodes, minimize contamination and scratches during handling, maintain high bonding stability, In addition, it is possible to increase the bonding reliability.

【００９９】突起電極により接合面積を大きくすること
が可能となったことにより、より電極面積を小型にでき
る。そのため、電極のピッチをより狭くすることがで
き、パッケージの更なる小型化、あるいは多ピン化に対
応することが可能となり、製品のより一層の小型、軽量
化を行うことが可能となる。Since the bonding area can be increased by the protruding electrodes, the electrode area can be further reduced. Therefore, the pitch of the electrodes can be narrowed, and the package can be further downsized or the number of pins can be increased, and the product can be further reduced in size and weight.

【０１００】[0100]

【発明の効果】以上説明したように、本発明によれば、
より高密度実装に適応することができるエリアアレイ型
半導体パッケージが実現される。As described above, according to the present invention,
An area array type semiconductor package adaptable to higher density mounting is realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態に係わるエリアアレイ
型半導体パッケージの模式的断面図である。FIG. 1 is a schematic sectional view of an area array type semiconductor package according to a first embodiment of the present invention.

【図２】第１の実施形態のエリアアレイ型半導体パッケ
ージをプリント基板に接合した状態を示す模式的断面図
である。FIG. 2 is a schematic cross-sectional view showing a state where the area array type semiconductor package according to the first embodiment is joined to a printed circuit board.

【図３】第２の実施形態を示す模式的断面図である。FIG. 3 is a schematic sectional view showing a second embodiment.

【図４】第２の実施形態の半導体パッケージとプリント
基板とを接合した状態を示す摸式的断面図である。FIG. 4 is a schematic cross-sectional view showing a state where a semiconductor package of a second embodiment and a printed circuit board are joined.

【図５】第３の実施形態の半導体パッケージの電極部の
配置を示す模式的上面図である。FIG. 5 is a schematic top view illustrating an arrangement of electrode portions of a semiconductor package according to a third embodiment.

【図６】第３の実施形態を示す模式的断面図である。FIG. 6 is a schematic sectional view illustrating a third embodiment.

【図７】第３の実施形態の半導体パッケージとプリント
基板とを接合した状態を示す模式的断面図である。FIG. 7 is a schematic cross-sectional view showing a state where a semiconductor package according to a third embodiment and a printed circuit board are joined.

【図８】第４の実施形態の半導体パッケージの電極部の
配置を示す模式的上面図である。FIG. 8 is a schematic top view illustrating an arrangement of electrode portions of a semiconductor package according to a fourth embodiment.

【図９】第４の実施形態を示す模式的断面図である。FIG. 9 is a schematic sectional view showing a fourth embodiment.

【図１０】第４の実施形態の半導体パッケージとプリン
ト基板とを接合した状態を示す模式的断面図である。FIG. 10 is a schematic cross-sectional view showing a state where a semiconductor package according to a fourth embodiment and a printed circuit board are joined.

【図１１】第５の実施形態を示す模式的断面図である。FIG. 11 is a schematic sectional view showing a fifth embodiment.

【図１２】第５の実施形態の半導体パッケージとプリン
ト基板とを接合した状態を示す模式的断面図である。FIG. 12 is a schematic cross-sectional view showing a state where the semiconductor package of the fifth embodiment and a printed board are joined.

【図１３】第６の実施形態の半導体パッケージの電極部
の配置を示す模式的上面図である。FIG. 13 is a schematic top view showing an arrangement of electrode portions of a semiconductor package according to a sixth embodiment.

【図１４】第６の実施形態を示す模式的断面図である。FIG. 14 is a schematic cross-sectional view showing a sixth embodiment.

【図１５】第６の実施形態の半導体パッケージとプリン
ト基板とを接合した状態を示す模式的断面図である。FIG. 15 is a schematic cross-sectional view showing a state where a semiconductor package according to a sixth embodiment and a printed circuit board are joined.

【図１６】第６の実施形態の別形態による半導体パッケ
ージの電極部の配置を示す模式的上面図である。FIG. 16 is a schematic top view showing an arrangement of electrode portions of a semiconductor package according to another mode of the sixth embodiment.

【図１７】第６の実施形態の別形態を示す模式的断面図
である。FIG. 17 is a schematic sectional view showing another form of the sixth embodiment.

【図１８】第６の実施形態の別形態による半導体パッケ
ージとプリント基板とを接合した状態を示す模式的断面
図である。FIG. 18 is a schematic sectional view showing a state in which a semiconductor package and a printed circuit board according to another form of the sixth embodiment are joined.

【図１９】第６の実施形態の別形態による半導体パッケ
ージの電極部の配置を示す模式的上面図である。FIG. 19 is a schematic top view showing an arrangement of electrode portions of a semiconductor package according to another mode of the sixth embodiment.

【図２０】第６の実施形態の別形態による半導体パッケ
ージの電極部の配置を示す模式的上面図である。FIG. 20 is a schematic top view showing an arrangement of electrode portions of a semiconductor package according to another mode of the sixth embodiment.

【図２１】従来のＬＧＡ半導体パッケージ構造を示す模
式的断面図である。FIG. 21 is a schematic sectional view showing a conventional LGA semiconductor package structure.

【図２２】従来のＬＧＡ半導体パッケージとプリント基
板とを接合した状態を示す模式的断面図である。FIG. 22 is a schematic cross-sectional view showing a state in which a conventional LGA semiconductor package and a printed board are joined.

【符号の説明】[Explanation of symbols]

１ 半導体素子 ２ ガラスエポキシ基板 ３ スルーホール部 ４ 電極部 ５ 保護レジスト ６ ダイボンディングペースト ７ Ａｕワイヤー ８ モールド樹脂 ９ 突起部 １０ はんだ １１ プリント基板 １２ フラット部 １３ 突起部 １４ アンダーフィル材 １５ セラミック基板 １６ 階段状突起 １７ ポリイミドテープ DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Glass epoxy board 3 Through hole part 4 Electrode part 5 Protective resist 6 Die bonding paste 7 Au wire 8 Mold resin 9 Projection part 10 Solder 11 Printed circuit board 12 Flat part 13 Projection part 14 Underfill material 15 Ceramic substrate 16 Stairs Projection 17 Polyimide tape

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された電極が形成されたエリアアレイ
型半導体パッケージにおいて、 前記電極上に各々突起部が設けられ、この突起部表面
は、少なくともはんだ材料が溶融し合金化して接合する
ことが可能な材料からなることを特徴とするエリアアレ
イ型半導体パッケージ。1. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and is arranged in an area array on the other surface of the holding member. In the area array type semiconductor package having the electrodes formed thereon, a protrusion is provided on each of the electrodes, and the surface of the protrusion is made of a material that can be joined by melting and alloying at least the solder material. Characteristic area array type semiconductor package. 【請求項２】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された複数の電極が形成されたエリア
アレイ型半導体パッケージにおいて、 前記電極上に各々突起部が設けられ、この突起部表面
は、少なくともはんだ材料が溶融し合金化して接合する
ことが可能な材料からなり、かつ、前記突起部は、少な
くとも一部の頂上部に平坦な部分が形成されていること
を特徴とするエリアアレイ型半導体パッケージ。2. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and is arranged in an area array on the other surface of the holding member. In the area array type semiconductor package in which a plurality of electrodes are formed, a projection is provided on each of the electrodes, and the surface of the projection is made of a material capable of joining at least by melting and alloying a solder material. An area array type semiconductor package, wherein a flat portion is formed on at least a part of a top of the protrusion. 【請求項３】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された複数の電極が形成されたエリア
アレイ型半導体パッケージにおいて、 前記エリアアレイ状に配置された電極の各々の外周部に
突起部が設けられ、該突起部の表面は、少なくともはん
だ材料が溶融し合金化して接合することが可能な材料か
らなることを特徴とするエリアアレイ型半導体パッケー
ジ。3. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and arranged in an area array on the other surface of the holding member. In the area array type semiconductor package in which a plurality of electrodes are formed, a projection is provided on an outer peripheral portion of each of the electrodes arranged in the area array, and the surface of the projection is formed by melting at least a solder material and forming an alloy. An area array type semiconductor package comprising a material that can be formed and joined. 【請求項４】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された複数の電極が形成されたエリア
アレイ型半導体パッケージにおいて、 前記電極の各々に複数の凹凸が設けられ、これら凹凸の
表面は、少なくともはんだ材料が溶融し合金化して接合
することが可能な材料からなることを特徴とするエリア
アレイ型半導体パッケージ。4. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and arranged in an area array on the other surface side of the holding member. In the area array type semiconductor package in which a plurality of electrodes are formed, a plurality of irregularities are provided on each of the electrodes, and the surface of these irregularities is made of a material that can be joined by melting and alloying at least the solder material. An area array type semiconductor package, comprising: 【請求項５】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された複数の電極が形成されたエリア
アレイ型半導体パッケージにおいて、 前記電極上に各々階段状の突起部が設けられ、該突起部
の表面は、少なくともはんだ材料が溶融し合金化して接
合することが可能な材料からなることを特徴とするエリ
アアレイ型半導体パッケージ。5. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and is arranged in an area array on the other surface of the holding member. In the area array type semiconductor package in which a plurality of electrodes are formed, a step-like projection is provided on each of the electrodes, and at least the surface of the projection can be joined by melting and alloying a solder material. Area array type semiconductor package characterized by being made of various materials. 【請求項６】 絶縁性材料からなる保持部材の少なくと
も片面に導電性材料からなる配線が形成され、この面上
に半導体素子が搭載され、前記保持部材の他面側にエリ
アアレイ状に配置された複数の電極が形成されたエリア
アレイ型半導体パッケージにおいて、 前記エリアアレイ状に配置された電極のうち、少なくと
もパッケージコーナー部に配置された電極が、前記保持
部材の表面より突出しており、この突出した表面は、少
なくともはんだ材料が溶融し合金化して接合することが
可能な材料からなることを特徴とするエリアアレイ型半
導体パッケージ。6. A wiring made of a conductive material is formed on at least one surface of a holding member made of an insulating material, a semiconductor element is mounted on this surface, and arranged in an area array on the other surface of the holding member. In the area array type semiconductor package in which a plurality of electrodes are formed, among the electrodes arranged in the area array, at least the electrode arranged at the corner of the package projects from the surface of the holding member, An area array type semiconductor package, characterized in that the formed surface is made of a material that can be joined by melting and alloying at least a solder material.
JP2000239113A 2000-08-07 2000-08-07 Area array type semiconductor package Withdrawn JP2002057242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000239113A JP2002057242A (en) 2000-08-07 2000-08-07 Area array type semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000239113A JP2002057242A (en) 2000-08-07 2000-08-07 Area array type semiconductor package

Publications (1)

Publication Number Publication Date
JP2002057242A true JP2002057242A (en) 2002-02-22

Family

ID=18730705

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005286331A (en) * 2004-03-30 2005-10-13 Internatl Business Mach Corp <Ibm> Minute bump for improving lga interconnection
US7968997B2 (en) 2008-01-30 2011-06-28 Kabushiki Kaisha Toshiba Semiconductor device
JP2012151487A (en) * 2008-06-16 2012-08-09 Intel Corp Processing method and apparatus for flat solder grid array and computer system
US11183491B2 (en) 2018-06-25 2021-11-23 Murata Manufacturing Co., Ltd. High-frequency module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005286331A (en) * 2004-03-30 2005-10-13 Internatl Business Mach Corp <Ibm> Minute bump for improving lga interconnection
US7968997B2 (en) 2008-01-30 2011-06-28 Kabushiki Kaisha Toshiba Semiconductor device
JP2012151487A (en) * 2008-06-16 2012-08-09 Intel Corp Processing method and apparatus for flat solder grid array and computer system
US11183491B2 (en) 2018-06-25 2021-11-23 Murata Manufacturing Co., Ltd. High-frequency module

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