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JP2002057271A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP2002057271A
JP2002057271A JP2000241945A JP2000241945A JP2002057271A JP 2002057271 A JP2002057271 A JP 2002057271A JP 2000241945 A JP2000241945 A JP 2000241945A JP 2000241945 A JP2000241945 A JP 2000241945A JP 2002057271 A JP2002057271 A JP 2002057271A
Authority
JP
Japan
Prior art keywords
pad electrode
semiconductor
semiconductor device
pad
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000241945A
Other languages
Japanese (ja)
Inventor
Koji Tamura
宏司 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000241945A priority Critical patent/JP2002057271A/en
Publication of JP2002057271A publication Critical patent/JP2002057271A/en
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】 【課題】 半導体装置の性能を確保しつつ、実装基板へ
実装する際の実装体積や半導体チップ間の配線長を小さ
くすることを目的とする。 【解決手段】 任意の配線層によって形成された第１パ
ッド電極８と、第１パッド電極８とは水平方向に異なる
位置に第１パッド電極８とは異なる配線層で形成された
第２パッド電極５を形成し、半導体基板１０を貫通して
第２パッド電極５と導通するバンプ４を充填することに
よって外部端子を形成する半導体チップを複数製造し、
それらを第１パッド電極８とバンプ４を接続することに
より積層して実装された半導体装置を構成する。この構
成により、半導体チップの上下両面に電極を独立して自
由な位置に設けることにより、積層実装時における半導
体チップのサイズの大小や接続する端子の位置などのレ
イアウトの制約を受けないように積層することができる
ため、半導体装置の性能を確保しつつ、基板へ実装する
際の実装体積や半導体チップ間の配線長を小さくするこ
とができる。 [PROBLEMS] To reduce the mounting volume and the wiring length between semiconductor chips when mounting on a mounting board while ensuring the performance of a semiconductor device. SOLUTION: A first pad electrode 8 formed by an arbitrary wiring layer, and a second pad electrode formed by a wiring layer different from the first pad electrode 8 at a position different from the first pad electrode 8 in a horizontal direction. 5, a plurality of semiconductor chips that form external terminals by filling the bumps 4 penetrating through the semiconductor substrate 10 and conducting to the second pad electrodes 5 are manufactured,
These are stacked by connecting the first pad electrode 8 and the bump 4 to constitute a semiconductor device mounted. With this configuration, the electrodes are independently provided at the upper and lower surfaces of the semiconductor chip at free positions, so that the layout is not restricted by layout restrictions such as the size of the semiconductor chip and the positions of the terminals to be connected at the time of lamination mounting. Therefore, it is possible to reduce the mounting volume and the wiring length between the semiconductor chips when mounting the semiconductor device on a substrate while ensuring the performance of the semiconductor device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、実装基板の高集積
化のために半導体チップを積層化した半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which semiconductor chips are stacked for high integration of a mounting substrate.

【０００２】[0002]

【従来の技術】近年、半導体装置を搭載した電子機器装
置の小型化，高速化を目的として、実装体積の縮小と配
線長の短縮のために、半導体装置の積層化が盛んに行わ
れている。複数の半導体チップを積層して実装する際、
図４に示す従来技術では、パッド電極５からリードフレ
ーム１にボンディングワイヤー３を配線する必要がある
ため、パッド電極５が隠れない程度のサイズの半導体チ
ップしか積層化できず、同程度のサイズの半導体チップ
は積層ができないという制限がある。このため、同程度
のサイズの半導体チップを積層する場合は、図５に示す
ように、半導体チップを貫通してスループラグ１３を充
填することにより半導体チップの上下両面に導通した電
極５を互いに接続して積層している。また、図６では、
上部の電極５から半導体チップを貫通して設けたバンプ
４を第２のパッド電極として設け、それぞれの電極を互
いに接続することにより積層している。2. Description of the Related Art In recent years, semiconductor devices have been actively stacked in order to reduce the mounting volume and the wiring length in order to reduce the size and speed of electronic equipment equipped with the semiconductor device. . When stacking and mounting multiple semiconductor chips,
In the prior art shown in FIG. 4, since it is necessary to wire the bonding wires 3 from the pad electrodes 5 to the lead frame 1, only semiconductor chips of such a size that the pad electrodes 5 cannot be hidden can be stacked. There is a limitation that semiconductor chips cannot be stacked. Therefore, when stacking semiconductor chips of approximately the same size, as shown in FIG. 5, the conductive electrodes 5 are connected to the upper and lower surfaces of the semiconductor chip by penetrating the semiconductor chip and filling the through plugs 13 with each other. And laminated. In FIG. 6,
A bump 4 provided from the upper electrode 5 through the semiconductor chip is provided as a second pad electrode, and the respective electrodes are connected to each other to be stacked.

【０００３】[0003]

【本発明が解決しようとする課題】以上のように、従来
の同程度のサイズの半導体チップを積層する技術では、
半導体チップ両面の電極の位置や電位を同一にせざるを
えず、上下の半導体チップの端子位置が固定されてしま
い異なる信号端子とすることもできないので、積層実装
時の半導体チップの端子配置に制限がかかり、半導体チ
ップ自体の機能が大幅に制限されるという問題点があっ
た。As described above, in the conventional technology for stacking semiconductor chips of the same size,
The positions and potentials of the electrodes on both sides of the semiconductor chip must be the same, and the terminal positions of the upper and lower semiconductor chips are fixed and cannot be different signal terminals. And the function of the semiconductor chip itself is greatly restricted.

【０００４】上記問題点を解決するために、本発明の半
導体装置、およびその製造方法では、積層実装時におけ
る半導体チップのサイズの大小や接続する端子の位置な
どのレイアウトの制約を受けないように、半導体チップ
の上下両面に電極を独立して自由な位置に設けることに
より、半導体装置の性能を確保しつつ、実装基板へ実装
する際の実装体積や半導体チップ間の配線長を小さくす
ることを目的とする。In order to solve the above problems, the semiconductor device and the method of manufacturing the same according to the present invention do not suffer from layout restrictions such as the size of the semiconductor chip and the positions of the terminals to be connected during stacking and mounting. By independently providing electrodes on the upper and lower surfaces of the semiconductor chip at free positions, it is possible to reduce the mounting volume and the wiring length between semiconductor chips when mounting on a mounting board while ensuring the performance of the semiconductor device. Aim.

【０００５】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明の請求項１記載の半導体装置は、実装基板に半
導体チップを積層して実装される半導体装置において、
半導体チップは配線層により形成され上部の保護膜が開
口されて露出する第１のパッド電極と、配線層により形
成された第２のパッド電極と、半導体基板を貫通して第
２のパッド電極と導通し半導体装置の第１のパッド電極
がある面とは反対の面から露出するバンプとを備え、第
１，第２のパッド電極は、それぞれ積層される半導体チ
ップのパッド電極に対応した位置に形成され、パッド電
極を互いに接続して半導体チップを積層する。According to a first aspect of the present invention, there is provided a semiconductor device in which a semiconductor chip is stacked on a mounting substrate and mounted.
The semiconductor chip includes a first pad electrode formed by a wiring layer and having an upper protective film opened and exposed, a second pad electrode formed by the wiring layer, and a second pad electrode penetrating the semiconductor substrate. And a bump exposed from a surface opposite to a surface where the first pad electrode of the semiconductor device is located, wherein the first and second pad electrodes are located at positions corresponding to the pad electrodes of the semiconductor chips to be stacked, respectively. The semiconductor chips are stacked by connecting the pad electrodes to each other.

【０００６】請求項２記載の半導体装置は、請求項１記
載の半導体装置において、第１のパッド電極と第２のパ
ッド電極を異なる配線層で形成する。請求項３記載の半
導体装置の製造方法は、実装基板に半導体チップを積層
して実装される半導体装置を製造するに際し、半導体基
板上に、上下に隣接して積層される半導体チップのパッ
ド電極と対応する位置に配線層により第１のパッド電極
と第２のパッド電極を形成し、第１のパッド電極上の絶
縁膜を開口して第１のパッド電極を露出し、第２のパッ
ド電極下の絶縁膜と半導体基板を貫通し、貫通された領
域に第２のパッド電極に導通したバンプを形成して半導
体チップを製造する工程と、半導体チップをパッド電極
を互いに接続することにより積層する工程とを有する。According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first pad electrode and the second pad electrode are formed in different wiring layers. The method of manufacturing a semiconductor device according to claim 3, wherein, when manufacturing a semiconductor device in which a semiconductor chip is stacked on a mounting substrate and mounted, a pad electrode of the semiconductor chip which is vertically stacked on the semiconductor substrate is provided. A first pad electrode and a second pad electrode are formed at corresponding positions by a wiring layer, an insulating film on the first pad electrode is opened to expose the first pad electrode, and a second pad electrode is formed under the second pad electrode. Forming a bump penetrating through the insulating film and the semiconductor substrate and conducting to the second pad electrode in the penetrated region to manufacture a semiconductor chip, and laminating the semiconductor chip by connecting the pad electrodes to each other And

【０００７】これにより、半導体装置の性能を確保しつ
つ、実装基板へ実装する際の実装体積や半導体チップ間
の配線長を小さくすることができる。As a result, the mounting volume and the wiring length between the semiconductor chips can be reduced when the semiconductor device is mounted on the mounting board while the performance of the semiconductor device is secured.

【０００８】[0008]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。図１は、本発明の積
層された半導体装置の電極を拡大した図である。１はリ
ードフレーム、２ａ，２ｂ，２ｃはそれぞれ半導体チッ
プ、３はボンディングワイヤーである。８は任意の配線
層によって形成された第１パッド電極である。５は第１
パッド電極８とは水平方向に異なる位置に第１パッド電
極８とは異なる配線層で形成された第２パッド電極であ
る。第２パッド電極５は半導体基板１０を貫通して導電
体を充填してバンプ４を外部端子として形成している。
このように構成された半導体チップ２ａ，２ｂ，２ｃに
ついて対応するようにレイアウトされた第１パッド電極
８とバンプ４を接続して積層している。ここで、第１パ
ッド電極８と第２パッド電極５の水平方向の位置をずら
した形態について説明したが、水平方向に同一の位置に
形成しても良い。また、第１パッド電極８と第２パッド
電極５を異なる配線層で形成した形態について説明した
が、同一の配線層により電極を形成することもできる。
図２は、上記のように積層された半導体装置を表した断
面図である。バンプ４と第２パッド電極５により接続さ
れた半導体チップ（２ａ，２ｂ，２ｃ）を積層し、ワイ
ヤーボンディング３によってリードフレーム１に導通さ
れている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged view of the electrodes of the stacked semiconductor device of the present invention. 1 is a lead frame, 2a, 2b and 2c are semiconductor chips, respectively, and 3 is a bonding wire. Reference numeral 8 denotes a first pad electrode formed by an arbitrary wiring layer. 5 is the first
The second pad electrode is formed at a different position in the horizontal direction from the pad electrode 8 with a different wiring layer from the first pad electrode 8. The second pad electrode 5 penetrates the semiconductor substrate 10 and is filled with a conductor to form the bump 4 as an external terminal.
The first pad electrodes 8 and the bumps 4 laid out so as to correspond to the semiconductor chips 2a, 2b, and 2c configured as described above are connected and stacked. Here, the form in which the horizontal position of the first pad electrode 8 and the second pad electrode 5 is shifted has been described, but they may be formed at the same position in the horizontal direction. Further, although the embodiment in which the first pad electrode 8 and the second pad electrode 5 are formed by different wiring layers has been described, the electrodes can be formed by the same wiring layer.
FIG. 2 is a cross-sectional view illustrating the semiconductor devices stacked as described above. The semiconductor chips (2a, 2b, 2c) connected by the bumps 4 and the second pad electrodes 5 are stacked, and are electrically connected to the lead frame 1 by wire bonding 3.

【０００９】図３は、本発明の製造方法を順を追って説
明したものである。図３（ａ）に示すように、従来の技
術を用い、半導体基板１０上に第１層間絶縁膜９、第１
パッド電極８、第２層間絶縁膜７、第２パッド電極５、
第１保護膜６を形成する。次に図３（ｂ）に示すよう
に、半導体基板１０のチップ裏面にフォトレジスト１２
を形成し、その後、異方性のウエットエッチまたはドラ
イエッチを行い、第１層間絶縁膜９までエッチングを行
う。本実施の形態では、アルカリ溶液で四角錐状に異方
エッチングした例を示したが、通常使われる臭化水素系
のエッチングガスを用いてドライエッチしてもかまわな
い。アルカリ溶液としては、例えば水酸化カリウム（Ｋ
ＯＨ）、ヒドロジン水溶液（Ｎ2Ｈ2）、エチレンジアミ
ン・ピロカテゴール（ＥＤＰ)、アンモニア水溶液（Ｎ
Ｈ4ＯＨ）、テトラメチルアンモニウムハイドロオキサ
イド（ＴＭＡＨ）などが挙げられる。次にフォトレジス
ト除去後、図３（ｃ）に示すように、半導体基板１０裏
面に第２保護膜１１を形成する。次に図３（ｄ）に示す
ように、フォトレジスト１２を形成し、その後、ウエッ
トエッチまたはドライエッチを行い、第１パッド電極８
下までエッチングする。次にフォトレジスト１２除去
後、図３（ｅ）に示すとおり、メッキなどで第１パッド
電極８に導通したバンプ４を形成後、第２パッド電極５
を従来の技術を用いて開口する。さらに、半導体チップ
を積層実装する場合、図３（ｆ）に示すように、上記の
様な構成の半導体チップ（２ａ，２ｂ，２ｃ）を作成
し、対応するパッド電極同士（５，８）をバンプ４を介
して接続して半導体チップ（２ａ，２ｂ，２ｃ）を積層
する。最後に、最上段の半導体チップ２ａの第２パッド
電極５にボンディングワイヤー３で配線を施す。以上、
本実施の形態では半導体チップを３層積層する場合につ
いて説明したが、２層以上を積層する場合は何層でも同
様である。製造順については前記記述は例であり、前後
してもかまわない。また、半導体チップを直接積層する
例を記述したが、間にプリント基板などの配線基板など
を挿入して間接的に積層しても良い。また、最上層半導
体チップ２ａにボンディングワイヤー３を用いている
が、バンプ４を用い、積層化したフリップチップとして
もかまわない。また、第１パッド電極８と第２パッド電
極５は接続されて同一電位でも、別電位でも良く、同一
の配線層で形成されていてもかまわない。また、パッド
電極は同一個所の表裏に存在しても存在しなくてもかま
わない。また、パッド電極にバンプを形成するかどうか
でそのパッド電極について半導体チップ間の接続を行う
かどうかを選択することも可能である。FIG. 3 illustrates the manufacturing method of the present invention step by step. As shown in FIG. 3A, a first interlayer insulating film 9 and a first interlayer insulating film 9 are formed on a semiconductor substrate 10 by using a conventional technique.
Pad electrode 8, second interlayer insulating film 7, second pad electrode 5,
The first protection film 6 is formed. Next, as shown in FIG. 3B, a photoresist 12
Then, anisotropic wet etching or dry etching is performed, and etching is performed up to the first interlayer insulating film 9. In this embodiment mode, an example in which anisotropic etching is performed in a pyramid shape with an alkali solution is described, but dry etching may be performed using a hydrogen bromide-based etching gas that is generally used. As the alkaline solution, for example, potassium hydroxide (K
OH), aqueous solution of hydrozine (N 2 H 2 ), ethylenediamine / pyrocatechol (EDP), aqueous solution of ammonia (N
H 4 OH), and the like tetramethylammonium hydroxide (TMAH). Next, after the photoresist is removed, a second protective film 11 is formed on the back surface of the semiconductor substrate 10 as shown in FIG. Next, as shown in FIG. 3D, a photoresist 12 is formed, and thereafter, wet etching or dry etching is performed, and the first pad electrode 8 is formed.
Etch down. Next, after the photoresist 12 is removed, as shown in FIG. 3E, the bumps 4 electrically connected to the first pad electrodes 8 are formed by plating or the like, and then the second pad electrodes 5 are formed.
Is opened using conventional techniques. Further, when the semiconductor chips are stacked and mounted, as shown in FIG. 3F, the semiconductor chips (2a, 2b, 2c) having the above-described configuration are formed, and the corresponding pad electrodes (5, 8) are connected. The semiconductor chips (2a, 2b, 2c) are stacked by connecting via the bumps 4. Finally, a wiring is provided to the second pad electrode 5 of the uppermost semiconductor chip 2a with the bonding wire 3. that's all,
In this embodiment, the case where three layers of semiconductor chips are stacked is described. However, when two or more layers are stacked, the same applies to any number of layers. The above description is an example of the manufacturing order, and the order may be changed. Although the example in which the semiconductor chips are directly stacked is described, the semiconductor chips may be indirectly stacked by inserting a wiring board such as a printed board therebetween. Although the bonding wires 3 are used for the uppermost semiconductor chip 2a, the flip chips may be stacked using the bumps 4. In addition, the first pad electrode 8 and the second pad electrode 5 are connected to each other and may be at the same potential or different potentials, and may be formed by the same wiring layer. Further, the pad electrodes may or may not be present on the front and back of the same location. It is also possible to select whether to connect the semiconductor chip to the pad electrode depending on whether a bump is formed on the pad electrode.

【００１０】以上のような構成にすることにより、半導
体装置の性能を確保しつつ、実装基板へ実装する際の実
装体積や半導体チップ間の配線長を小さくすることがで
きる。With the above configuration, the volume of the semiconductor device mounted on the mounting substrate and the wiring length between the semiconductor chips can be reduced while ensuring the performance of the semiconductor device.

【００１１】[0011]

【発明の効果】本発明の半導体装置、およびその製造方
法は、半導体チップの上下両面に電極を独立して自由な
位置に設けることにより、積層実装時における半導体チ
ップのサイズの大小や接続する端子の位置などのレイア
ウトの制約を受けないように積層することができるた
め、半導体装置の性能を確保しつつ、実装基板へ実装す
る際の実装体積や半導体チップ間の配線長を小さくする
ことができる。According to the semiconductor device of the present invention and the method for manufacturing the same, the electrodes are provided independently at free positions on the upper and lower surfaces of the semiconductor chip, so that the size of the semiconductor chip in lamination mounting and the terminals to be connected can be improved. Can be stacked so as not to be restricted by the layout such as the position of the semiconductor device. Therefore, the performance of the semiconductor device can be ensured, and the mounting volume and the wiring length between the semiconductor chips can be reduced when the semiconductor device is mounted on the mounting substrate. .

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態における半導体装置のパッ
ド電極部分拡大断面図FIG. 1 is an enlarged sectional view of a part of a pad electrode of a semiconductor device according to an embodiment of the present invention;

【図２】本発明の実施の形態における半導体装置の断面
図FIG. 2 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention;

【図３】本発明の実施の形態における半導体装置の工程
断面図FIG. 3 is a process sectional view of the semiconductor device according to the embodiment of the present invention;

【図４】従来の半導体装置の積層実装図FIG. 4 is a stacked mounting diagram of a conventional semiconductor device.

【図５】従来のスループラグを用いて半導体基板両面に
パッド電極を設けた半導体装置の断面図FIG. 5 is a cross-sectional view of a semiconductor device in which pad electrodes are provided on both surfaces of a semiconductor substrate using a conventional through plug.

【図６】従来のバンプを用いて半導体基板両面にパッド
電極を設けた半導体装置の断面図FIG. 6 is a cross-sectional view of a conventional semiconductor device in which pad electrodes are provided on both surfaces of a semiconductor substrate using bumps.

【符号の説明】[Explanation of symbols]

１ リードフレーム ２ 半導体チップ ２ａ 半導体チップ ２ｂ 半導体チップ ２ｃ 半導体チップ ３ ボンディングワイヤー ４ バンプ ５ パッド電極 ６ 保護膜 ７ 絶縁膜 ８ パッド電極 ９ 絶縁膜 １０ 半導体基板 １１ 保護膜 １２ フォトレジスト １３ スループラグ DESCRIPTION OF SYMBOLS 1 Lead frame 2 Semiconductor chip 2a Semiconductor chip 2b Semiconductor chip 2c Semiconductor chip 3 Bonding wire 4 Bump 5 Pad electrode 6 Protective film 7 Insulating film 8 Pad electrode 9 Insulating film 10 Semiconductor substrate 11 Protective film 12 Photoresist 13 Through plug

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】実装基板に半導体チップを積層して実装さ
れる半導体装置において、 半導体チップは、配線層により形成され上部の保護膜が
開口されて露出する第１のパッド電極と、配線層により
形成された第２のパッド電極と、半導体基板を貫通して
前記第２のパッド電極と導通し半導体装置の前記第１の
パッド電極がある面とは反対の面から露出するバンプと
を備え、 前記第１，第２のパッド電極は、それぞれ積層される半
導体チップのパッド電極に対応した位置に形成され、前
記パッド電極を互いに接続して前記半導体チップを積層
した半導体装置。In a semiconductor device mounted with a semiconductor chip laminated on a mounting substrate, the semiconductor chip includes a first pad electrode formed of a wiring layer and having an upper protective film opened and exposed, and a wiring layer. A second pad electrode formed, and a bump penetrating through a semiconductor substrate and electrically connected to the second pad electrode and exposed from a surface of the semiconductor device opposite to a surface where the first pad electrode is located, A semiconductor device in which the first and second pad electrodes are formed at positions corresponding to the pad electrodes of the semiconductor chips to be laminated, respectively, and the semiconductor chips are laminated by connecting the pad electrodes to each other. 【請求項２】前記第１のパッド電極と前記第２のパッド
電極が異なる配線層で形成された請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein said first pad electrode and said second pad electrode are formed in different wiring layers. 【請求項３】実装基板に半導体チップを積層して実装さ
れる半導体装置を製造するに際し、 半導体基板上に、上下に隣接して積層される半導体チッ
プのパッド電極と対応する位置に配線層により第１のパ
ッド電極と第２のパッド電極を形成し、前記第１のパッ
ド電極上の絶縁膜を開口して前記第１のパッド電極を露
出し、前記第２のパッド電極下の絶縁膜と半導体基板を
貫通し、前記貫通された領域に前記第２のパッド電極に
導通したバンプを形成して半導体チップを製造する工程
と、 前記半導体チップを、前記パッド電極を互いに接続する
ことにより積層する工程とを有する半導体装置の製造方
法。3. When manufacturing a semiconductor device in which a semiconductor chip is mounted on a mounting substrate by laminating the semiconductor chip, a wiring layer is formed on the semiconductor substrate at a position corresponding to a pad electrode of the semiconductor chip stacked vertically adjacently. Forming a first pad electrode and a second pad electrode, opening an insulating film on the first pad electrode, exposing the first pad electrode, and forming an insulating film under the second pad electrode; A step of forming a bump penetrating the semiconductor substrate and conducting to the second pad electrode in the penetrated region to produce a semiconductor chip; and stacking the semiconductor chip by connecting the pad electrodes to each other And a method for manufacturing a semiconductor device.
JP2000241945A 2000-08-10 2000-08-10 Semiconductor device and method of manufacturing the same Pending JP2002057271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000241945A JP2002057271A (en) 2000-08-10 2000-08-10 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000241945A JP2002057271A (en) 2000-08-10 2000-08-10 Semiconductor device and method of manufacturing the same

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US7045870B2 (en) 2001-10-04 2006-05-16 Sony Corporation Solid image-pickup device and method for manufacturing the solid image pickup device
JP2010232685A (en) * 2010-07-05 2010-10-14 Fujikura Ltd Wiring board manufacturing method
JP2011009781A (en) * 2010-09-29 2011-01-13 Fujikura Ltd Manufacturing method of semiconductor device with through electrode
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US8410567B2 (en) 2001-10-04 2013-04-02 Sony Corporation Solid image-pickup device with flexible circuit substrate
US9048352B2 (en) 2001-10-04 2015-06-02 Sony Corporation Solid image-pickup device with flexible circuit substrate
US7187051B2 (en) 2001-10-04 2007-03-06 Sony Corporation Solid image-pickup device and method for manufacturing the solid image pickup device
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