JP2002057342A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: A semiconductor device capable of avoiding abnormal etching of a gate insulating film when forming a gate electrode by patterning, even when a TFT is formed by a low-temperature process of less than 600 ° C. To provide a manufacturing method. SOLUTION: In manufacturing an active matrix substrate 200 by a low-temperature process, a substrate 50 made of glass or the like is used.
After forming the gate insulating films 12, 22, 32 on the surface of the semiconductor film 100 formed thereon under a temperature condition of 600 ° C. or less,
The gate insulating films 12, 22, 3
Step 2 of modifying the gate insulating film to enhance the etching resistance. Next, after a conductive film 150 for forming a gate electrode is formed on the surfaces of the gate insulating films 12, 22, and 32, a resist mask 66 is formed.
, Dry etching is performed on the conductive film 150 for forming a gate electrode to form the gate electrodes 14, 24 and 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device having a thin film transistor (hereinafter, referred to as TFT). More specifically, the present invention relates to a method for manufacturing a semiconductor device in which each step is performed by a low-temperature process in which the temperature is lower than 600 ° C.

[0002]

2. Description of the Related Art Among various semiconductor devices having a TFT, when manufacturing a device using a TFT as an active element of a liquid crystal display device, a quartz substrate is used instead of a quartz substrate.
Low temperature processes are being adopted so that inexpensive glass substrates can be used. The low-temperature process generally means that the maximum temperature of the process (the maximum temperature at which the entire substrate simultaneously rises) is about 600.
In contrast, the high-temperature process is a process in which the maximum temperature of the process (the maximum temperature at which the entire substrate simultaneously rises) is approximately 800 ° C. or higher, such as thermal oxidation of silicon. 700 ° C to 1200 ° C
Is performed at a high temperature.

However, in a low-temperature process, it is impossible to directly form a polycrystalline semiconductor film on a substrate. Therefore, an amorphous semiconductor film is formed using a plasma CVD method or a low-pressure CVD method. After this, it is necessary to crystallize this semiconductor film. As a method of this crystallization, for example, S
PC method (Solid Phase Crystalli)
zation) and RTA method (Rapid Thermo)
l Annealong), there is a method such as laser annealing (ELA: Excimer) by irradiating an excimer laser beam using XeCI.
According to Laser Annealing, an increase in the temperature of the glass substrate is suppressed and polycrystalline Si having a large grain size can be obtained.

Therefore, after a polycrystalline semiconductor film is formed by using such a crystallization process, if each of the processes described below with reference to FIG. A semiconductor device including a TFT, such as an active matrix substrate, can be manufactured.

[0005] In the manufacturing method shown in FIG.
As shown in (A), after forming a polycrystalline semiconductor film 100 on the surface of a substrate 50 such as glass using a laser annealing method or the like, the temperature is lower than 600 ° C., preferably 500 ° C.
Under conditions below, gate insulating films 12, 22, and 32 made of a silicon oxide film having a thickness of 60 nm to 150 nm are formed by a plasma CVD method using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas (gate insulating film). Forming step).

[0006] Next, as shown in FIG.
After a conductive film 150 for forming a gate electrode such as an aluminum film is formed by a sputtering method under a condition of less than 00 ° C., preferably less than 500 ° C., as shown in FIG. Mask 66 on the surface of
Then, dry etching is performed on the gate electrode forming conductive film 150 via the resist mask 66 to form the gate electrodes 14, 24, and 34 as shown in FIG. Forming step).

Thereafter, the gate electrode 1 is formed by a method such as ion implantation or ion shower doping.
4, 24, 34 or the semiconductor film 100 via the gate insulating films 12, 22, 32 using the resist mask as a mask.
An N-type or P-type impurity is introduced into a predetermined region of the TFT to form a TFT using the semiconductor film 100 as an active layer.

[0008]

SUMMARY OF THE INVENTION However, 600
Since the gate insulating films 12, 22, and 32 formed under a temperature condition of less than 500C or less than 500C have many defects,
Low etching resistance. When the gate insulating films 12, 22, and 32 are formed using TEOS, the etching resistance is low due to carbon contained in the gate insulating films 12, 22, and 32 and the presence of defects caused by the carbon. For this reason, the gate electrode forming conductive film 150
When the gate electrodes 14, 24, 34 are formed by dry etching, the gate insulating films 12, 22, 32 are over-etched as shown in FIG. , 32 vary. As a result, when impurities are introduced into the semiconductor film 100 via the gate insulating films 12, 22, 32 by a method such as ion implantation or ion implantation, it is difficult to control the impurity concentration distribution in the depth direction of the semiconductor film 100. There is a point. That is, the acceleration voltage or the like at the time of introducing the impurity is set to an optimal condition according to the thickness of the gate insulating films 12, 22, and 32. In addition, the optimum accelerating voltage at the time of introducing impurities fluctuates. In addition, when the gate electrode forming conductive film 150 is dry-etched to form the gate electrodes 14, 24, 34, as shown in FIG. 9B, the gate insulating films 12, 2
Of the layers 2 and 32, the portion 102 located directly below the end of the gate electrodes 14, 24 and 34 may be etched. In such a state, the gate electrodes 14, 2
When impurities are introduced into the semiconductor film 100 using the masks 4 and 34 as masks, the region into which the impurities are introduced cannot be controlled. , L of this TFT
There is a problem that the DD length cannot be controlled.

[0009] In view of the above problems, an object of the present invention is to provide:
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of avoiding abnormal etching of a gate insulating film when forming a gate electrode by patterning even when a TFT is formed by a low-temperature process of less than 600 ° C.

[0010]

In order to solve the above-mentioned problems, according to the present invention, the surface of a semiconductor film formed on a substrate is coated with 6.
Forming a gate insulating film under a temperature condition of less than 00 ° C .; forming a conductive film for forming a gate electrode on the surface of the gate insulating film; and forming a patterning mask on the surface of the conductive film for forming the gate electrode. Forming a gate electrode by forming the gate electrode by etching the conductive film for forming a gate electrode through the patterning mask, and then forming an active layer of the thin film transistor by the semiconductor film. In the method of manufacturing the device,
After performing the gate insulating film forming step and before performing the gate electrode forming step, a gate insulating film modifying step for improving the etching resistance of the gate insulating film is performed.

When a semiconductor device provided with a TFT is manufactured by a low-temperature process, a gate insulating film is also formed at a temperature of less than 600 ° C. or even less than 500 ° C., so that the etching resistance is not affected by the presence of defects or the like. Low,
In the present invention, before patterning the conductive film for forming a gate electrode, a gate insulating film modifying step for improving the etching resistance of the gate insulating film is performed. Therefore, when the gate electrode is formed by etching the conductive film for forming a gate electrode, the gate insulating film can be prevented from being abnormally etched. For example, in RIE dry etching using Cl ₂ + BCl ₃ gas, the etching rate of aluminum is 100 nm / min to 150 nm / min, and the etching rate of the silicon oxide film without performing the gate insulating film modification step is 5 nm / min. ~ 15nm / min
It is. Therefore, in the conventional method in which the gate insulating film modification step is not performed, assuming that the over-etching time is 50 seconds, the silicon oxide film used as the gate insulating film is abnormally etched by 4 to 12 nm / min. As a result, the implantation depth at the time of ion implantation greatly varies, and the TFT characteristics vary. On the other hand, when the gate insulating film modification step is performed as in the present invention, the etching rate of the silicon oxide film in the RIE dry etching using Cl ₂ + BCl ₃ gas is 0.5 nm / min to 1.0 nm. Since the silicon oxide film used as the gate insulating film is etched even if over-etching is performed for 50 seconds, the thickness is 0.4 nm / min to 1.2 n.
m / min. Therefore, when the gate electrode has been formed, the thickness of the gate insulating film is constant. Therefore, when impurities are introduced into the semiconductor film through the gate insulating film by a method such as ion implantation or ion implantation, The impurity concentration distribution in the depth direction of the film can be easily controlled. That is, the acceleration voltage or the like at the time of introducing the impurity is set to an optimum condition according to the thickness of the gate insulating film. However, according to the present invention, since the thickness of the gate insulating film does not change, The optimum acceleration voltage at the time of introduction does not fluctuate. Therefore, the impurity can always be introduced under the optimum condition, so that the impurity concentration of the source / drain can be set to the optimum condition. Further, when the gate electrode is formed by dry-etching the conductive film for forming a gate electrode, a portion of the gate insulating film located immediately below an end of the gate electrode is not etched, so that the gate electrode is formed. Even when an impurity is introduced into a semiconductor film as a mask, an impurity introduction region can be reliably controlled. Therefore, even when a low-concentration impurity is introduced into a semiconductor film using a gate electrode as a mask to manufacture a TFT having an LDD structure, this T
The LDD length of the FT can be reliably controlled.

The present invention is characterized in that in the step of forming a gate electrode,
This is effective when the gate electrode is formed by dry etching of the conductive film for forming a gate electrode.
That is, in the case of dry etching, the etching selectivity is lower than that of wet etching. Therefore, when the conductive film for forming a gate electrode is etched, the gate insulating film is also easily etched. However, if the etching resistance of the gate insulating film is increased by applying the present invention, the gate insulating film is abnormally etched even when dry etching is used to pattern the gate electrode forming conductive film. Can be prevented.

In the present invention, in the gate insulating film modifying step, for example, an annealing process is performed on the gate insulating film. As the annealing treatment, for example, a heat treatment for heating the gate insulating film in an atmosphere of a nitrogen gas, an argon gas, a helium gas, an oxygen gas, or a mixed gas of these gases can be employed. Further, a lamp annealing process or a laser annealing process may be performed as the annealing process. By performing such processing,
The etching resistance of the gate insulating film is improved. It is considered that the reason is that such an annealing treatment densifies the gate insulating film.

In the present invention, in the step of modifying the gate insulating film, a plasma treatment for irradiating the gate insulating film with plasma may be performed. In such plasma processing,
The gate insulating film is irradiated with oxygen plasma, hydrogen plasma, or nitrogen plasma. Even when such processing is performed, the etching resistance of the gate insulating film is improved. It is considered that the reason is that defects are reduced on the surface of the gate insulating film by plasma irradiation.

In the present invention, the conductive film for forming a gate electrode is, for example, a single layer or a multilayer of any one of an aluminum film, an aluminum-copper alloy film, a chromium film, a titanium film, and a tantalum film. Conductive film.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, as an embodiment of the present invention, a P-type TFT for a driving circuit and an N-type TFT for a driving circuit are formed on an active matrix substrate of a liquid crystal display device. TFT and N-type T for pixel switching
An example of forming an FT will be described.

[Overall Configuration of Active Matrix Substrate]
1A and 1B are a block diagram schematically showing a configuration of an active matrix substrate of a liquid crystal display device, and an equivalent circuit diagram of a COMS circuit forming a driving circuit thereof. FIG. 2 is a sectional view of three types of TFTs formed on the active matrix substrate shown in FIG.

As shown in FIG. 1A, in an active matrix substrate 200 for a liquid crystal display device, in a screen display region 81 corresponding to a substantially central region of a transparent substrate made of glass or the like, an aluminum film, aluminum A pixel is formed by a data line 90 and a scanning line 91 formed of a conductive film in which a metal film of any one of a copper alloy film, a chromium film, a titanium film, and a tantalum film is formed in a single layer or a multilayer; Each pixel has a liquid crystal capacitor 94 to which an image signal is input via the pixel switching TFT 30.
(Liquid crystal cell) is formed. For the data line 90, a data side drive circuit 60 including a shift register 84, a level shifter 85, a video line 87, and an analog switch 86 is configured. For the scanning line 91, a scanning side driving circuit 70 including a shift register 88 and a level shifter 89 is configured. Note that each pixel has
A storage capacitor 40 is formed between the scanning line 91 and a capacitor line 92 extending in parallel, and the storage capacitor 40 has a function of improving the charge holding characteristics of the liquid crystal capacitor 94. This storage capacitor 40 may be formed between the scanning line 91 and the preceding stage.

[Basic Configuration of CMOS Circuit] In the driving circuits 60 and 70 on the data side and the scanning side, as shown in FIG. 1B, a CMOS circuit is constituted by an N-type TFT 10 and a P-type TFT 20. I have. Such CMOS
One or more stages of the driving circuits 60 and 70 constitute an inverter circuit.

[TFT on Active Matrix Substrate]
Therefore, as shown in FIG. 2, in the active matrix substrate 200, the surface side of the transparent substrate 50 made of glass is
N-type TFT 10 for drive circuit, P-type T for drive circuit
FT20 and N-type TFT3 for pixel switching
Three types of TFTs consisting of 0 are formed. In such an active matrix substrate 200, the substrate 50
Is formed on the underside protective film 51 made of a silicon oxide film, and a polycrystalline semiconductor film 100 patterned in an island shape is formed on the underside protective film 51.

These semiconductor films 100 are respectively composed of an N-type TFT 10 for a drive circuit and a P-type TF for a drive circuit.
T20 and N-type TFT 30 for pixel switching
For forming an active layer or the like of each semiconductor film 10
Gate insulating films 12, 22, and 32 made of a silicon oxide film or the like are formed on the surface of 0.

On the surfaces of the gate insulating films 12, 22, and 32, a conductive film in which a metal film of any one of an aluminum film, an aluminum-copper alloy film, a chromium film, a titanium film, and a tantalum film is formed in a single layer or a multilayer is formed. Gate electrodes 14, 24, 34 made of a film are respectively formed, and among these gate electrodes, an N-type TFT 30 for pixel switching is used.
Is a part of the scanning line 91 (see FIG. 1).

Each semiconductor film 100 has a gate electrode 14,
Channel regions 15, 25, and 35 are formed in regions facing gate electrodes 24 and 34 via gate insulating films 12, 22 and 32, respectively. On both sides of these channel regions 15, 25, and 35, low-concentration source / drain regions 17, 27, and 37 facing the gate electrodes 14, 24, and 34 via the gate insulating films 12, 22, and 32 are formed, respectively. Have been. Also, low-concentration source / drain regions 17, 27,
37, high-concentration source / drain regions 16, 2
6 and 36 are formed, respectively,
Source electrodes 41, 43, a drain electrode 42, a source electrode 44 which is a part of the data line 90 (see FIG. 1), and a pixel electrode 45 are provided in the drain regions 16, 26, 36 via contact holes in an interlayer insulating film 52. Are electrically connected to each other.

As described above, in this embodiment, any TFT
Since 10, 20, and 30 also have the LDD structure, the off-leak current is small. For this reason, it is possible to prevent a reduction in contrast, display unevenness, flicker, malfunction of the driving circuit, and the like.
The display quality can be improved.

(Method of Manufacturing TFT) A method of manufacturing the active matrix substrate 200 having such a configuration will be described with reference to FIGS. 3, 4, and 5. FIG.

FIGS. 3 to 5 are process sectional views showing a method for manufacturing the active matrix substrate 200 of the present embodiment.

First, in FIG. 3A, after preparing a substrate 50 made of glass or the like cleaned by ultrasonic cleaning or the like,
When the substrate temperature is from about 150 ° C. to about 450 ° C.,
As shown in FIG. 3B, a thickness of 20
A base protective film 51 made of a silicon oxide film having a thickness of 0 nm to 500 nm is formed by a plasma CVD method. As the raw material gas at this time, for example, a mixed gas of monosilane and laughing gas, TEOS (tetraethoxysilane) and oxygen,
Alternatively, disilane and ammonia can be used.

Next, it is necessary to form a polycrystalline semiconductor film on the substrate 50 without thermally deforming the glass substrate 50. In order to form a polycrystalline semiconductor film under such restrictions, as shown in FIG.
Under a temperature condition of 50 ° C. to about 450 ° C., a semiconductor film 100 made of an amorphous silicon film having a thickness of 30 nm to 70 nm is formed on the entire surface of the substrate 50 by a plasma CVD method. At this time, for example, disilane or monosilane can be used as a source gas (semiconductor film forming step). Note that the amorphous semiconductor film 100 is formed on the substrate 50 under a low temperature condition.
Is formed instead of the plasma CVD method.
A low-pressure CVD method, an EB evaporation method, a sputtering method, or the like may be used.

Next, as shown in FIG. 3C, the semiconductor film 100 is irradiated with laser light to perform laser annealing, so that the semiconductor film 100 is polycrystallized (crystallization step).

After forming the polycrystalline semiconductor film 100 in this manner, as shown in FIG.
Is patterned in an island shape.

Thereafter, a TFT using the island-shaped semiconductor film 100 as an active layer is formed. First, as shown in FIG. 4A, the temperature is lower than 600 ° C., preferably 50 ° C.
Under a temperature condition of less than 0 ° C., a thickness of 60 n is applied to the surface side of the semiconductor film 100 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas.
Gate insulating films 12, 22, and 32 made of a silicon oxide film having a thickness of m to 150 nm are formed (gate insulating film forming step).

In the present embodiment, the gate insulating films 12 and 2
A step of modifying the gate insulating film for improving the etching resistance of steps 2 and 32 is performed.

In this embodiment, as the gate insulating film reforming step, an annealing process is performed on the gate insulating films 12, 22, and 32. Here, the annealing treatment is performed in an atmosphere of a nitrogen gas, an argon gas, a helium gas, an oxygen gas, or a mixed gas of these gases.
32 is heated (heat treatment). The heat treatment condition at this time is, for example, when the processing temperature is set to 400 ° C. or more and less than 500 ° C., the processing time is set to 3 hours or more. In the heat treatment step, when the heat treatment temperature is set to 500 ° C. or more and less than 600 ° C., the treatment time is set to 1 hour or more and less than 3 hours.

The annealing performed in the gate insulating film modifying step may be a lamp annealing or a laser annealing. By performing such a process, the etching resistance of the gate insulating films 12, 22, and 32 is improved.
The reason is that such an annealing process
This is considered to be due to densification of the gate insulating films 12, 22, and 32.

In the step of modifying the gate insulating film, a plasma treatment for irradiating the gate insulating films 12, 22, 32 with plasma may be performed. As such a plasma treatment, for example, an oxygen plasma treatment for irradiating the gate insulating films 12, 22, 32 with oxygen plasma, a gate insulating film 12,
Hydrogen plasma treatment for irradiating hydrogen plasma to 22, 22 or nitrogen plasma treatment for irradiating nitrogen plasma can be employed. Conditions at this time are, for example,
1. The internal pressure in the plasma processing chamber is set to 0.66 × 10 ² Pa to ² .
66 × 10 ² Pa and at a temperature of 200 ° C. to 40 ° C.
0 ° C. Even when such a plasma treatment is performed,
The etching resistance of the gate insulating films 12, 22, 32 is improved. It is considered that the reason is that defects on the surfaces of the gate insulating films 12, 22, and 32 are significantly reduced by plasma irradiation.

Next, as shown in FIG. 4C, the surface of the gate insulating films 12, 22, 24 is heated to a temperature of 600 ° C. or less.
An aluminum film, preferably under a condition of 500 ° C. or lower,
A conductive film 150 for forming a gate electrode formed of a conductive film in which one of a metal film of an aluminum-copper alloy film, a chromium film, a titanium film, and a tantalum film is formed in a single layer or a multilayer
Is formed by a sputtering method, as shown in FIG. 4D, a resist mask 66 is formed on the surface of the conductive film 150 for gate electrode formation, and thereafter, the conductive film 150 for gate electrode formation is formed via the resist mask 66. By performing dry etching, gate electrodes 14, 24, 34 of each TFT are formed as shown in FIG. 4E (gate electrode forming step).

In this embodiment, when the conductive film 150 for forming a gate electrode is an aluminum film, the gas for dry-etching the conductive film 150 for forming a gate electrode is CCl ₄ gas, CCl ₄ + He, BCl ₃ gas, or BCl ₃ gas. _{The material of} the gate electrode forming conductive film 150 is, for example, using ₂ gas, Cl ₂ + BCl ₃ gas, or SiCl ₄ gas, and using the Cl ₂ gas, CCl ₄ + O ₂ gas when the gate electrode forming conductive film 150 is a chromium film. The most suitable gas is used according to the conditions.

Next, as shown in FIG.
N-type TFT 10 and N-type for pixel switching
Each formation region of the pixel TFT 30 is formed by a resist mask 61.
Cover with. In this state, about 10¹³cm^-2With a dose of
When ion is implanted, a gate electrode is formed on the semiconductor film 100.
Impurity concentration of about 10¹⁸cm ^-3
Is formed. In addition, impurities
The portion not entered becomes the channel region 25.

If this low concentration impurity implantation step is not performed, the P-type drive circuit TFT 20 has an offset gate structure instead of an LDD structure.

Next, as shown in FIG. 5B, the formation region of the P-type TFT 20 for the driving circuit is
Cover with. In this state, when phosphorus ions are implanted at a dose of about 10 ¹³ cm ⁻² , the gate electrode 1
The impurity concentration is about 10 ¹⁸ c in a self-aligned manner with respect to 4, 34.
m ⁻³ low concentration N-type regions 13 and 33 are formed. In addition,
The portions where the impurities are not introduced are the channel regions 15, 3
It becomes 5.

Unless this low concentration impurity implantation step is performed, the N-type driving circuit TFT 10 and the N-type pixel TFT 30 have an offset gate structure instead of an LDD structure.

Next, as shown in FIG.
N-type TFT 10 and N-type for pixel switching
In addition to the region where the pixel TFT 30 is formed, the gate electrode 2
Then, a resist mask 63 is formed to cover 4 in a wider manner. this
In the state, about 10^Fifteencm^-2The dose of
Implantation of boron ions in an amount of about 10 ²⁰
cm^-3The high concentration source / drain region 26 is formed.
Covered by the resist mask 63 in the low concentration P-type region 23
The part which was in the low concentration source / drain region 2
Remains as 7. Thus, the P-type TF for the driving circuit
Form T20.

Next, as shown in FIG. 5D, a resist mask 64 is formed to widely cover the gate electrodes 14 and 34 in addition to the formation region of the P-type TFT 20 for the driving circuit. In this state, the low-concentration N-type regions 13 and 23 have about 10 ¹⁵
A high concentration source / drain region 1 with an impurity concentration of about 10 ²⁰ cm ⁻³ is implanted by implanting phosphorus ions at a dose amount of cm ^−2.
6 and 36 are formed. Portions of the low-concentration N-type regions 13 and 23 covered with the resist mask 64 remain as low-concentration source / drain regions 17 and 37 having an impurity concentration of about 10 ¹⁸ cm ⁻³ . Thus, the N-type TFT 10 for the driving circuit and the N-type TFT
The pixel TFT 30 is formed.

Thereafter, as shown in FIG.
Is formed, annealing for activation is performed, and then a contact hole is formed.
3. If the drain electrode 42 and the pixel electrode 45 are formed, the active matrix substrate 200 can be manufactured.

It should be noted that a high concentration impurity is implanted using the gate electrodes 14, 24, 34 as a mask without introducing a low concentration impurity, and the source regions and the drains are self-aligned into the gate electrodes 14, 24, 34. A region may be formed.

(Main Effects of the Manufacturing Method of the Present Embodiment) As described above, when the active matrix substrate 200 is manufactured by the low-temperature process, the gate insulating films 12 and 2
Since the films 2 and 32 are also formed at a temperature of less than 600 ° C. or even less than 500 ° C., the etching resistance is low due to the presence of defects and the like as they are, but in this embodiment, the gate electrode forming conductive film 150 is patterned. First, a gate insulating film modifying step for improving the etching resistance of the gate insulating films 12, 22, 32 is performed. Therefore, the conductive film 150 for forming a gate electrode is etched to form the gate electrodes 14, 24, and 34.
Is formed, it is possible to prevent the gate insulating films 12, 22, and 32 from being abnormally etched. For example, in RIE dry etching using Cl ₂ + BCl ₃ gas, the etching rate of aluminum is 10
The etching rate is 0 nm / min to 150 nm / min, and the etching rate of the silicon oxide film without performing the gate insulating film modification step is 5 nm / min to 15 nm / min. Therefore, in the conventional method without performing the gate insulating film reforming step,
Assuming that the over-etching time is 50 seconds, the silicon oxide film used as the gate insulating film is 4 nm / mi.
As a result, abnormal etching is performed at a rate of n to 12 nm / min. As a result, the implantation depth at the time of ion implantation greatly varies, and the TFT characteristics vary. On the other hand, when the gate insulating film modification step is performed as in the present embodiment, the etching rate of the silicon oxide film becomes 0.1 in RIE dry etching using Cl ₂ + BCl ₃ gas.
Since it is reduced to 5 nm / min to 1.5 nm / min, even if over-etching is performed for 50 seconds, the thickness of the silicon oxide film used as the gate insulating films 12, 22, 32 is 0.1 mm. 4 nm / min ~
It is 1.2 nm / min. Therefore, the gate electrode 14,
When the formation of the gate insulating films 12 and 24 is completed,
Since the film thicknesses of the films 22 and 32 are constant, FIG.
In steps (B), (C), and (D), when impurities are introduced into the semiconductor film 100 via the gate insulating films 12, 22, 32 by a method such as ion implantation or ion implantation, The impurity concentration distribution in the depth direction can be easily controlled. That is, the acceleration voltage or the like at the time of introducing the impurity is controlled by the gate insulating films 12 and 2.
The optimum conditions are set according to the film thicknesses of the gate insulating films 2 and 32. According to the present embodiment, the film thicknesses of the gate insulating films 12, 22, and 32 do not change. Does not fluctuate. Therefore, the impurity can be introduced into the semiconductor film 100 under the optimum condition, so that the impurity concentration of the source / drain can be set to the optimum condition.

When the gate electrodes 14, 24, and 34 are formed by dry-etching the conductive film 150 for forming a gate electrode, the end portions of the gate electrodes 14, 24, and 34 of the gate insulating films 12, 22, and 32 are formed. 5 is not etched down to the portion located immediately below
In the steps shown in (A) and (B), the gate electrode 14,
Even when an impurity is introduced into the semiconductor film 100 using the masks 24 and 34 as a mask, the region into which the impurity is introduced can be reliably controlled. Therefore, as in the present embodiment, the gate electrodes 14, 24,
Even when the low-concentration impurities are introduced into the semiconductor film 100 using the mask 34 as a mask to manufacture the TFTs 10, 20, and 30 having the LDD structure, the LDDs of these TFTs 10, 20, and 30 are formed.
The length can be controlled reliably. Therefore, TFTs 10, 20, which have stable on-current characteristics and off-leak current characteristics,
30 can be manufactured.

Further, in the case of dry etching, since the etching selectivity is lower than that of wet etching, when the conductive film 150 for forming a gate electrode is etched, the gate insulating films 12, 22, and 32 are also likely to be etched. However, as in this embodiment, the gate insulating film 1
If the etching resistance of 2, 22, 32 is increased, even when dry etching is used to pattern the gate electrode forming conductive film 150, the gate insulating film 12,
22 and 32 can be prevented from being abnormally etched.

[Structure of Liquid Crystal Panel] FIGS. 6 and 7 show an example in which a liquid crystal panel for a liquid crystal display is formed by using the active matrix substrate 100 formed by such a method.
This will be described with reference to FIG.

FIGS. 6 and 7 are a plan view of the liquid crystal panel used in the liquid crystal display device according to the present embodiment as viewed from the side of the counter substrate, and a view of the liquid crystal panel taken along line HH 'in FIG. It is sectional drawing.

6 and 7, the liquid crystal panel 1 used in the liquid crystal display device has an active matrix substrate 200 on which pixel electrodes 45 are formed in a matrix and a counter substrate 40 on which a counter electrode 532 and a light shielding film 531 are formed.
0 and a liquid crystal 53 sealed and sandwiched between these substrates.
9 is roughly constituted. The active matrix substrate 200 and the opposing substrate 400 are formed by sealing material 552 including a gap material formed along the outer peripheral edge of the opposing substrate 400.
By a predetermined gap. Further, the active matrix substrate 200 and the counter substrate 400
Between the liquid crystal sealing area 54 and the sealing material 552.
0 are defined, and the liquid crystal 5
39 are enclosed. The active matrix substrate 200 and the opposing substrate 40
A spacer 537 is interposed between 0 and 0. Seal material 5
As 52, an epoxy resin or various ultraviolet curable resins can be used. In addition, as a gap material mixed in the sealing material 552, an inorganic or organic fiber or sphere of about 2 μm to about 10 μm is used.

The counter substrate 400 is smaller than the active matrix substrate 200,
The peripheral portion of 0 is bonded so as to protrude from the outer peripheral edge of the counter substrate 400. Accordingly, the driving circuits (the scanning line driving circuit 70 and the data line driving circuit 60) and the input / output terminals 545 of the active matrix substrate 200 are in a state of being exposed from the counter substrate 400. Here, since the sealant 552 is partially interrupted, the liquid crystal injection port 541 is formed by the interrupted portion. Therefore, the opposing substrate 4
00 and the active matrix substrate 200 are bonded to each other, and then the inside area of the sealing material 552 is depressurized,
The liquid crystal 539 can be injected under reduced pressure from the liquid crystal injection port 541. After the liquid crystal 539 is sealed, the liquid crystal injection port 541 is sealed with the sealing agent 542.
It should be closed with. The counter substrate 400 has a sealing material 5
A light-shielding film 555 for cutting off the screen display area 81 inside the area 52 is also formed. Also, the counter substrate 40
A vertical conductive material 556 for establishing electrical conduction between the active matrix substrate 30 and the counter substrate 400 is formed at any of the 0 corner portions.

Here, if the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 70 may be provided on only one side. Further, the data line driving circuits 60 may be arranged on both sides along the side of the screen display area 81. For example, an odd-numbered data line supplies an image signal from a data line driving circuit arranged along one side of the screen display area 81, and an even-numbered data line runs along the opposite side of the screen display area 81. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines are driven in a comb-tooth shape as described above, the formation area of the data line driving circuit 60 can be expanded, so that a complicated circuit can be formed. In the active matrix substrate 200, the data line driving circuit 6
On the side of the side opposite to 0, a precharge circuit or an inspection circuit may be provided by utilizing a portion under the light shielding film 555 or the like. Note that instead of forming the data line driving circuit 60 and the scanning line driving circuit 70 on the active matrix substrate 200, for example, a TA on which a driving LSI is mounted is mounted.
A B (tape automated, bonding) substrate may be electrically and mechanically connected to a terminal group formed on the periphery of the active matrix substrate 200 via an anisotropic conductive film. Also, the counter substrate 400
The type of liquid crystal 539 to be used, that is, TN (twisted nematic) mode, S
TN (super TN) mode, D-STN (double-S
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a TN) mode and a normally white mode / normally black mode.

When the liquid crystal panel 1 of the present embodiment is of a transmission type, it is used, for example, in a projection type liquid crystal display device (liquid crystal projector). In this case, three liquid crystal panels 1 are used as light valves for RGB, respectively.
The light of each color separated via the dichroic mirror for RGB color separation is incident on each of the liquid crystal panels 1 as projection light. Therefore, no color filter is formed on the liquid crystal panel 1 of the present embodiment. However,
A color liquid crystal display device such as a color liquid crystal television can be configured in addition to the projection type liquid crystal display by forming an RGB color filter together with its protective film in a region facing each pixel electrode 45 on the counter substrate 400. . Furthermore, a dichroic filter that creates RGB colors by utilizing the interference effect of light may be formed by stacking a number of interference layers having different refractive indexes on the counter substrate 400. According to the counter substrate with the dichroic filter, a brighter color display can be performed.

[0055]

As described above, according to the present invention, 60
Although the gate insulating film is formed at a temperature of less than 0 ° C. and further less than 500 ° C., before patterning the conductive film for forming a gate electrode, a gate insulating film modifying step for improving the etching resistance of the gate insulating film is performed. When the gate electrode is formed by etching the conductive film for forming a gate electrode, abnormal etching of the gate insulating film can be prevented. Therefore, when the formation of the gate electrode is completed,
Since the thickness of the gate insulating film is constant, when impurities are introduced into the semiconductor film through the gate insulating film by a method such as ion implantation or ion implantation, the impurity concentration distribution in the depth direction of the semiconductor film can be easily controlled. it can. Further, when the gate electrode is formed by dry-etching the conductive film for forming a gate electrode, a portion of the gate insulating film located immediately below an end of the gate electrode is not etched. Even when an impurity is introduced into a semiconductor film as a mask, an impurity introduction region can be reliably controlled. Therefore, a low-concentration impurity is introduced into the semiconductor film using the gate electrode as a mask to form the TF having the LDD structure.
Even when T is manufactured, the LDD length of the TFT can be reliably controlled.

[Brief description of the drawings]

FIG. 1A is a block diagram of an active matrix substrate for a liquid crystal display device, and FIG. 1B is an equivalent circuit diagram of a CMOS circuit forming a driving circuit thereof.

FIG. 2 is a sectional view of three types of TFTs formed on the active matrix substrate shown in FIG.

FIGS. 3A to 3D are process cross-sectional views illustrating a method for manufacturing the active matrix substrate shown in FIG. 2;

4 (A) to 4 (E) are cross-sectional views showing steps performed after the step shown in FIG. 3 in the method for manufacturing the active matrix substrate shown in FIG.

5 (A) to 5 (D) are cross-sectional views showing the steps performed after the step shown in FIG. 4 in the method for manufacturing the active matrix substrate shown in FIG.

FIG. 6 is a plan view of a liquid crystal panel for an active matrix type liquid crystal display device.

FIG. 7 is a sectional view taken along line HH ′ of FIG. 6;

FIGS. 8A to 8D are cross-sectional views showing steps from forming a gate insulating film to patterning a gate electrode in a conventional method for manufacturing an active matrix substrate.

FIGS. 9A and 9B are explanatory views showing problems that occur when a gate electrode is formed in a conventional method for manufacturing an active matrix substrate.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal panel 10 N-type TFT for drive circuit 20 P-type TFT for drive circuit 12, 22, 32 Gate insulating film 14, 24, 34 Gate electrode 15, 25, 35 Channel region 16, 26, 36 High concentration Source / drain region 17, 27, 37 Low-concentration source / drain region 30 TFT for pixel switching 40 Storage capacitor 41, 43, 44 Source electrode 42 Drain electrode 45 Pixel electrode 50 Substrate 51 Base protective film 52 Interlayer insulating film 60 Data side Drive circuit 61, 62, 63, 64, 65, 66 Resist mask 70 Scan side drive circuit 81 Screen display area 90 Data line 91 Scan line 94 Liquid crystal capacitor (liquid crystal cell) 100 Semiconductor film 150 Gate electrode conductive film 200 Active matrix Substrate (semiconductor device) 400 Counter substrate 531 Counter electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA59 HA28 JA25 JA40 JB51 KA04 KA10 KA12 KA18 KA19 MA07 MA08 MA19 MA22 MA27 MA30 MA37 MA41 NA22 NA24 PA06 PA09 PA11 PA13 QA07 QA10 RA05 5F058 BA01 BB04 BB07 B02BHB BH03H 5F110 AA17 AA26 BB02 BB04 CC02 DD02 DD13 EE03 EE04 EE06 EE14 EE44 FF02 FF30 FF36 GG02 GG13 GG25 GG42 GG43 GG45 GG47 HJ01 HJ04 HJ13 HJ23 HM14 HM15 NN02 NN72 PP03 QQ04 Q

Claims (9)

[Claims] A semiconductor film formed on a substrate;
Forming a gate insulating film under a temperature condition of less than 0 ° C .; forming a gate electrode forming conductive film on the surface of the gate insulating film; and forming a patterning mask on the surface of the gate electrode forming conductive film. Forming a gate electrode by forming the gate electrode by etching the conductive film for forming a gate electrode through the patterning mask, and then forming an active layer of the thin film transistor by the semiconductor film. In the method of manufacturing a device, after performing the gate insulating film forming step, before performing the gate electrode forming step, performing a gate insulating film modifying step of increasing the etching resistance of the gate insulating film is performed. A method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the gate electrode, the gate electrode is formed by dry etching the conductive film for forming a gate electrode. 3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of modifying the gate insulating film, an annealing process is performed on the gate insulating film. 4. The method according to claim 3, wherein the annealing is a heat treatment for heating the gate insulating film in an atmosphere of nitrogen gas, argon gas, helium gas, oxygen gas, or a mixed gas of these gases. A method for manufacturing a semiconductor device, comprising: 5. The method according to claim 3, wherein the annealing process is a lamp annealing process. 6. The method according to claim 3, wherein the annealing is a laser annealing. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the step of modifying the gate insulating film is a plasma treatment of irradiating the gate insulating film with plasma. 8. The plasma processing device according to claim 7, wherein in the plasma processing, oxygen plasma, hydrogen plasma,
And irradiating the semiconductor device with nitrogen plasma. 9. The method according to claim 1, wherein
The conductive film for forming a gate electrode is a conductive film in which any one of a metal film of an aluminum film, an aluminum-copper alloy film, a chromium film, a titanium film, and a tantalum film is formed in a single layer or a multilayer. Semiconductor device manufacturing method.