JP2002076199A - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JP2002076199A JP2002076199A JP2000264099A JP2000264099A JP2002076199A JP 2002076199 A JP2002076199 A JP 2002076199A JP 2000264099 A JP2000264099 A JP 2000264099A JP 2000264099 A JP2000264099 A JP 2000264099A JP 2002076199 A JP2002076199 A JP 2002076199A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- sealing material
- predetermined position
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 半導体装置と実装基板の間に形成された間隙
に封止材を充填した際の、封止材と実装基板の線膨張係
数および弾性係数の相違に起因した熱応力による配線の
断線を防止、あるいはその進行を遅らせる。
【解決手段】 配線１６の所定位置に幅広部１６ａを形
成し、配線１６の耐応力性を幅広部１６ａにおいて向上
させると共に、熱応力が集中するアンダーフィル樹脂２
０の端部２４を、幅広部１６ａ上に位置させる。
Abstract: PROBLEM TO BE SOLVED: To provide a heat caused by a difference between a linear expansion coefficient and an elastic coefficient between a sealing material and a mounting substrate when a gap formed between the semiconductor device and the mounting substrate is filled with the sealing material. Prevents disconnection of wiring due to stress or delays its progress. A wide portion (16a) is formed at a predetermined position of a wiring (16) to improve the stress resistance of the wiring (16) in the wide portion (16a) and to concentrate an underfill resin (2) on which thermal stress is concentrated.
The zero end portion 24 is located on the wide portion 16a.
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体装置の実
装構造に関し、より具体的には、ＢＧＡ（Ball Grid Ar
ray)やＦＣ（Flip Chip ）などのはんだバンプを有する
半導体装置の実装基板への実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure, and more specifically, to a BGA (Ball Grid Arrangement).
The present invention relates to a mounting structure of a semiconductor device having solder bumps such as a ray chip or an FC (flip chip) on a mounting substrate.
【０００２】[0002]
【従来の技術】図５を参照し、従来技術に係る半導体装
置の実装構造についてその工程をおいながら説明する
と、先ず、同図（ａ）に示すように、はんだバンプ１０
０を有する半導体装置１０２と実装基板１０４とを接続
する。この接続は、はんだバンプ１００を実装基板１０
４に設けられた電極パッド（図示せず）に接触させつつ
加熱溶融（リフロー）することにより行われる。尚、実
装基板１０４は、基材１０４ａとはんだ付け不要部分を
覆うレジスト（ビルドアップ法により製造されるビルド
アップ基板においてはレジストおよびビルドアップ層）
１０４ｂからなる。2. Description of the Related Art Referring to FIG. 5, the mounting structure of a semiconductor device according to the prior art will be described with reference to its steps. First, as shown in FIG.
The semiconductor device 102 having 0 and the mounting substrate 104 are connected. This connection is performed by connecting the solder bumps 100 to the mounting substrate 10.
This is performed by heating and melting (reflowing) while making contact with an electrode pad (not shown) provided in 4. The mounting substrate 104 is made of a resist covering the base material 104a and a portion not requiring soldering (resist and a build-up layer in a build-up substrate manufactured by a build-up method).
104b.
【０００３】このように接続された半導体装置１０２お
よび実装基板１０４が、車両のエンジンルームなどの温
度変化や振動、衝撃が生じる環境に配置されると、繰り
返しの熱的負荷、より具体的には半導体装置１０２と実
装基板１０４との線膨張係数および弾性係数の相違に起
因して生じる熱応力がはんだバンプ１００に集中すると
共に、振動や衝撃による応力もはんだバンプ１００に集
中し、前記はんだバンプ１００に亀裂が発生することが
ある。When the semiconductor device 102 and the mounting board 104 connected as described above are placed in an environment where a temperature change, vibration, or impact occurs, such as an engine room of a vehicle, a repetitive thermal load, more specifically, The thermal stress generated due to the difference between the linear expansion coefficient and the elastic coefficient between the semiconductor device 102 and the mounting board 104 is concentrated on the solder bump 100, and the stress due to vibration and impact is also concentrated on the solder bump 100. Cracks may occur.
【０００４】このため、従来、半導体装置１０２と実装
基板１０４の間に形成される間隙に封止材（アンダーフ
ィル樹脂）を充填し、よってはんだバンプ１００に集中
する熱応力および振動、衝撃による応力を封止材に分散
させることにより、はんだバンプ１００における亀裂の
発生を抑制している。For this reason, conventionally, a gap formed between the semiconductor device 102 and the mounting substrate 104 is filled with a sealing material (underfill resin), so that the thermal stress concentrated on the solder bump 100 and the stress due to vibration and impact. Is dispersed in the sealing material, thereby suppressing the occurrence of cracks in the solder bumps 100.
【０００５】具体的には、図５（ｂ）に示すように、半
導体装置１０２の周辺の実装基板１０４上に、ニードル
１０６などを用いて封止材１０８を塗布する。塗布され
た封止材１０８は、毛細管現象によって、同図（ｃ）に
示すように半導体装置１０２と実装基板１０４の間隙に
隙間なく充填され、よって従来技術に係る半導体装置の
実装構造が完成する。尚、封止材１０８を充填すると、
通常、半導体装置１０２の端部からその外方の実装基板
１０４上にかけてフィレット部１１０が形成される。図
６に、図５（ｃ）、即ち、従来技術に係る半導体装置の
実装構造を上方から見た平面図を示す。More specifically, as shown in FIG. 5B, a sealing material 108 is applied to the mounting substrate 104 around the semiconductor device 102 by using a needle 106 or the like. The applied sealing material 108 fills the gap between the semiconductor device 102 and the mounting substrate 104 without gaps by the capillary phenomenon as shown in FIG. 3C, thereby completing the mounting structure of the semiconductor device according to the prior art. . When the sealing material 108 is filled,
Usually, a fillet portion 110 is formed from the end of the semiconductor device 102 to the mounting board 104 outside the end. FIG. 6 is a plan view of FIG. 5C, that is, a top view of the mounting structure of the semiconductor device according to the prior art.
【０００６】[0006]
【発明が解決しようとする課題】上記のように、はんだ
バンプ１００における亀裂の発生を抑制するために半導
体装置１０２と実装基板１０４の間隙に封止材１０８を
充填する場合、充填する封止材１０８の物性値（性質）
は、その目的から線膨張係数が低く（温度変化に起因す
る伸縮量が少なく）、かつ弾性係数が大きい（応力に起
因する変形量が少ない）ことが好ましい。具体的には、
線膨張係数が２０〜４０〔ｐｐｍ／°Ｃ〕程度で、かつ
弾性係数が５〜１０〔ＧＰａ〕程度のエポキシ系樹脂を
主成分とした封止材が使用されることが多い。As described above, when filling the gap between the semiconductor device 102 and the mounting substrate 104 with the sealing material 108 in order to suppress the occurrence of cracks in the solder bumps 100, the sealing material to be filled is used. Physical property value (property) of 108
For that purpose, it is preferable that the coefficient of linear expansion be low (the amount of expansion and contraction caused by temperature change is small) and the elastic coefficient is large (the amount of deformation caused by stress is small). In particular,
In many cases, a sealing material whose main component is an epoxy resin having a linear expansion coefficient of about 20 to 40 [ppm / ° C.] and an elastic coefficient of about 5 to 10 [GPa] is used.
【０００７】一方、実装基板１０４の物性値は、広く一
般に使用されているガラスエポキシ系の基材１０４ａ
で、平面方向の線膨張係数が１２〜１６〔ｐｐｍ／°
Ｃ〕程度、弾性係数が２０〔ＧＰａ〕程度である。On the other hand, the physical properties of the mounting substrate 104 are based on the glass epoxy base material 104a which is widely used in general.
And the linear expansion coefficient in the plane direction is 12 to 16 ppm / °
C] and the elastic coefficient is about 20 [GPa].
【０００８】また、レジスト（あるいはレジストおよび
ビルドアップ層）１０４ｂは、線膨張係数が４０〜７０
〔ｐｐｍ／°Ｃ〕程度、弾性係数が１〜３〔ＧＰａ〕程
度である。The resist (or the resist and the build-up layer) 104b has a linear expansion coefficient of 40 to 70.
[Ppm / ° C.] and an elastic coefficient of about 1 to 3 [GPa].
【０００９】このように、封止材１０８と実装基板１０
４（基材１０４ａ、レジスト（あるいはレジストおよび
ビルドアップ層）１０４ｂ）の線膨張係数および弾性係
数は大きく相違する。このため、前述の如く、半導体装
置１０２と実装基板１０４との線膨張係数および弾性係
数の相違に起因して熱応力が生じるのと同様に、封止材
１０８と実装基板１０４の線膨張係数および弾性係数の
相違によっても熱応力が生じる。As described above, the sealing material 108 and the mounting substrate 10
4 (base material 104a, resist (or resist and build-up layer) 104b) have significantly different coefficients of linear expansion and elasticity. For this reason, as described above, similarly to the case where thermal stress is generated due to the difference between the linear expansion coefficient and the elastic coefficient between the semiconductor device 102 and the mounting substrate 104, the linear expansion coefficient and the Thermal stress also occurs due to the difference in elastic modulus.
【００１０】封止材１０８と実装基板１０４間に生じた
熱応力は、図５および図６に符号１１２で示す封止材１
０８の端部、より具体的には、フィレット部１１０の端
部に集中する。そのため、端部１１２の下方の実装基板
表層に配置された配線１１４が断線されることがあり、
接続に対する信頼性の低下につながっていた。The thermal stress generated between the sealing member 108 and the mounting substrate 104 is the same as that of the sealing member 1 indicated by reference numeral 112 in FIGS.
08, more specifically, at the end of the fillet 110. Therefore, the wiring 114 arranged on the surface layer of the mounting board below the end 112 may be disconnected,
This has led to a decrease in the reliability of the connection.
【００１１】従って本発明の目的は、半導体装置と実装
基板の間隙に封止材を充填した際の封止材の端部下方に
配置された配線の断線を防止、あるいはその進行を遅ら
せ、よって接続に対する信頼性を向上させることができ
るようにした半導体装置の実装構造を提供することにあ
る。Accordingly, an object of the present invention is to prevent disconnection of a wiring disposed below an end of a sealing material when a gap between the semiconductor device and a mounting substrate is filled with the sealing material, or to delay the progress thereof. An object of the present invention is to provide a semiconductor device mounting structure capable of improving the reliability of connection.
【００１２】[0012]
【課題を解決するための手段】上記した課題を解決する
ために、請求項１項においては、はんだバンプを用いて
半導体装置を実装基板上に接続すると共に、前記半導体
装置と実装基板との間隙に封止材を充填する半導体装置
の実装構造において、前記実装基板の表層に配置された
配線の幅を、所定位置において拡大すると共に、前記封
止材の端部を前記拡大した配線上に形成する如く構成し
た。According to one aspect of the present invention, a semiconductor device is connected to a mounting substrate using solder bumps and a gap between the semiconductor device and the mounting substrate. In the mounting structure of the semiconductor device in which the sealing material is filled, the width of the wiring arranged on the surface layer of the mounting substrate is increased at a predetermined position, and the end of the sealing material is formed on the expanded wiring. It was configured so that
【００１３】実装基板の表層に配置された配線の幅を、
所定位置において拡大すると共に、封止材の端部を拡大
した配線上に形成する如く構成した、即ち、封止材の端
部下方に配置される配線の幅を拡大し、耐応力性を向上
させたので、半導体装置と実装基板の間隙に封止材を充
填した際の封止材の端部下方に配置された配線の断線を
防止、あるいはその進行を遅らせることができ、よって
接続に対する信頼性を向上させることができる。The width of the wiring arranged on the surface layer of the mounting board is
It is configured to be enlarged at a predetermined position and to form the end of the sealing material on the enlarged wiring, that is, to increase the width of the wiring disposed below the end of the sealing material and improve the stress resistance. Therefore, it is possible to prevent disconnection of the wiring arranged under the end of the sealing material when the gap between the semiconductor device and the mounting board is filled with the sealing material, or to delay the progress thereof, and thus to improve the reliability of the connection. Performance can be improved.
【００１４】請求項２項においては、はんだバンプを用
いて半導体装置を実装基板上に接続すると共に、前記半
導体装置と実装基板との間隙に封止材を充填する半導体
装置の実装構造において、前記実装基板の表層に配置さ
れた配線を第１の所定位置において少なくとも２本以上
の複数本の配線に分岐させ、さらに前記分岐させた複数
本の配線を第２の所定位置において再度結合させると共
に、前記封止材の端部を前記第１の所定位置と第２の所
定位置の間に形成する如く構成した。According to a second aspect of the present invention, in the semiconductor device mounting structure, the semiconductor device is connected to the mounting substrate using solder bumps, and a sealing material is filled in a gap between the semiconductor device and the mounting substrate. Wiring arranged on the surface layer of the mounting substrate is branched into at least two or more wirings at a first predetermined position, and the branched wirings are re-coupled at a second predetermined position, The end of the sealing material is formed between the first predetermined position and the second predetermined position.
【００１５】実装基板の表層に配置された配線を第１の
所定位置において少なくとも２本以上の複数本の配線に
分岐させ、さらに分岐させた複数本の配線を第２の所定
位置において再度結合させると共に、封止材の端部を第
１の所定位置と第２の所定位置の間に形成する如く構成
した、即ち、封止材の端部下方に配置される配線を少な
くとも２本の配線に分岐させるようにしたので、封止材
の端部に集中した熱応力によりそのうちの１本（ｎ本に
分岐した場合はｎ−１本）が切断されたとしても、配線
全体としては断線したことにならず、よって半導体装置
と実装基板の間隙に封止材を充填した際の接続に対する
信頼性を向上させることができる。The wiring arranged on the surface layer of the mounting substrate is branched into at least two or more wirings at a first predetermined position, and the branched wirings are reconnected at a second predetermined position. At the same time, the end of the sealing material is formed between the first predetermined position and the second predetermined position, that is, the wiring arranged below the end of the sealing material is reduced to at least two wirings. Since the branch is made, even if one of them (n-1 if it branches into n) is cut by the thermal stress concentrated on the end of the sealing material, the whole wiring is broken. Therefore, the reliability of the connection when the gap between the semiconductor device and the mounting board is filled with the sealing material can be improved.
【００１６】[0016]
【発明の実施の形態】以下、添付した図面を参照して、
本発明に係る半導体装置の実装構造について説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The mounting structure of the semiconductor device according to the present invention will be described.
【００１７】図１は、本発明の一つの実施の形態に係る
半導体装置の実装構造を説明する説明断面図であり、図
２は図１に示す半導体装置の実装構造を上方から見た平
面図である。FIG. 1 is an explanatory sectional view for explaining a mounting structure of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a plan view of the mounting structure of the semiconductor device shown in FIG. It is.
【００１８】図１および図２を参照し、本発明の一つの
実施の形態に係る半導体装置の実装構造についてその工
程をおいながら説明すると、先ず、図１（ａ）に示すよ
うに、ＢＧＡやＦＣなどのはんだバンプ１０を有する半
導体装置１２を、実装基板（以下、単に「基板」とい
う）１４に接続する。この接続は、はんだバンプ１０を
基板１４に設けられた電極パッド（図示せず）に接触さ
せつつ加熱溶融（リフロー）することにより行われる。
尚、基板１４は、基材１４ａとはんだ付け不要部分を覆
うレジスト（ビルドアップ法により製造されるビルドア
ップ基板においてはレジストおよびビルドアップ層）１
４ｂからなる。Referring to FIGS. 1 and 2, the mounting structure of a semiconductor device according to an embodiment of the present invention will be described while describing the steps. First, as shown in FIG. A semiconductor device 12 having a solder bump 10 such as FC is connected to a mounting substrate (hereinafter simply referred to as “substrate”) 14. This connection is performed by heating and melting (reflowing) the solder bump 10 while contacting it with an electrode pad (not shown) provided on the substrate 14.
The substrate 14 is made of a resist (a resist and a build-up layer in the case of a build-up substrate manufactured by a build-up method) covering the base material 14a and portions not requiring soldering.
4b.
【００１９】また、基板１４の表層に配置される配線１
６を、所定位置、具体的には半導体装置１２の端部から
所定距離だけ離間した位置において、図２によく示すよ
うな幅広部１６ａを有するように形成する。即ち、基板
１４の表層に配置された配線１６の所定位置に幅広部１
６ａを設け、その位置における幅を他に位置する配線１
６の幅に比して拡大することで、配線１６の耐応力性を
幅広部１６ａにおいて向上させるようにする。The wiring 1 arranged on the surface layer of the substrate 14
6 is formed at a predetermined position, specifically, at a position separated by a predetermined distance from an end of the semiconductor device 12, so as to have a wide portion 16a as well shown in FIG. That is, the wide portion 1 is provided at a predetermined position of the wiring 16 disposed on the surface layer of the substrate 14.
6a, and the width of the wiring 1 at another position
6, the stress resistance of the wiring 16 is improved in the wide portion 16a.
【００２０】次いで、図１（ｂ）に示すように、半導体
装置１２周辺の基板１４上に、ニードル１８などを用い
てエポキシ系のアンダーフィル樹脂（前記した封止材）
２０を塗布する。尚、アンダーフィル樹脂２０の物性
値、より詳しくは、線膨張係数および弾性係数は、はん
だバンプ１０を保護するのに十分な値、例えば、従来技
術で述べたように、線膨張係数が２０〜４０〔ｐｐｍ／
°Ｃ〕程度、弾性係数が５〜１０〔ＧＰａ〕程度に設定
される。Next, as shown in FIG. 1B, an epoxy-based underfill resin (the above-described sealing material) is formed on the substrate 14 around the semiconductor device 12 by using a needle 18 or the like.
Apply 20. The physical property value of the underfill resin 20, more specifically, the coefficient of linear expansion and the coefficient of elasticity are values sufficient to protect the solder bump 10, for example, as described in the related art, the coefficient of linear expansion is 20 to 40 [ppm /
° C] and the elastic modulus is set to about 5 to 10 [GPa].
【００２１】塗布されたアンダーフィル樹脂２０は、毛
細管現象によって、同図（ｃ）に示すように半導体装置
１２と基板１４の間に形成された間隙に隙間なく充填さ
れる。The applied underfill resin 20 fills the gap formed between the semiconductor device 12 and the substrate 14 without any gap by capillary action as shown in FIG.
【００２２】尚、アンダーフィル樹脂２０は、半導体装
置１２と基板１４の間隙に充填、硬化された際に、その
端部、より具体的には表面張力により形成されるフィレ
ット部２２の端部２４が前記した幅広部１６ａ上に位置
するまで塗布される。このようにして同図（ｃ）および
図２に示す、本発明の一つの実施の形態に係る半導体装
置の実装構造を得る。When the underfill resin 20 is filled in the gap between the semiconductor device 12 and the substrate 14 and cured, the end portion thereof, more specifically, the end portion 24 of the fillet portion 22 formed by surface tension. Is applied until it is located on the wide portion 16a. Thus, the mounting structure of the semiconductor device according to one embodiment of the present invention shown in FIG.
【００２３】このように、配線１６の耐応力性を幅広部
１６ａにおいて向上させると共に、熱応力が集中するア
ンダーフィル樹脂の端部２４を前記した幅広部１６ａ上
に位置するようにしたので、半導体装置１２と基板１４
の間隙にアンダーフィル樹脂２０を充填した際のアンダ
ーフィル樹脂の端部２４下方に配置された配線１６（幅
広部１６ａ）の断線を防止、あるいはその進行を遅らせ
ることができ、よって接続に対する信頼性を向上させる
ことができる。As described above, the stress resistance of the wiring 16 is improved in the wide portion 16a, and the end 24 of the underfill resin where the thermal stress is concentrated is located on the wide portion 16a. Device 12 and substrate 14
Can prevent the disconnection of the wiring 16 (wide portion 16a) disposed below the end portion 24 of the underfill resin when the underfill resin 20 is filled in the gap, or delay the progress thereof, thereby improving the reliability of the connection. Can be improved.
【００２４】尚、上記において、半導体装置１２を囲う
適宜な型枠などを用いてフィレット部２２を形成しない
ようにしてもよく、この場合、幅広部１６ａは半導体装
置１２の端部下方に形成すればよい。In the above description, the fillet portion 22 may not be formed using an appropriate mold or the like surrounding the semiconductor device 12, and in this case, the wide portion 16a is formed below the end of the semiconductor device 12. I just need.
【００２５】次いで、本発明の第２の実施の形態に係る
半導体装置の実装構造および実装方法について説明す
る。尚、前述の実施の形態と同様な構成については同一
符号を付し、説明を省略する。Next, a mounting structure and a mounting method of a semiconductor device according to a second embodiment of the present invention will be described. The same components as those of the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.
【００２６】図３は本発明の第２の実施の形態に係る半
導体装置の実装構造を説明する説明断面図であり、図４
は図３に示す半導体装置の実装構造を上方から見た平面
図である。FIG. 3 is an explanatory sectional view for explaining a mounting structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a plan view of the mounting structure of the semiconductor device shown in FIG. 3 as viewed from above.
【００２７】図３および図４を参照し、本発明の一つの
実施の形態に係る半導体装置の実装構造についてその工
程をおいながら説明すると、先ず、図１（ａ）に示すよ
うに、はんだバンプ１０を有する半導体装置１２を、基
板１４に接続する。A mounting structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4. First, as shown in FIG. The semiconductor device 12 having 10 is connected to the substrate 14.
【００２８】ここで、基板１４の表層に配置される配線
１６について説明すると、表層に配置される配線１６
は、図４によく示すように、第１の所定位置Ａ、具体的
には半導体装置１２の端部から所定距離だけ離間した位
置において、第１の配線１６ｂと第２の配線１６ｃとに
分岐される。Here, the wiring 16 disposed on the surface of the substrate 14 will be described.
As shown in FIG. 4, at a first predetermined position A, specifically, at a position separated from the end of the semiconductor device 12 by a predetermined distance, a first wiring 16b and a second wiring 16c are branched. Is done.
【００２９】また、分岐された第１の配線１６ｂおよび
第２の配線１６ｃは、第２の所定位置Ｂ、具体的には第
１の所定位置Ａから所定距離だけ離間した位置において
再度結合される。即ち、第１の所定位置Ａから第２の所
定位置Ｂの間において、配線１６が２本の配線（第１の
配線１６ｂおよび第２の配線１６ｃ）に分岐されるよう
にする。The branched first wiring 16b and second wiring 16c are reconnected at a second predetermined position B, specifically, at a position separated by a predetermined distance from the first predetermined position A. . That is, between the first predetermined position A and the second predetermined position B, the wiring 16 is branched into two wirings (a first wiring 16b and a second wiring 16c).
【００３０】次いで、図３（ｂ）に示すように、半導体
装置１２周辺の基板１４上に、ニードル１８などを用い
てエポキシ系のアンダーフィル樹脂（前記した封止材）
２０を塗布する。尚、アンダーフィル樹脂２０の物性値
は、前述の実施例同様、はんだバンプ１０を保護するの
に十分な値、例えば、線膨張係数が２０〜４０〔ｐｐｍ
／°Ｃ〕程度、弾性係数が５〜１０〔ＧＰａ〕程度に設
定される。Next, as shown in FIG. 3B, an epoxy-based underfill resin (the above-described sealing material) is formed on the substrate 14 around the semiconductor device 12 using a needle 18 or the like.
Apply 20. In addition, the physical property value of the underfill resin 20 is a value sufficient to protect the solder bumps 10, for example, the linear expansion coefficient is 20 to 40 ppm as in the above-described embodiment.
/ ° C] and an elastic coefficient of about 5 to 10 [GPa].
【００３１】塗布されたアンダーフィル樹脂１８は、毛
細管現象によって、同図（ｃ）に示すように半導体装置
１２と基板１４の間に形成された間隙に隙間なく充填さ
れる。The applied underfill resin 18 is filled without gap into the gap formed between the semiconductor device 12 and the substrate 14 by capillary action as shown in FIG.
【００３２】尚、アンダーフィル樹脂２０は、半導体装
置１２と基板１４の間隙に充填、硬化された際に、その
端部、より具体的にはフィレット部２２の端部２４が前
記した第１の所定位置Ａと第２の所定位置Ｂの間に位置
するまで塗布される。即ち、アンダーフィル樹脂の端部
２４が、分岐された２本の配線（第１の配線１６ｂと第
２の配線１６ｃ）上に位置するようにする。このように
して同図（ｃ）および図２に示す、本発明の第２の実施
の形態に係る半導体装置の実装構造を得る。When the underfill resin 20 is filled in the gap between the semiconductor device 12 and the substrate 14 and cured, the end of the underfill resin 20, more specifically, the end 24 of the fillet portion 22, is filled with the first filling material. It is applied until it is located between the predetermined position A and the second predetermined position B. That is, the end portion 24 of the underfill resin is located on the two branched wires (the first wire 16b and the second wire 16c). Thus, the mounting structure of the semiconductor device according to the second embodiment of the present invention shown in FIG.
【００３３】このように、本発明の第２の実施の形態に
おいては、第１の所定位置Ａから第２の所定位置Ｂの間
において、配線１６を２本の配線（第１の配線１６ｂお
よび第２の配線１６ｃ）に分岐させると共に、アンダー
フィル樹脂の端部２４を前記した第１の所定位置Ａと第
２の所定位置Ｂの間に位置するようにしたので、アンダ
ーフィル樹脂の端部２４に集中した熱応力により、分岐
された２本の配線（第１の配線１６ｂおよび第２の配線
１６ｃ）のうちの１本が切断されたとしても、配線全体
としては断線したことにならず、よって半導体装置と実
装基板の間隙に封止材を充填した際の接続に対する信頼
性を向上させることができる。As described above, in the second embodiment of the present invention, between the first predetermined position A and the second predetermined position B, the wiring 16 is divided into two wirings (the first wiring 16b and the first wiring 16b). Since the branch is made to the second wiring 16c) and the end 24 of the underfill resin is located between the first predetermined position A and the second predetermined position B, the end of the underfill resin is formed. Even if one of the two branched wirings (the first wiring 16b and the second wiring 16c) is cut due to the thermal stress concentrated on 24, the entire wiring does not break. Therefore, the reliability of connection when the gap between the semiconductor device and the mounting substrate is filled with the sealing material can be improved.
【００３４】尚、上記において、半導体装置１２を囲う
適宜な型枠などを用いてフィレット部２２を形成しない
ようにしてもよく、この場合、分岐された２本の配線１
６ｂと１６ｃが半導体装置１２の下方に位置するように
第１の所定位置Ａおよび第２の所定位置Ｂを設定すれば
よい。In the above, the fillet portion 22 may not be formed by using an appropriate mold or the like surrounding the semiconductor device 12, and in this case, the two branched wires 1
The first predetermined position A and the second predetermined position B may be set so that 6b and 16c are located below the semiconductor device 12.
【００３５】また、配線１６を２本の配線（第１の配線
１６ｂおよび第２の配線１６ｃ）に分岐させるようにし
たが、それに限られるものではなく、３本以上に分岐さ
せてもよい。Although the wiring 16 is branched into two wirings (the first wiring 16b and the second wiring 16c), the present invention is not limited to this. The wiring 16 may be branched into three or more wirings.
【００３６】上記した如く、本発明の実施の形態におい
ては、配線１６の耐応力性を幅広部１６ａにおいて向上
させると共に、熱応力が集中するアンダーフィル樹脂の
端部２４を前記した幅広部１６ａ上に位置するようにし
たので、半導体装置１２と基板１４の間隙にアンダーフ
ィル樹脂２０を充填した際のアンダーフィル樹脂の端部
２４下方に配置された配線１６（幅広部１６ａ）の断線
を防止、あるいはその進行を遅らせることができ、よっ
て接続に対する信頼性を向上させることができる。As described above, in the embodiment of the present invention, the stress resistance of the wiring 16 is improved in the wide portion 16a, and the end 24 of the underfill resin where the thermal stress is concentrated is placed on the wide portion 16a. To prevent disconnection of the wiring 16 (wide portion 16a) disposed below the end 24 of the underfill resin when the gap between the semiconductor device 12 and the substrate 14 is filled with the underfill resin 20. Alternatively, the progress can be delayed, so that the reliability of the connection can be improved.
【００３７】また、第１の所定位置Ａから第２の所定位
置Ｂの間において、配線１６を２本の配線（第１の配線
１６ｂおよび第２の配線１６ｃ）に分岐させると共に、
アンダーフィル樹脂の端部２４を前記した第１の所定位
置Ａと第２の所定位置Ｂの間に位置するようにしたの
で、アンダーフィル樹脂の端部２４に集中した熱応力に
より、分岐させた２本の配線（第１の配線１６ｂおよび
第２の配線１６ｃ）のうちの１本が切断されたとして
も、配線全体としては断線したことにならず、よって半
導体装置と実装基板の間隙に封止材を充填した際の接続
に対する信頼性を向上させることができる。Between the first predetermined position A and the second predetermined position B, the wiring 16 is branched into two wirings (a first wiring 16b and a second wiring 16c).
Since the end 24 of the underfill resin is located between the first predetermined position A and the second predetermined position B, the underfill resin is branched by the thermal stress concentrated on the end 24 of the underfill resin. Even if one of the two wirings (the first wiring 16b and the second wiring 16c) is cut, the entire wiring is not disconnected, and therefore, is sealed in the gap between the semiconductor device and the mounting board. The reliability of the connection when the stopper is filled can be improved.
【００３８】以上のように、本発明の実施の形態にあっ
ては、はんだバンプ１０を用いて半導体装置１２を実装
基板（基板）１４上に接続すると共に、前記半導体装置
と実装基板との間隙に封止材（アンダーフィル樹脂２
０）を充填する半導体装置の実装構造において、前記実
装基板の表層に配置された配線１６の幅を、所定位置に
おいて拡大する（幅広部１６ａ）と共に、前記封止材の
端部２４を前記拡大した配線上に形成する如く構成し
た。As described above, in the embodiment of the present invention, the semiconductor device 12 is connected to the mounting substrate (substrate) 14 by using the solder bumps 10 and the gap between the semiconductor device and the mounting substrate. Sealing material (underfill resin 2)
0), the width of the wiring 16 arranged on the surface layer of the mounting substrate is increased at a predetermined position (wide portion 16a), and the end portion 24 of the sealing material is enlarged. It was configured to be formed on the formed wiring.
【００３９】また、はんだバンプ１０を用いて半導体装
置１２を実装基板（基板）１４上に接続すると共に、前
記半導体装置と実装基板との間隙に封止材（アンダーフ
ィル樹脂２０）を充填する半導体装置の実装構造におい
て、前記実装基板の表層に配置された配線１６を第１の
所定位置Ａにおいて少なくとも２本以上の複数本の配線
（第１の配線１６ｂ、第２の配線１６ｃ）に分岐させ、
さらに前記分岐させた複数本の配線を第２の所定位置Ｂ
において再度結合させると共に、前記封止材の端部２４
を前記第１の所定位置と第２の所定位置の間に形成する
如く構成した。Further, the semiconductor device 12 is connected to the mounting substrate (substrate) 14 using the solder bumps 10, and a gap between the semiconductor device and the mounting substrate is filled with a sealing material (underfill resin 20). In the mounting structure of the device, the wiring 16 disposed on the surface layer of the mounting substrate is branched into at least two or more wirings (first wiring 16b and second wiring 16c) at a first predetermined position A. ,
Further, the plurality of branched wires are connected to a second predetermined position B.
At the end of the sealing material.
Is formed between the first predetermined position and the second predetermined position.
【００４０】[0040]
【発明の効果】請求項１項記載の発明にあっては、封止
材の端部下方に配置される配線の幅を拡大し、耐応力性
を向上させたので、半導体装置と実装基板の間隙に封止
材を充填した際の封止材の端部下方に配置された配線の
断線を防止、あるいはその進行を遅らせることができ、
よって接続に対する信頼性を向上させることができる。According to the first aspect of the present invention, the width of the wiring disposed below the end of the sealing material is increased, and the stress resistance is improved. It is possible to prevent disconnection of the wiring arranged below the end of the sealing material when filling the gap with the sealing material, or to delay the progress thereof,
Therefore, the reliability of the connection can be improved.
【００４１】請求項２項記載の発明にあっては、封止材
の端部下方に配置される配線を少なくとも２本の配線に
分岐させるようにしたので、封止材の端部に集中した熱
応力によりそのうちの１本（ｎ本に分岐した場合はｎ−
１本）が切断されたとしても、配線全体としては断線し
たことにならず、よって半導体装置と実装基板の間隙に
封止材を充填した際の接続に対する信頼性を向上させる
ことができる。According to the second aspect of the present invention, the wiring arranged below the end of the sealing material is branched into at least two wirings, so that the wiring is concentrated at the end of the sealing material. One of them (if n branches, n-
Even if one of them is cut, it does not mean that the entire wiring is broken, so that the reliability of the connection when the gap between the semiconductor device and the mounting substrate is filled with the sealing material can be improved.
【図１】本発明の一つの実施の形態に係る半導体装置の
実装構造を説明する説明断面図である。FIG. 1 is an explanatory cross-sectional view illustrating a mounting structure of a semiconductor device according to one embodiment of the present invention.
【図２】図１に示す半導体装置の実装構造を上方からみ
た平面図である。FIG. 2 is a plan view of the mounting structure of the semiconductor device shown in FIG. 1 as viewed from above.
【図３】本発明の第２の実施の形態に係る半導体装置の
実装構造を説明する説明断面図である。FIG. 3 is an explanatory sectional view illustrating a mounting structure of a semiconductor device according to a second embodiment of the present invention.
【図４】図３に示す半導体装置の実装構造を上方からみ
た平面図である。4 is a plan view of the mounting structure of the semiconductor device shown in FIG. 3 as viewed from above.
【図５】従来技術に係る半導体装置の実装構造を説明す
る説明断面図である。FIG. 5 is an explanatory cross-sectional view illustrating a mounting structure of a semiconductor device according to a conventional technique.
【図６】図５に示す半導体装置の実装構造を上方からみ
た平面図である。6 is a plan view of the mounting structure of the semiconductor device shown in FIG. 5 as viewed from above.
１０ はんだバンプ １２ 半導体装置 １４ 基板（実装基板） １６ 配線 １６ａ 幅広部 １６ｂ 第１の配線 １６ｃ 第２の配線 ２０ アンダーフィル樹脂（封止材） ２４ アンダーフィル樹脂（封止材）の端部 Ａ 第１の所定位置 Ｂ 第２の所定位置 DESCRIPTION OF SYMBOLS 10 Solder bump 12 Semiconductor device 14 Substrate (mounting board) 16 Wiring 16a Wide part 16b First wiring 16c Second wiring 20 Underfill resin (sealing material) 24 End of underfill resin (sealing material) A 1 predetermined position B 2nd predetermined position
Claims (2)
基板上に接続すると共に、前記半導体装置と実装基板と
の間隙に封止材を充填する半導体装置の実装構造におい
て、前記実装基板の表層に配置された配線の幅を、所定
位置において拡大すると共に、前記封止材の端部を前記
拡大した配線上に形成することを特徴とする半導体装置
の実装構造。In a semiconductor device mounting structure in which a semiconductor device is connected to a mounting substrate using solder bumps and a sealing material is filled in a gap between the semiconductor device and the mounting substrate, the surface layer of the mounting substrate is provided. A mounting structure of a semiconductor device, wherein the width of the arranged wiring is enlarged at a predetermined position, and an end of the sealing material is formed on the enlarged wiring.
基板上に接続すると共に、前記半導体装置と実装基板と
の間隙に封止材を充填する半導体装置の実装構造におい
て、前記実装基板の表層に配置された配線を第１の所定
位置において少なくとも２本以上の複数本の配線に分岐
させ、さらに前記分岐させた複数本の配線を第２の所定
位置において再度結合させると共に、前記封止材の端部
を前記第１の所定位置と第２の所定位置の間に形成する
ことを特徴とする半導体装置の実装構造。2. A mounting structure for a semiconductor device, wherein a semiconductor device is connected to a mounting substrate using solder bumps and a sealing material is filled in a gap between the semiconductor device and the mounting substrate. The arranged wiring is branched into a plurality of at least two or more wirings at a first predetermined position, and the plurality of branched wirings are re-coupled at a second predetermined position. A mounting structure for a semiconductor device, wherein an end is formed between the first predetermined position and the second predetermined position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000264099A JP4347506B2 (en) | 2000-08-31 | 2000-08-31 | Mounting structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000264099A JP4347506B2 (en) | 2000-08-31 | 2000-08-31 | Mounting structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002076199A true JP2002076199A (en) | 2002-03-15 |
| JP4347506B2 JP4347506B2 (en) | 2009-10-21 |
Family
ID=18751561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000264099A Expired - Fee Related JP4347506B2 (en) | 2000-08-31 | 2000-08-31 | Mounting structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4347506B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013183002A (en) * | 2012-03-01 | 2013-09-12 | Ibiden Co Ltd | Electronic component |
| US20140124941A1 (en) * | 2011-10-21 | 2014-05-08 | Panasonic Corporation | Semiconductor device |
| CN105390458A (en) * | 2011-12-21 | 2016-03-09 | 联发科技股份有限公司 | Semiconductor package |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7413102B2 (en) | 2020-03-17 | 2024-01-15 | キオクシア株式会社 | semiconductor equipment |
-
2000
- 2000-08-31 JP JP2000264099A patent/JP4347506B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140124941A1 (en) * | 2011-10-21 | 2014-05-08 | Panasonic Corporation | Semiconductor device |
| US9117770B2 (en) * | 2011-10-21 | 2015-08-25 | Panasonic Corporation | Semiconductor device |
| CN105390458A (en) * | 2011-12-21 | 2016-03-09 | 联发科技股份有限公司 | Semiconductor package |
| JP2013183002A (en) * | 2012-03-01 | 2013-09-12 | Ibiden Co Ltd | Electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4347506B2 (en) | 2009-10-21 |
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