JP2002083878A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To prevent a forward leakage current due to a parasitic bipolar and to effectively prevent a backward leakage current generated near a boundary between a semiconductor substrate and an element isolation region. To prevent. SOLUTION: A semiconductor substrate 1, an element isolation region 3 formed on the surface of the semiconductor substrate, a complementary MIS transistor formed on the semiconductor substrate, and a region on the semiconductor substrate surrounded by the element isolation region And a Schottky junction diode 8a forming the Schottky barrier diode is formed at a predetermined distance from the element isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a Schottky barrier diode capable of suppressing leakage current and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, in a semiconductor device having a complementary MIS transistor and a Schottky barrier diode on the same silicon substrate, an interface between the element isolation region and the silicon substrate has a problem.
The reverse leakage of the Schottky barrier diode significantly occurs.

On the other hand, near the boundary between a Schottky barrier junction formed on the surface of a silicon substrate and an element isolation region formed so as to surround the junction, a conductivity type different from the conductivity type of the surface of the silicon substrate is provided. A semiconductor device provided with a guard ring has been proposed (Japanese Patent Laid-Open No. 11-1633).
No. 73, etc.).

This semiconductor device is shown in FIG.
Thus, a p-type silicon substrate on which the element isolation region 3 is formed
An n-channel MIS transistor (not shown) is formed at 1.
Then, an n-well 2 is formed on the surface of the silicon substrate 1,
A Schottky barrier junction and a p-channel
MIS transistor (not shown)
You. The Schottky barrier junction is formed between n well 2 and n well.
Formed on the surface of the n-well 2 between the element isolation regions 3 in the
And a silicide film 22a made of titanium.
You. In addition, immediately below the silicide film 22a,
P near the remote region 3 ⁺Guard consisting of a metal-type impurity diffusion layer
A ring 23 is formed.

In the semiconductor device, an element isolation region 3 and an n-well 2 are formed on a silicon substrate 1 (FIG. 3A).
Thereafter, a p-type impurity is ion-implanted into a desired region on the silicon substrate 1 (FIG. 3B), whereby the p-channel M
Source / drain region of IS transistor (not shown)
At the same time, a guard ring 23 is formed using the resist pattern 21 having a desired opening as a mask. After that, the silicide films 22a, 22a
By forming the b and 22c, a Schottky barrier junction is formed on the guard ring 23 (FIG. 3C). Thereafter, the interlayer insulating film 11, the contact hole, the anode electrode 26 of the Schottky diode, and the cathode electrode 27 are formed. ,
A substrate contact electrode 12 and an electrode (not shown) of the MIS transistor are formed, respectively (FIG. 3D). In FIG. 3D, the N ⁺ buried diffusion layer is omitted for simplification of the description.

With such a configuration, a leak current caused by a defect generated at a boundary between the element isolation region 3 and the silicide film 22a is suppressed by the p-type guard ring 23 arranged to take in a surface defect portion. be able to.

However, when a current flows in the forward direction in this semiconductor device, as shown in FIG.
The p-type guard ring 23 constitutes an emitter, the n-well 2 constitutes a base, and the p-type silicon substrate 1 constitutes a parasitic bipolar transistor functioning as a collector. Therefore, a forward bias is applied between the emitter and the base, thereby forming a collector. A leak current to the silicon substrate 1 occurs.

That is, when the Schottky barrier diode having the above configuration is formed alone on the silicon substrate, the leakage current can be prevented. However, the n-well for forming the complementary MIS transistor has: When a guard ring type Schottky barrier diode is formed, the substrate leakage current in the forward direction of the above-mentioned parasitic bipolar transistor becomes significant.

Further, since the forward leakage current largely depends on the carrier concentration of the guard ring,
As described above, a commonly used ion implantation amount (1 × 10 ¹⁵ atoms / cm) for forming a source / drain region is used.
² ) cannot be prevented and becomes very large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a semiconductor device having a Schottky barrier diode capable of effectively preventing a leak current when any operating voltage is applied, and a method of manufacturing the same. About.

[0011]

According to the present invention, there is provided a semiconductor substrate, an element isolation region formed on the surface of the semiconductor substrate, and an element isolation region formed in a region on the semiconductor substrate surrounded by the element isolation region. Consisting of a Schottky barrier diode,
A semiconductor device is provided in which a Schottky junction forming the Schottky barrier diode is formed at a predetermined distance from the element isolation region.

According to the present invention, a semiconductor substrate, an element isolation region formed on the surface of the semiconductor substrate, a complementary MIS transistor formed on the semiconductor substrate, and the semiconductor device are surrounded by the element isolation region. There is provided a semiconductor device comprising a Schottky barrier diode formed in a region on a semiconductor substrate, wherein a Schottky junction forming the Schottky barrier diode is formed at a predetermined distance from the element isolation region.

Further, according to the present invention, a step of forming an element isolation region in a semiconductor substrate, a step of forming a mask for an offset region covering a boundary between the semiconductor substrate and the element isolation region and the vicinity thereof, Selectively forming a high-melting-point silicide film on the semiconductor substrate using an offset region mask.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention comprises a semiconductor substrate, an element isolation region formed on the surface of the semiconductor substrate, and a Schottky barrier formed in a region on the semiconductor substrate surrounded by the element isolation region. It is preferable that a complementary MIS transistor is mainly formed of a diode and that a complementary MIS transistor is formed on the same semiconductor substrate.

The semiconductor substrate in the present invention is not particularly limited as long as it is generally used for a semiconductor device. For example, an element semiconductor such as silicon or germanium, or a compound semiconductor such as GaAs, InGaAs, ZnSe or the like is used. No. Further, a substrate such as an SOI or SOS may be used. Among them, a silicon substrate is preferable. The semiconductor substrate is usually doped with a p-type or n-type impurity, and is preferably set to a predetermined resistance value.
Further, in addition to an element isolation region, a Schottky barrier diode, and a complementary MIS transistor, which will be described later, a semiconductor device such as a transistor and a capacitor, a circuit, a wiring layer, an insulating film, an impurity diffusion region (well), and the like are formed in combination. May be.

The element isolation region can be formed by various element isolation films such as a LOCOS film, a trench oxide film, and an STI film. In particular, it is preferable that the element isolation region is a LOCOS film or an STI film. The shape, thickness, size, and the like of the element isolation region can be appropriately adjusted in consideration of the operating voltage, performance, characteristics, and the like of the semiconductor device to be obtained.

The Schottky barrier diode is mainly composed of a Schottky junction between a semiconductor substrate and a high melting point silicide film formed on the surface of the semiconductor substrate, and electrodes respectively connected to the semiconductor substrate and the silicide film. Here, the semiconductor substrate may be a semiconductor substrate itself doped with a desired impurity, or a p-type or n-type impurity diffusion region formed on the surface of the semiconductor substrate, a so-called well. Among them, an n-type well is preferable. The impurity concentration of the semiconductor substrate (or well) on which the Schottky barrier diode is formed can be appropriately adjusted depending on the voltage applied to the Schottky barrier diode, the characteristics to be obtained, and the like.
About × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ . In addition,
It is preferable to lower the well concentration to increase the reverse breakdown voltage and to increase the well concentration to increase the forward current. Examples of the high melting point silicide film include a silicide film made of a high melting point metal such as titanium, tantalum, tungsten, and cobalt. Among them, a titanium silicide film and a cobalt silicide film are preferable. The thickness of the high melting point silicide is not particularly limited.
About 60 nm.

The high-melting-point silicide film is formed on the surface of the semiconductor substrate (or well) to provide a Schottky junction at its boundary. This Schottky junction must be at a certain distance from the element isolation region. is necessary. The certain distance here can be appropriately adjusted according to the size of the Schottky barrier diode, the thickness of the high melting point silicide film, the operating voltage of the Schottky barrier diode, and the like, but the shortest distance is 0.5 to 1. It is appropriate that they are separated by about 0 μm.

The electrode connected to the semiconductor substrate and the silicide film may be formed of any conductive material which is usually used as an electrode material, for example, aluminum, copper, platinum, etc. Can be formed of the above metal or alloy. The semiconductor substrate and the electrode may be connected via a contact region having a relatively high impurity concentration formed on the surface of the semiconductor substrate (or well), or may be formed on the surface of the semiconductor substrate (or well) or the contact region. May be connected via the high-melting-point silicide film. The contact region only needs to contain a p-type or n-type impurity concentration enough to realize an ohmic contact between the electrode and the semiconductor substrate. For example, the contact region is used to form a source / drain region constituting a MIS transistor described later. The contact region can be formed by utilizing the introduction of the impurity. As the high melting point silicide film, a film which can be formed simultaneously with the high melting point silicide film constituting the Schottky barrier diode can be used. For the electrodes, for example, an interlayer insulating film such as a BPSG film is formed by a technique known in the art, a contact window is opened, a contact portion is buried, an electrode material is deposited,
It can be formed by performing etching or the like.
This electrode can be formed, for example, by the same method as the formation of the electrodes of the MIS transistor described later.

In the semiconductor device of the present invention, it is preferable that the complementary MIS transistor is formed on the same substrate as the semiconductor substrate on which the Schottky barrier diode is formed. The MIS transistor usually has a gate insulating film,
Although mainly constituted by a gate electrode and a source / drain, a sidewall spacer, an LDD region, a DDD region, and the like may be further formed on a side wall of the gate electrode. Further, a silicide film may be formed on the surfaces of the gate electrode and the source / drain regions. Complementary MIS
The transistor is typically formed on a semiconductor substrate or on one or more p-type or n-type wells formed on the surface of the semiconductor substrate. In this case, the impurity concentration of the semiconductor substrate or the well is not particularly limited, and for example, the same impurity concentration as described above can be used.

According to the method of manufacturing a semiconductor device of the present invention,
First, an element isolation region is formed in a semiconductor substrate. The element isolation region can be formed by a known method, for example, various methods such as a LOCOS method, a trench element isolation method, and an STI method.

Next, an offset region mask covering the boundary between the semiconductor substrate and the element isolation region and the vicinity thereof is formed. The offset region mask may be formed of any material, shape, film thickness, or the like as long as it can cover the boundary between the semiconductor substrate and the element isolation region and the vicinity thereof. For example, the mask for the offset region is an insulating film such as a silicon oxide film, a silicon nitride film, or a laminated film thereof; a metal or alloy such as polysilicon, aluminum, and copper; a high melting point metal such as tantalum, titanium, and tungsten;
It can be formed of a conductive film such as a silicide with a high melting point metal and a poly sidewall spacer. In addition, a shape that can cover at least a boundary between the semiconductor substrate and the element isolation region and a region of about 0.5 μm or more from the boundary can be given. Further, the film thickness is not particularly limited, and may be, for example, about 200 to 400 nm.

The mask for the offset region is formed by forming a material film for forming the mask over the entire surface of the semiconductor substrate and etching the mask with a mask covering the boundary between the semiconductor substrate and the element isolation region and the vicinity thereof. For example, it may be formed using an insulating film or a conductive film used for forming an element, a circuit, or the like formed over the same substrate. Specifically, when a complementary MIS transistor is formed on the same semiconductor substrate, a mask for the offset region is formed by using a gate electrode material constituting the MIS transistor and using an appropriate mask when patterning the gate electrode. Can be formed. Further, a gate electrode and a side wall spacer constituting the complementary MIS transistor may be used. Further, when an insulating film for forming a sidewall spacer on the gate electrode of the complementary MIS transistor is anisotropically etched, an appropriate mask is used, and a mask for an offset region is formed using the insulating film. Is also good. Alternatively, the mask for the offset region may be formed using an insulating film or the like formed as a mask for preventing silicidation in the region where the diffusion resistance of the protection circuit of the complementary MIS transistor is formed.

Subsequently, a high melting point silicide film is selectively formed on the semiconductor substrate using the mask for the offset region. To selectively form a high melting point silicide film, first, a high melting point metal film is formed on the entire surface of a semiconductor substrate. The refractory metal film has a thickness of 20 to 20 by a sputtering method, a vacuum evaporation method, or the like.
It can be formed with a thickness of about 0 nm. The obtained substrate is
For example, heat treatment such as lamp annealing is performed in a temperature range of about 600 to 700 ° C. for about 10 seconds to react the high melting point metal film with the semiconductor substrate. Then, for example, H ₂ SO ₄ +
By removing the unreacted refractory metal film by wet etching using a mixed solution of H ₂ O _2, a refractory silicide film can be formed in a desired region. The high-melting-point silicide film only needs to be formed at least as a part of the Schottky barrier diode. For example, the high-melting-point silicide film may be formed on the surface of the gate electrode or the source / drain region of the MIS transistor, other elements, or the substrate surface.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. First Embodiment As shown in FIG. 1D, an n-channel MIS transistor (not shown) is formed on a p-type silicon substrate 1 on which an element isolation region 3 is formed, as shown in FIG.
Is formed, and a Schottky barrier diode is formed in an n-type well 2 formed on the surface of the silicon substrate 1.
P-channel MIS in different n-type wells (not shown)
A transistor (not shown) is formed.

The Schottky barrier diode is a silicide film formed between the well 2 and the isolation region 3 in the well 2 and in a surface region of the well 2 which is separated from the isolation region 3 by about 0.5 μm. 8a. The silicide film 8a functions as an anode, and a cathode is composed of an n-type impurity diffusion region 9 (well contact) formed in another region of the well 2 and a silicide film 8b formed on the surface thereof. The anode and the cathode are respectively provided with an anode electrode 16 and a cathode electrode 17.
Is connected.

Further, a p-type impurity diffusion region 10 (substrate contact) and a silicide film 8 c are formed on the surface of the silicon substrate 1, and these are connected to the substrate contact electrode 12.

As described above, by causing the Schottky junction of the Schottky barrier diode to be offset from the element isolation region by a predetermined distance, the generation of leakage current at the interface between the element isolation region and the silicon substrate can be prevented without forming a guard ring. Can be prevented.

The above semiconductor device can be formed by the following method.

First, as shown in FIG. 1A, for example, an STI (Shallow Trench)
Isolation) method, an n ^- type well 2 by phosphorus ion implantation using a resist pattern having a desired opening as a mask and diffusion in a thermal diffusion furnace.
To form The well 2 has, for example, a surface concentration of 1 × 10
^It is set so as to be ¹⁶ to 1 × 10 ¹⁷ atms / cm ³ .

Next, as shown in FIG. 1B, a gate insulating film 4 and a polysilicon film are formed on the entire surface of the silicon substrate 1, and these are patterned into a desired shape to form a gate electrode 5. A silicon oxide film is formed on the entire surface of the obtained polysilicon substrate 1 and anisotropically etched to form sidewall spacers 6 on the side walls of the gate electrode 5. At this time, the gate electrode 5 is formed so as to cover the interface between the element isolation region 3 and the polysilicon substrate 1, and finally, the offset width A between the sidewall spacer 6 and the gate electrode 5 is about 0.5 μm. Set so as to be as described above.

Subsequently, as shown in FIG. 1C, a region for forming the anode of the Schottky barrier diode is covered with a resist pattern (not shown),
At the same time as performing ion implantation for forming source / drain regions (not shown) of the S transistor, arsenic or phosphorus is ion-implanted into the surface of the n-well 2 and n-type is implanted in the region where the cathode of the Schottky barrier diode is formed. An impurity diffusion layer 9 is formed.

Next, both the region for forming the anode and the region for forming the cathode of the Schottky barrier diode are covered with a resist pattern (not shown), and the source / drain regions (not shown) of the p-channel MIS transistor are formed. For ion implantation. At that time, well 2
Are formed on the surface region of the polysilicon substrate 1 where
A p-type impurity diffusion layer 10 is simultaneously formed as a substrate contact. After that, a diffusion furnace or lamp annealing is performed to activate the impurities.

Next, a titanium film having a thickness of about 50 nm is deposited on the entire surface of the obtained polysilicon substrate 1 at 600 ° C.
Lamp annealing at about 700 ° C. is performed. The unreacted titanium film is selectively removed by etching the unreacted titanium film in a mixed solution of H ₂ SO ₄ + H ₂ O ₂ , lamp annealing at about 850 ° C. is performed again, and the gate electrode 5 and the polysilicon are removed. Silicide films 7, 8a, 8 on the surface of silicon substrate 1.
b and 8c are formed respectively.

Thereafter, as shown in FIG. 1D, an interlayer insulating film 11 made of BPSG is formed on the obtained polysilicon substrate 1, and a contact hole is formed in a desired region of the interlayer insulating film 11. Then, the contact hole is filled with a metal film and the metal film is patterned, so that the anode electrode 16, the cathode electrode 17, the substrate contact electrode 12, and the p-type and n-type MIS of the Schottky diode are formed.
An electrode (not shown) of the transistor is formed.

Embodiment 2 In a semiconductor device according to this embodiment, as shown in FIG. 2D, an element isolation region is formed by a LOCOS film 13, and an element is formed by an offset mask 14 made of a silicon oxide film. The semiconductor device of the first embodiment has substantially the same configuration except that it is formed so as to cover the interface between the isolation region and the silicon substrate.

The above semiconductor device can be formed by the following method.

[0038] First, as shown in FIG. 2 (a), p-type polysilicon substrate 1, the LOCOS film 13 is formed as an element isolation region by LOCOS, as in the first embodiment, n ^- -type Well 2 is formed.

Next, as in the first embodiment, a gate electrode (not shown) having a gate insulating film (not shown) and sidewall spacers is formed. At the time of etching for forming the side wall spacer, as shown in FIG. 2B, a silicon oxide film is left by using a resist pattern covering the vicinity of the interface between the polysilicon substrate 1 and the LOCOS film 13, and an offset mask is formed. 14 is formed. In this case, the offset width B is set so as to be finally about 0.5 μm or more.

Subsequently, as shown in FIG. 2C, the region for forming the anode of the Schottky diode is covered with a resist pattern (not shown), and the source / drain region (not shown) of the n-channel MIS transistor is formed. At the same time as the ion implantation for formation, arsenic or phosphorus is ion-implanted into the surface of the n-well 2 to form an n-type impurity diffusion layer 19 in a region where the cathode of the Schottky diode is formed.

Next, both the region for forming the anode and the region for forming the cathode of the Schottky diode are covered with a resist pattern (not shown), and the p-channel MI is formed.
Ion implantation for forming source / drain regions (not shown) of the S transistor is performed. At this time, as in the first embodiment, a p-type impurity diffusion layer 20 is simultaneously formed as a substrate contact, and heat treatment is performed.

Next, as in the first embodiment, a silicide film 18 is formed on the surface of the polysilicon substrate 1 by silicidation.
a, 18b and 18c are formed.

Thereafter, as shown in FIG. 2D, an interlayer insulating film 11, a contact hole, an anode electrode 16 of a Schottky diode, and a cathode are formed on the obtained polysilicon substrate 1 as in the first embodiment. The electrode 17, the substrate contact electrode 12, and the electrodes (not shown) of the p-type and n-type MIS transistors are formed.

Third Embodiment This embodiment is substantially the same as the first and second embodiments except that the semiconductor substrate, the well and the like are formed of the opposite conductivity type.

[0045]

According to the present invention, the Schottky junction forming the Schottky barrier diode is formed at a predetermined distance from the element isolation region. It is possible to suppress a leak current generated near the boundary between the semiconductor substrate and the element isolation region in the barrier diode.

In particular, in a semiconductor device in which a complementary MIS transistor and a Schottky barrier diode are formed on the same semiconductor substrate, it is possible to prevent a leakage current in a forward direction due to a parasitic bipolar. It is possible to effectively prevent the leakage current in the reverse direction that occurs near the boundary with the element isolation region.

Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to form a high-performance semiconductor device having a small leak current as described above by a simple method.

In particular, when the offset region mask is formed of an insulating film, a complementary type MI is further formed on the same semiconductor substrate.
Including a step of forming a gate electrode and a side wall spacer of the S transistor, a mask for an offset region,
When forming with a sidewall spacer material at the same time as the sidewall spacer, the method further includes a step of forming a gate electrode of a complementary MIS transistor on the same semiconductor substrate. In the case of using a gate electrode material, a complementary MIS transistor manufacturing process can be used, and a semiconductor device having desired characteristics can be manufactured more easily.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional manufacturing process diagram of a main part for describing one embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional manufacturing process diagram of a main part for describing another embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic cross-sectional manufacturing process diagram of a main part for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 polysilicon substrate (semiconductor substrate) 2 well 3 element isolation region 4 gate insulating film 5 gate electrode 6 sidewall spacer 7, 8a, 8b, 8c, 18a, 18b, 18c silicide film 9, 19 n-type impurity diffusion layer 10, Reference Signs List 20 p-type impurity diffusion layer 11 interlayer insulating film 12 substrate contact electrode 13 LOCOS film (element isolation region) 14 offset mask 16 anode electrode 17 cathode electrode A, B offset width

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB01 BB02 BB04 BB06 BB20 BB25 BB27 BB28 CC01 CC03 DD02 DD79 DD84 FF40 GG03 GG10 GG14 HH20 5F048 AC03 AC10 BA01 BB05 BB08 BB12 BC06 BF06 BG25 DA

Claims (8)

[Claims] 1. A semiconductor substrate comprising: a semiconductor substrate; an element isolation region formed on a surface of the semiconductor substrate; and a Schottky barrier diode formed in a region on the semiconductor substrate surrounded by the element isolation region. A semiconductor device, wherein a Schottky junction forming a key barrier diode is formed at a predetermined distance from the element isolation region. 2. A semiconductor substrate, a device isolation region formed on a surface of the semiconductor substrate, a complementary MIS transistor formed on the semiconductor substrate, and a semiconductor device surrounded by the device isolation region. And a Schottky junction forming the Schottky barrier diode is formed at a predetermined distance from the element isolation region. 3. A step of forming an element isolation region in a semiconductor substrate, a step of forming a mask for an offset region covering a boundary between the semiconductor substrate and the element isolation region and its vicinity, and using the mask for an offset region. Selectively forming a high-melting-point silicide film on the semiconductor substrate by using the above method. 4. The method according to claim 3, wherein the mask for the offset region is formed of an insulating film. 5. The method according to claim 1, further comprising the step of forming a complementary type MI on the same semiconductor substrate.
Including a step of forming a gate electrode and a side wall spacer of the S transistor, a mask for an offset region,
The method according to claim 4, wherein the side wall spacer is formed of a material for the side wall spacer simultaneously with the side wall spacer. 6. A complementary type MI on a same semiconductor substrate.
4. The method according to claim 3, further comprising the step of forming a gate electrode of the S transistor, wherein the mask for the offset region is formed of a gate electrode material simultaneously with the gate electrode. 7. The device isolation region is formed by a LOCOS method or an ST method.
The method according to any one of claims 3 to 5, which is formed by Method I. 8. The method according to claim 3, wherein the high melting point silicide is titanium silicide or cobalt silicide.