JP2002007314A - General-purpose bus connection device and multi-CPU computer using the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] Since it is possible to directly connect PCI buses that are independent of the type of each of the two motherboards, differences in processors can be absorbed, and
Build a multiprocessor system for distributed processing that also increases the communication speed. SOLUTION: Two motherboards 201 and 20 having a PCI bus and a bus slot independent of a machine type.
2 is connected to the PCI bus slot at both ends.
The connection is made by the PCI connection card 200 having the 00a and 200b. On the PCI connection card 200, a controller chip 200c for arbitrating the PCI bus is mounted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connection device and a multi-CPU computer using the same.

[0002]

2. Description of the Related Art There is known a technique for connecting computers to perform parallel processing. Heretofore, this parallel processing has been realized by a large computer such as a mainframe. Also, a technique of performing distributed processing for centralized processing is widely used.

On the other hand, with the development of electronic technology, the processing speed of personal computers (hereinafter simply referred to as PCs) has been dramatically improved in recent years. Distributed processing using a PC is generally realized by configuring a network.

The most common card for connecting a PC to a network is an Ethernet (registered trademark) card, and connection categories of 10Base2, 5, and T are known. At present, this extended category 10
0 Mbps / sec network cards are gradually becoming popular.

[0005]

SUMMARY OF THE INVENTION However, 100
Mbps / sec = 12.5 Mbytes / sec. In this case, even if the speed of the PC is increased, the speed of the essential communication means is hindered, and high-speed distributed processing cannot be performed.

The present invention has been made in view of such a problem, and directly connects general-purpose bus slots provided on a general-purpose bus shared by a general workstation and a personal computer to each other. BUS CONNECTION DEVICE AND MULTI-CPU USING THE BUS CONNECTION DEVICE FOR PERFORMING HIGH-SPEED DATA COMMUNICATION THAT WAS NOT AVAILABLE
It is intended to provide a computer.

[0007]

In order to solve this problem, for example, a bus connection device of the present invention has the following configuration. That is, a bus connection device for connecting two motherboards each having a general-purpose bus slot independent of a model, comprising a connector at both ends for connecting to the bus slots provided in the two motherboards, A controller chip for arbitrating between the buses while maintaining the bus width is mounted.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows the structure of a general motherboard (also called a main board).

In the figure, 100 is a motherboard, 10
1 is, for example, a processor P manufactured by Intel Corporation of the United States.
A socket on which entium (registered trademark) (Celeron or the like) is mounted, and 102 is a memory slot. 103
Is a chip generally called a north bridge, and 10
4 is a chip called a south bridge. The north bridge 103 and the south bridge 104 are generally called a chipset. 105 is AGP (Accelerated
Graphics Port) slot, on which a graphics card is mounted. The connection to the monitor is made via a connector provided on the graphic card. 10
Reference numeral 6 denotes a PCI (Peripheral Component Interconnect) slot. Since this slot is provided on the PCI bus, it may be simply called a PCI bus. The purpose is to connect a general-purpose expansion card such as a graphics card, SCSI card, network card, or the like. In addition, as for the form of the expansion slot, in addition to the one shown in the figure, an ISA bus (Industry standard accrchi
There are also a techture bus and a VL bus (VESA Local bus), which are based on the PCAT of IBM Corporation of the United States, and have a narrow transfer band and do not support plug and play. However, in recent years, the number of devices mounted is decreasing. 107 is a keyboard, mouse, serial, parallel, USB (Universa
l Serial Bus).

Although various circuits and interface connectors (for example, a connector for a floppy (registered trademark) disk and a connector for a hard disk) are mounted on the motherboard in addition to the above, they are not shown in the figure.

[0012] On the other hand, the PCI bus was originally developed for the purpose of eliminating model dependency. That is, the processor to be mounted (for example, Pentium series from Intel USA, SPAR from Sun Micro Corporation)
It does not depend on the C series, the PowerPC series by Motorola, the Alpha chip series of DEC, or other processors), and the pin arrangement of connectors and the timing and dimensions of signals are unified.

As the PCI bus, a 32-bit bus and a 64-bit bus and a 33-MHz clock and a 66-MHz clock are standardized.
Bus, and the clock supplied to the bus is 33 MHz.
z. That is, the 32-bit PCI bus is 32/8
× 33 ≒ 133 Mbytes / sec. This is 10 times faster than a 100 Mbps / s Ethernet card. In the case of a 64-bit, 66 MHz clock PCI bus,
532 Mbytes / sec.

The present inventors have found that personal computers and workstations having a motherboard equipped with a PCI bus have become widespread at present.
Focusing on the fact that the CI bus is a bus architecture that can absorb differences between processors, different motherboards are connected directly via a common bus called a PCI bus, and the transfer speed is much higher than the conventional transfer speed. Communication can now be performed at the transfer speed.

The details will be described below.

Cards that can be mounted on the PCI bus include a network card and a SCSI card. Many of them function as bus masters of the PCI bus without the intervention of a processor. For example, SCS
The I card has a function of transferring data to an address space when data is transferred from an external device (such as a hard disk, a CDROM, or an image scanner) connected to the I card.

A controller that functions as a bus master and an arbiter is also mounted on a card for connecting the PCIs of the present invention (hereinafter, referred to as a PCI connection card), and the PCI connection card is a SCSI when viewed from each processor. Just make it look like a card. The contents of such a controller will be described later, and a connection form of two motherboards will be described first below.

FIG. 2 shows the relationship between the two mother boards and the PCI connection card in the embodiment.

FIG. 1A shows a stage before connection of the PCI connection card. In the figure, reference numeral 200 denotes a PCI connection card of the embodiment, and reference numerals 201 and 202 denote mother boards, respectively. 201a and 202a are PCI bus slots mounted on each motherboard.

At the lower ends of both ends of the PCI connection card 200,
PCI slots 201a provided on each motherboard,
Connection terminal 2 that is electrically connected by being inserted into 202a
00a and 200b are provided. In addition, the PCI connection card 200 includes a PCI card of each motherboard.
A controller chip 200c that controls bus arbitration and transfer is mounted. Of course, other various electronic components are mounted.

FIG. 2B shows the PCI connection card 20.
0 shows an example in which 0 is actually mounted.

Now, the controller chip 200c mounted on the PCI connection card 200 performs bidirectional data transfer (32-bit parallel transfer) on the PCI bus and functions as a bus master as described above. Will be needed.

Although it is possible to produce such a controller chip 200c utilizing an ASIC or the like, a chip manufactured by Intel Corporation of the United States (chip name: 215)
According to the specification of 54), data can be transferred from an internal PCI bus to an external device and from an external device to an internal PCI bus, and can function as a bus master and an arbiter.

Depending on the setting of the chip, a function of mapping an external address space to an internal address space can be provided. If the external address space mentioned here is set to the address space of another motherboard, the address space on the other motherboard can be accessed as if it were its own address space. On the other hand, if the same setting is made for other motherboards, a part of each address space can be mapped to the other address space.

FIG. 3 shows an example in which certain portions of the main memory mounted on the two motherboards A and B are shared with each other.

The points to be noted here are motherboards A and B.
The point is that the OS on which the processor (actually, the processor is determined by the type of the motherboard) mounted on each does not need to be the same.

In particular, the processing of 3D images, for example, the processing of recognizing the shape of 3D objects requires extremely sophisticated and complicated processing. Therefore, this processing is performed, for example, by using a SPARC processor (Sun Microsystems, USA) which is excellent in processing capacity. A processor (a developed RISC processor) is executed by a machine (UNIX (an OS developed by AT & T in the United States) which generally operates as an OS), and a user interface and the like are provided by a processor provided by Intel Corporation of the United States, which is becoming widespread as a personal computer. Pentium series processor, hereinafter simply based on Pentium) and provided by Microsoft, USA, MS-Window
ws (hereinafter simply Windows).

In order to realize the above processing, two parallel machines (two motherboards) have respective O
After the start of the S, at the stage when the OS is started or at the stage when the BIOS is started before the OS is started, each is automatically executed by executing a program for performing setting for operating the controller chip in the execution state. The shared state can be set as described above. Of course, since this setting program is executed by each processor, it is necessary to write each setting program in a code unique to the processor.

The above-mentioned setting is to set which internal address space is to be mapped to which address space provided by the external machine, and the same setting is made in the external machine.

From then on, it is only necessary to run an application for sharing work on each machine.

For the sake of simplicity, one machine is a machine using Pentium as a processor and Windows as a used OS, and the other is a SPARC processor and a used OS.
Is a machine using UNIX. And the above P
Connected with CI connection card and configured as parallel machine,
The flow of processing when a program related to the shape recognition processing of a three-dimensional image is executed will be described with reference to the flowchart of FIG.

In the following, Pentium + Window
s machine is machine A, SPARC (registered trademark) + UN
The IX machine will be described as a machine B. Before executing the program according to the illustrated flowchart,
It is assumed that the settings for accessing each external machine have been completed.

First, the operation processing procedure of the machine A First, when the program is started, in step S1, the PCI
Get the memory mapping information set for the connection card. Next, the process proceeds to step S2, in which the display device displays 3D.
Display the image application user interface. When a user instructs input of image data, the user inputs the data. The input source is not particularly limited, and may be, for example, a video camera, a video tape, an output of a broadcast television image, or a download from a network.

Then, the process proceeds to a step S4, wherein the input image data is written in the address space mapped to the machine B. If the area size of the address space is smaller than the size of the image data, the image is divided and written into the area size, and the process is repeated until it is determined in step S5 that the writing of the input image has been completed.

When the writing is completed, the flow advances to step S6 to wait until it is determined that the recognition result has been transferred from the machine B. This determination may be made by an interrupt from the PCI connection card or by examining the actual memory of the machine B mapped to its own memory space. If it is determined that the recognition has been completed, the process proceeds to step S7, and an image of the recognition result is displayed based on the data.

Operation processing procedure of machine B First, when the program is started, in step S11 the PC
Acquire the memory mapping information set for the I-connection card. Then, the process proceeds to step S12, in which the area where the address space of the machine A is mapped in the address space of the machine B itself is examined to determine whether there is data to be processed. If it is determined that there is, step S
In step 13, the data is sequentially read, and the shape recognition processing of the three-dimensional image is performed. When the shape recognizing process is completed, the address is written into the address space of the machine B assigned to the machine A, and the process returns to the step S12.

As described above, according to the present embodiment, it is possible to directly connect the PCI buses of the two machines and to secure a speed at which the transfer bandwidth of the PCI bus is substantially used up. Therefore, even if the speed of each computer is high, it is possible to configure a machine which is much faster than the conventional distributed processing in which the communication speed between them is a bottleneck.

Further, in the embodiment, an example is shown in which two motherboards (a controller chip may be mounted on one of the cards) are connected by a connection card in a U-shape, but FIG. As shown in (2), the two PCI cards may be connected by a flexible cable (a transfer rate is high, so it is desirable that the length be a certain length or less). Also, it is not a general-purpose motherboard,
As shown in FIG. 5 (b), a controller chip for connecting the PCI bus as described above is mounted on the motherboard, and a female connector and a male connector of the PCI bus are provided on each side edge. Chain).

In particular, when a PCI card as shown in FIG. 5A is used, two motherboards can be arranged in parallel as shown in FIG. 6, and a standard housing is sufficient.

In the above-described embodiment, an example is shown in which a chip "21554" manufactured by Intel Corporation of the United States is used and its memory map function is utilized. However, the PCI buses of the two motherboards are connected to each other by the bus width. Any other chip may be used, as long as it can be connected as it is and each motherboard can perform data transfer. In particular, when manufacturing a controller chip capable of simply transmitting and receiving data, a P-chip mounted with the controller chip is required.
The CI connection card may be recognized as an ultra-high-speed network card when viewed from the processor, and a driver for this may be prepared.

In general, a motherboard has a plurality of PCI bus slots as shown in FIG. 1, so if a plurality of PCI connection cards of the embodiment are prepared,
A 1: N connection (star connection) is also possible.

[0042]

As described above, according to the present invention, 2
P independent of the model that each motherboard has
Since the CI buses can be directly connected to each other, it is possible to construct a multiprocessor system for distributed processing that can absorb differences in processors and increase the communication speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general structure of a motherboard.

FIG. 2 is a diagram illustrating a method of using a PCI connection card used in the embodiment.

FIG. 3 is a diagram showing a relationship between address spaces in two motherboard machines according to the embodiment.

FIG. 4 is a flowchart illustrating an example of an application when a multi-motherboard is used.

FIG. 5 is a diagram showing another example of connection of a motherboard.

FIG. 6 is a diagram illustrating another connection example of the motherboard.

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Kiichiro Shibuya 5-45-7 Masago, Mihama-ku, Chiba-shi, Chiba F-term (reference) 5B061 BB03 FF01 GG15 PP05 QQ02

Claims (4)

[Claims] 1. A bus connection device for connecting two motherboards each having a general-purpose bus slot independent of a CPU model, comprising a connector at each end for connecting to a bus slot provided in each of the two motherboards. A bus connection device comprising a controller chip that performs arbitration between buses while maintaining the bus width of each motherboard. 2. The bus connection device according to claim 1, wherein said bus slot is a PCI bus slot. 3. A multi-CPU computer comprising at least two independent motherboards each having a general-purpose bus slot independent of a machine type, wherein the bus slots of each of the two motherboards maintain their respective bus widths. A multi-CPU computer wherein the buses are connected via a controller chip that arbitrates between the buses. 4. The multi-CPU computer according to claim 3, wherein said bus slot is a PCI bus slot.