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JP2002010645A - Voltage-control method and unit - Google Patents

Voltage-control method and unit

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Publication number
JP2002010645A
JP2002010645A JP2000186780A JP2000186780A JP2002010645A JP 2002010645 A JP2002010645 A JP 2002010645A JP 2000186780 A JP2000186780 A JP 2000186780A JP 2000186780 A JP2000186780 A JP 2000186780A JP 2002010645 A JP2002010645 A JP 2002010645A
Authority
JP
Japan
Prior art keywords
voltage
signal
chopper circuit
primary winding
pwm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000186780A
Other languages
Japanese (ja)
Other versions
JP4647752B2 (en
Inventor
Koji Konishi
功次 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kawamura Electric Inc
Original Assignee
Kawamura Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawamura Electric Inc filed Critical Kawamura Electric Inc
Priority to JP2000186780A priority Critical patent/JP4647752B2/en
Publication of JP2002010645A publication Critical patent/JP2002010645A/en
Application granted granted Critical
Publication of JP4647752B2 publication Critical patent/JP4647752B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a voltage-control unit having no occurrence of a distortion even in the neighborhood of a zero-cross point of an output voltage and no fluctuation of a voltage waveform even if power fails. SOLUTION: A switching signal of a chopper circuit 4 that controls an applied voltage applied to a primary winding 2 of a transformer 1 is generated by combining a PWM signal generated at a control unit 11 and a synchronized signal generated at a synchronized-signal generating circuit 12. The synchronized signal is the one that repeats 'H' and 'L' at every half cycle of an input- voltage waveform, and always indicates 'L' in the neighborhood of 400 μs of the zero-cross point of the input voltage. The chopper circuit 4 is chopping- controlled by the PWM signal only when the synchronized signal indicates 'L'.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、PWM制御により
変圧器の1次側電圧を変化させて、2次側出力電圧を制
御する電圧制御方法及び電圧制御装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage control method and a voltage control device for controlling a secondary output voltage by changing a primary voltage of a transformer by PWM control.

【0002】[0002]

【従来の技術】単相3線電路において、PWM制御(パ
ルス幅変調制御)により電圧を制御する電圧制御装置の
回路図を図3に示す。図3では、例えば200Vの入力
電圧を変圧器により最大20V降圧して180Vを出力
する電圧制御装置を示し、変圧器20の1次巻線21を
電源側入力端子23の両電圧線X−Y間に接続し、2つ
の巻線から成る2次巻線22を夫々入力端子23の電圧
線X,Yと出力端子24の電圧線x,yに直列に接続さ
れている。そして、入力端子23の中性線Nは出力端子
24の中性線nに直接接続されている。
2. Description of the Related Art FIG. 3 is a circuit diagram of a voltage controller for controlling a voltage in a single-phase three-wire circuit by PWM control (pulse width modulation control). FIG. 3 shows a voltage control device that steps down the input voltage of 200 V by a maximum of 20 V by a transformer and outputs 180 V, and connects the primary winding 21 of the transformer 20 to both voltage lines XY of the power supply side input terminal 23. A secondary winding 22 composed of two windings is connected in series to voltage lines X and Y of an input terminal 23 and voltage lines x and y of an output terminal 24, respectively. The neutral line N of the input terminal 23 is directly connected to the neutral line n of the output terminal 24.

【0003】1次巻線21には入力電圧を4個のFET
を組み合わせたPWMチョッパ回路25によりPWM制
御した電圧を印加し、このPWM制御は出力端子24の
電圧が出力設定値となるように演算された値で行われ、
チョッパ回路25によりチョッピングされた電圧波形
は、出力フィルタ回路26により正弦波電圧に成形され
一次巻線に印加されている。図4は入力電圧波形と4個
のFETの動作タイムチャートを示し、パルスデューテ
ィー比を50%として入力電圧を10V降圧して出力す
る場合を示している。
The primary winding 21 has an input voltage of four FETs.
Is applied by a PWM chopper circuit 25 in which the voltage of the output terminal 24 is set to an output set value.
The voltage waveform chopped by the chopper circuit 25 is shaped into a sine wave voltage by the output filter circuit 26 and applied to the primary winding. FIG. 4 shows an input voltage waveform and an operation time chart of the four FETs, and shows a case where the pulse duty ratio is 50% and the input voltage is stepped down by 10 V and output.

【0004】[0004]

【発明が解決しようとする課題】ところが、上記構成の
場合、変圧器20の1次巻線印加電圧が、FETのスイ
ッチング遅れやスイッチングノイズ等により図4のタイ
ムチャート通りにスイッチングされず、交流電圧の0ク
ロス付近で歪みが生じ、その影響で出力端の電圧も0ク
ロス付近で歪みが生じていた。また、運転中に瞬間的な
停電があると、両電圧線間の電圧低下時間と制御回路の
電圧低下時間との間に差が生じ、また復電時も両電圧線
間の電圧が定常値まで上昇する時間と制御回路の電圧が
定常値まで上昇する時間には差があるため、各過渡期に
おいてFETのスイッチング動作が不確定となってい
た。そのため、変圧器の1次巻線印加電圧は不定値とな
り、その結果出力電圧が大きく変動していた。
However, in the case of the above configuration, the voltage applied to the primary winding of the transformer 20 is not switched according to the time chart of FIG. At the zero cross, and the voltage at the output terminal was also distorted near the zero cross. Also, if there is a momentary power failure during operation, there will be a difference between the voltage drop time between the two voltage lines and the voltage drop time of the control circuit. Since there is a difference between the time when the voltage of the control circuit rises and the time when the voltage of the control circuit rises to the steady value, the switching operation of the FET is uncertain in each transition period. As a result, the voltage applied to the primary winding of the transformer becomes an indefinite value, and as a result, the output voltage fluctuates greatly.

【0005】そこで、本発明は上記問題点に鑑み、出力
電圧が0クロス付近でも歪みが発生することが無く、ま
た停電が発生しても電圧波形が乱れることのない電圧制
御方法及び電圧制御装置を提供することを課題とする。
Accordingly, in view of the above problems, the present invention provides a voltage control method and a voltage control device which do not cause distortion even when the output voltage is near zero crossing and which do not disturb the voltage waveform even if a power failure occurs. The task is to provide

【0006】[0006]

【課題を解決するための手段】上記課題を解決するた
め、請求項1の発明は、変圧器の1次巻線をチョッパ回
路を介在させて単相3線電路の両電圧線間に接続すると
共に、該変圧器の2次巻線を前記両電圧線と負荷の間に
直列接続し、チョッパ回路のPWM制御によりチョッピ
ングした電圧を前記1次巻線に印加して負荷印加電圧を
制御する電圧制御方法であって、入力電圧の半周期毎に
「H」,「L」の信号を繰り返して発生する同期信号発
生ステップと、入力電圧信号の0クロス点を中心に前後
数百μSの間を常に「L」となるよう前記同期信号を加
工して出力する同期信号加工ステップとを有し、該加工
した同期信号が「L」の場合にPWM信号を出力してチ
ョッパ制御することを特徴とする電圧制御方法。
According to a first aspect of the present invention, a primary winding of a transformer is connected between two voltage lines of a single-phase three-wire circuit via a chopper circuit. A voltage for controlling a load applied voltage by connecting a secondary winding of the transformer in series between the voltage lines and the load and applying a chopped voltage to the primary winding by PWM control of a chopper circuit. A control method, comprising: a synchronizing signal generating step of repeatedly generating “H” and “L” signals every half cycle of an input voltage; A synchronization signal processing step of processing and outputting the synchronization signal so as to always be "L", and outputting a PWM signal and performing chopper control when the processed synchronization signal is "L". Voltage control method.

【0007】請求項2の発明は、請求項1の発明におい
て、同期信号が電源電圧の0クロス点を中心に前後数百
μS間に「H」,「L」の変化がなかったとき、或いは
0クロス点を中心に前後数百μS間以外で「H」,
「L」の変化があったときに停電と判断し、入力電圧を
遮断するステップを有することを特徴とする。
A second aspect of the present invention is based on the first aspect, wherein the synchronizing signal does not change "H" and "L" between several hundreds μS before and after the zero-cross point of the power supply voltage, or “H”, except for a few hundred μS before and after the zero cross point,
It is characterized by having a step of judging a power failure when there is a change of “L” and cutting off the input voltage.

【0008】請求項3の発明は、変圧器の1次巻線をチ
ョッパ回路を介在させて単相3線電路の両電圧線間に接
続すると共に、該変圧器の2次巻線を前記両電圧線と負
荷の間に直列接続し、チョッパ回路のPWM制御により
チョッピングした電圧を前記1次巻線に印加して負荷印
加電圧を制御する電圧制御装置であって、PWM信号発
生手段と、入力電圧の周期に同期した信号を発生する同
期信号発生手段と、前記PWM信号と該同期信号発生手
段からの同期信号を組み合わせて前記チョッパ回路のス
イッチング信号を出力する制御手段とを有することを特
徴とする。
According to a third aspect of the present invention, a primary winding of a transformer is connected between both voltage lines of a single-phase three-wire circuit via a chopper circuit, and a secondary winding of the transformer is connected to the two windings. A voltage control device which is connected in series between a voltage line and a load and controls a load applied voltage by applying a chopped voltage to the primary winding by PWM control of a chopper circuit, comprising: a PWM signal generating means; A synchronizing signal generating means for generating a signal synchronized with a voltage cycle; and a control means for outputting a switching signal of the chopper circuit by combining the PWM signal and a synchronizing signal from the synchronizing signal generating means. I do.

【0009】請求項4の発明は、請求項3の発明におい
て、同期信号発生手段の発生信号が、電源電圧の半周期
毎に「H」,「L」を繰り返し、制御手段が該同期信号
を受けて、電源電圧の0クロス点を中心に前後数百μS
の間は常に「L」信号となるよう加工し、該加工信号と
PWM信号を組み合わせてスイッチング信号を出力する
ことを特徴とする。
According to a fourth aspect of the present invention, in the third aspect of the present invention, the signal generated by the synchronizing signal generating means repeats "H" and "L" every half cycle of the power supply voltage, and the control means converts the synchronizing signal to Several hundred μS around the zero cross point of the power supply voltage
During this period, the signal is always processed to be an "L" signal, and the processed signal and the PWM signal are combined to output a switching signal.

【0010】請求項5の発明は、請求項4の発明におい
て、チョッパ回路の電源側電圧線に第1開閉手段を、更
に1次巻線の両端間に第2開閉手段を設けると共に、停
電検出手段を設け、停電を検出した際に第1開閉手段を
開動作させると共に第2開閉手段を閉動作させることを
特徴とする。
According to a fifth aspect of the present invention, in the fourth aspect of the present invention, a first switching means is provided on a power supply side voltage line of the chopper circuit, and a second switching means is provided between both ends of the primary winding. Means for opening the first opening / closing means and closing the second opening / closing means when a power failure is detected.

【0011】請求項6の発明は、請求項5の発明におい
て、停電検出手段は、同期信号発生手段からの同期信号
が電源電圧の0クロス点を中心に前後数百μS間に
「H」,「L」の変化がなかったとき、或いは0クロス
点を中心に前後数百μS間以外で「H」,「L」の変化
があったときに停電と判断することを特徴とする。尚、
数百μSとは100μS〜800μSとする。
According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the power failure detecting means is configured such that the synchronizing signal from the synchronizing signal generating means outputs "H" between several hundreds μS before and after the power supply voltage at the zero cross point. When there is no change in “L”, or when there is a change in “H” or “L” other than a few hundred μS before and after the zero cross point, it is determined that a power failure has occurred. still,
Several hundred μS means 100 μS to 800 μS.

【0012】[0012]

【発明の実施の形態】以下、本発明を具体化した実施の
形態を、図面に基づいて詳細に説明する。図1は本発明
に係る電圧制御装置の1例を示す回路図であり、1は1
個の1次巻線2と2個の2次巻線3を有する変圧器、4
は第1〜第4の4個のFETを有するチョッパ回路、5
aは入力フィルタ回路、5bは出力フィルタ回路であ
り、単相3線電路に接続する入力端子8の両電圧線X,
Yがチョッパ回路4及びフィルタ回路5a,5bを介し
て変圧器1の1次巻線2に接続され、2個の巻線から成
る2次巻線3は夫々入力端子8の電源電圧線X,Yから
負荷に接続する出力端子9の電圧線x,yに直列に接続
され、入力端子8の中性線Nは出力端子9の中性線nに
直接接続されている。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a voltage control device according to the present invention, where 1 is 1
Transformer having two primary windings 2 and two secondary windings 3,
Represents a chopper circuit having first to fourth four FETs;
a is an input filter circuit, 5b is an output filter circuit, and both voltage lines X and X of the input terminal 8 connected to the single-phase three-wire circuit are provided.
Y is connected to the primary winding 2 of the transformer 1 via the chopper circuit 4 and the filter circuits 5a and 5b, and the secondary winding 3 composed of two windings is connected to the power supply voltage lines X and X of the input terminal 8, respectively. The neutral line N of the input terminal 8 is directly connected to the neutral line n of the output terminal 9, which is connected in series to the voltage lines x, y of the output terminal 9 connected from Y to the load.

【0013】また、電源側電圧線Xに第1開閉器6a
が、1次巻線2に並列に第2開閉器6bが夫々設けら
れ、双方は1つの電磁開閉器のa接点とb接点で形成さ
れている。そして、これら開閉器6a,6b及びチョッ
パ回路4の各FETは制御部11により制御されてい
る。制御部11には入力端子8からの交流電圧信号を受
けて交流電源の0クロス点と同期したパルス信号を発生
する同期信号発生回路12が接続されると共に出力端子
9の電圧値を検出して制御部11に電圧値信号を出力す
る電圧読込回路13が接続されている。
A first switch 6a is connected to the power supply side voltage line X.
However, the second switches 6b are respectively provided in parallel with the primary winding 2, and both are formed by the a contact and the b contact of one electromagnetic switch. The FETs of the switches 6a and 6b and the chopper circuit 4 are controlled by the control unit 11. The control unit 11 is connected to a synchronizing signal generating circuit 12 which receives an AC voltage signal from the input terminal 8 and generates a pulse signal synchronized with the zero cross point of the AC power supply, and detects a voltage value of the output terminal 9. A voltage reading circuit 13 that outputs a voltage value signal is connected to the control unit 11.

【0014】制御部11はマイクロコンピュータを内蔵
し、各FETを制御する第1〜第4の4個の出力部11
a〜11dを有し、この4個の出力部11a〜11dは
夫々4個のOR回路14に接続され、OR回路14の出
力をチョッパ回路4のFET制御信号としている。ま
た、第1開閉器6a,第2開閉器6bを制御する1つの
出力ポート11eを有し、出力ポート11eは開閉器制
御回路16に接続され、第1,第2開閉器を同時に開閉
制御している。
The control unit 11 includes a microcomputer and controls first to fourth four output units 11 for controlling each FET.
The four output units 11a to 11d are respectively connected to four OR circuits 14, and the output of the OR circuit 14 is used as an FET control signal of the chopper circuit 4. It also has one output port 11e for controlling the first switch 6a and the second switch 6b, and the output port 11e is connected to the switch control circuit 16 to control the opening and closing of the first and second switches simultaneously. ing.

【0015】この制御部11の制御動作を図2のタイム
チャートを基に説明する。まず、正常動作時は同期信号
発生回路12が入力端子間の交流電源と同期したパルス
信号を発生し、制御部11の入力ポートへ入力する。制
御部11では、そのパルス信号に同期させながら内部カ
ウンタをスタートする。尚、このカウンタはパルス信号
の立ち上がりを検知する度に0クリアされる。また、出
力電圧設定部15で予め設定された設定値と、電圧読込
回路13から入力される出力電圧の読込値とを比較演算
し、その結果に準じたパルス幅のPWMパルス信号の正
アクティブ信号を出力部11aから出力し、負アクティ
ブ信号を出力部11bから出力する。
The control operation of the control unit 11 will be described with reference to the time chart of FIG. First, during normal operation, the synchronization signal generation circuit 12 generates a pulse signal synchronized with the AC power supply between the input terminals, and inputs the pulse signal to the input port of the control unit 11. The control unit 11 starts the internal counter while synchronizing with the pulse signal. This counter is cleared to 0 each time a rising edge of the pulse signal is detected. Further, a comparison operation is performed between a preset value set by the output voltage setting unit 15 and a read value of the output voltage input from the voltage reading circuit 13, and a positive active signal of a PWM pulse signal having a pulse width according to the result is calculated. Is output from the output unit 11a, and a negative active signal is output from the output unit 11b.

【0016】そして、内部カウンタの値に特定のs値、
例えばs=400μSを設定して次の動作をさせる。ま
ず、内部カウンタの値がsになったら、第4の出力部1
1dの出力を「H」にする。次に、内部カウンタの値が
「半周期−s」となったら、第4の出力部11dを
「L」にし、「半周期+s」となったら、第3の出力部
11cを「H」にし、「1周期−s」となったら、第3
の出力部11cを「L」にする。このように第3の出力
部11cの出力をパルス信号の加工信号とし、第4の出
力部11dの出力を第3の出力部11cの信号を反転さ
せて出力する。そして、これら第1〜第4の出力部の信
号を4個のOR回路14を図示するように介在させるこ
とで、図2のA,B,C,Dに示すように、パルス信号
が入力交流電圧信号に同期した「L」信号を出力してい
る間のみPWM信号を出力させて、この信号によりチョ
ッパ回路4を制御している。
A specific s value is added to the value of the internal counter,
For example, the following operation is performed by setting s = 400 μS. First, when the value of the internal counter becomes s, the fourth output unit 1
The output of 1d is set to "H". Next, when the value of the internal counter becomes "half cycle-s", the fourth output unit 11d is set to "L", and when it becomes "half cycle + s", the third output unit 11c is set to "H". , "1 cycle-s", the third
Is set to "L". Thus, the output of the third output unit 11c is used as a pulse signal processing signal, and the output of the fourth output unit 11d is output by inverting the signal of the third output unit 11c. Then, by interposing the signals of the first to fourth output units with the four OR circuits 14 as shown in the figure, the pulse signal is converted into the input AC as shown in A, B, C, and D of FIG. The PWM signal is output only while the "L" signal synchronized with the voltage signal is being output, and the chopper circuit 4 is controlled by this signal.

【0017】次に停電が発生した場合の動作を説明す
る。まず、停電の判断は次の3つの条件でおこなう。 1.内部カウンタの値が「半周器−s」から「半周器+
s」の間に交流電源と同期したパルス信号が「H」から
「L」に変化しなかった時。 2.内部カウンタの値が「1周期−s」から「1周期+
s」の間に交流電源と同期したパルス信号が「L」から
「H」に変化しなかった時。 3.内部カウンタの値が「半周器−s」から「半周器+
s」の期間外または「1周期−s」から「1周期+s」
の期間外に交流電源と同期したパルス信号が「H」から
「L」または「L」から「H」に変化した時。
Next, the operation when a power failure occurs will be described. First, a power outage is determined under the following three conditions. 1. When the value of the internal counter changes from “half-circle-s” to “half-circle +
When the pulse signal synchronized with the AC power supply does not change from “H” to “L” during “s”. 2. When the value of the internal counter changes from “1 cycle−s” to “1 cycle +
When the pulse signal synchronized with the AC power supply does not change from “L” to “H” during “s”. 3. When the value of the internal counter changes from “half-circle-s” to “half-circle +
out of the period of "s" or "1 cycle-s" to "1 cycle + s"
When the pulse signal synchronized with the AC power supply changes from “H” to “L” or from “L” to “H” outside the period.

【0018】以上の場合を停電と判断して、第2の出力
部11bを「H」、第1の出力部11a,第3の出力部
11c、第4の出力部11dを「L」とし、出力ポート
11eから第1及び第2開閉器6a,6bの動作信号を
出力して、第1開閉器6aを開動作、第2開閉器6bを
閉動作させて、回路を入力電圧から遮断する。こうする
ことで、変圧器1の1次巻線2への供給電圧が0Vとな
る。
In the above case, it is determined that a power failure has occurred, and the second output unit 11b is set to "H", the first output unit 11a, the third output unit 11c, and the fourth output unit 11d are set to "L". The operation signals of the first and second switches 6a and 6b are output from the output port 11e to open the first switch 6a and close the second switch 6b to cut off the circuit from the input voltage. By doing so, the supply voltage to the primary winding 2 of the transformer 1 becomes 0V.

【0019】このように、入力電圧の0クロス前後で安
定させてPWM信号を出力させることで、出力電圧が0
クロス付近でも歪むことがなくなる。また、停電による
電圧低下の際、出力端の電圧は入力端側と同様に低下
し、低下途中でFETのミストリガによる電圧波形の乱
れが生ずることがないし、停電後の復帰時も入力端の電
圧が安定してから制御がスタートすることができ、FE
Tのミストリガによる出力端電圧波形の乱れが生じな
い。尚、上記s値は400μSでなくとも良く、300
μSから600μSの間であれば良好に作用させること
ができるが、50Hzの場合は400μs、60Hzで
あれば330μsが好適である。また、この実施の形態
では制御部がPWM信号発生手段及び停電検出手段を兼
ねているが個別に構成しても良い。
As described above, by stably outputting the PWM signal before and after the zero cross of the input voltage, the output voltage becomes zero.
There is no distortion near the cross. In addition, when the voltage drops due to a power failure, the voltage at the output terminal drops in the same way as the input terminal side, and the voltage waveform does not disturb due to a mistrigger of the FET during the fall. Control can start after the FE has stabilized
The output terminal voltage waveform is not disturbed by the T mistrigger. Note that the s value does not have to be 400 μS,
The function can be satisfactorily performed between μS and 600 μS, but 400 μs is preferable at 50 Hz, and 330 μs is preferable at 60 Hz. In this embodiment, the control unit also serves as a PWM signal generation unit and a power failure detection unit, but may be configured separately.

【0020】[0020]

【発明の効果】以上詳述したように、請求項1,3の発
明によれば、PWM信号と電源電圧の周期に同期させた
信号を組み合わせてチョッパ回路を制御するので、0ク
ロス付近での負荷印加電圧の歪みを無くすことが可能で
ある。
As described in detail above, according to the first and third aspects of the present invention, the chopper circuit is controlled by combining the PWM signal and the signal synchronized with the cycle of the power supply voltage. It is possible to eliminate the distortion of the load applied voltage.

【0021】請求項2の発明によれば、請求項1の効果
に加えて停電時入力電圧を遮断するので、出力端の電圧
は入力端側と同様に低下し、低下途中でミストリガによ
る電圧波形の乱れが生じない。
According to the second aspect of the present invention, in addition to the effect of the first aspect, the input voltage at the time of a power failure is cut off, so that the voltage at the output terminal decreases in the same manner as the input terminal side, and a voltage waveform caused by a mistrigger during the decrease. There is no disturbance.

【0022】請求項4の発明によれば、請求項3の効果
に加えて電源電圧の周期に同期させた同期信号が「L」
の時のみPWM信号を出力させることで、0クロス付近
での波形歪みを無くせる。
According to the invention of claim 4, in addition to the effect of claim 3, the synchronization signal synchronized with the cycle of the power supply voltage is "L".
By outputting the PWM signal only in the case of, the waveform distortion near the zero cross can be eliminated.

【0023】請求項5の発明によれば、請求項4の効果
に加えて停電時入力電圧を遮断するので、出力端の電圧
は入力端側と同様に低下し、低下途中でミストリガによ
る電圧波形の乱れが生じない。また、停電後の復帰時も
入力端の電圧が安定してから制御をスタートすることが
可能なため、チョッパ回路のミストリガによる出力端電
圧波形の乱れが生じない。従って、停電が発生しても電
圧波形が乱れることがない。
According to the fifth aspect of the present invention, in addition to the effect of the fourth aspect, the input voltage at the time of a power failure is cut off, so that the voltage at the output terminal decreases in the same manner as the input terminal side, and the voltage waveform caused by a mistrigger during the decrease. There is no disturbance. Also, at the time of recovery after a power failure, control can be started after the voltage of the input terminal is stabilized, so that the output terminal voltage waveform is not disturbed by a mistrigger of the chopper circuit. Therefore, even if a power failure occurs, the voltage waveform is not disturbed.

【0024】請求項6の発明によれば、請求項5の効果
に加えて瞬時停電を確実に検出することができる。
According to the invention of claim 6, in addition to the effect of claim 5, an instantaneous power failure can be reliably detected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態の1例を示す電圧制御装置
の回路ブロック図である。
FIG. 1 is a circuit block diagram of a voltage control device showing an example of an embodiment of the present invention.

【図2】図1の動作のを説明するタイムチャートであ
る。
FIG. 2 is a time chart for explaining the operation of FIG. 1;

【図3】従来の電圧制御装置を示す電圧制御装置の回路
ブロック図である。
FIG. 3 is a circuit block diagram of a voltage control device showing a conventional voltage control device.

【図4】図3の動作を説明するタイムチャートである。FIG. 4 is a time chart for explaining the operation of FIG. 3;

【符号の説明】[Explanation of symbols]

1・・変圧器、2・・1次巻線、3・・2次巻線、4・
・チョッパ回路、5・・フィルタ回路、6a・・第1開
閉器、6b・・第2開閉器、8・・入力端子、9・・出
力端子、11・・制御部、12・・同期信号発生回路、
13・・電圧読込回路、14・・OR回路、15・・出
力電圧設定部。
1. Transformer, 2. Primary winding, 3. Secondary winding, 4.
Chopper circuit, 5 filter circuit, 6a first switch, 6b second switch, 8 input terminal, 9 output terminal, 11 control unit, 12 synchronization signal generation circuit,
13. Voltage reading circuit, 14. OR circuit, 15 output voltage setting section.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 変圧器の1次巻線をチョッパ回路を介在
させて単相3線電路の両電圧線間に接続すると共に、該
変圧器の2次巻線を前記両電圧線と負荷の間に直列接続
し、チョッパ回路のPWM制御によりチョッピングした
電圧を前記1次巻線に印加して負荷印加電圧を制御する
電圧制御方法であって、入力電圧の半周期毎に「H」,
「L」の信号を繰り返して発生する同期信号発生ステッ
プと、入力電圧信号の0クロス点を中心に前後数百μS
の間を常に「L」となるよう前記同期信号を加工して出
力する同期信号加工ステップとを有し、該加工した同期
信号が「L」の場合にPWM信号を出力してチョッパ制
御することを特徴とする電圧制御方法。
1. A primary winding of a transformer is connected between both voltage lines of a single-phase three-wire circuit via a chopper circuit, and a secondary winding of the transformer is connected between the two voltage lines and a load. A voltage control method for controlling a load applied voltage by applying a voltage chopped by PWM control of a chopper circuit to the primary winding, wherein "H" is applied every half cycle of the input voltage.
A synchronizing signal generating step of repeatedly generating an “L” signal, and a few hundred μs before and after the zero cross point of the input voltage signal.
A synchronization signal processing step of processing and outputting the synchronization signal so as to always be “L” during the period of time, and outputting a PWM signal to perform chopper control when the processed synchronization signal is “L”. A voltage control method characterized by the above-mentioned.
【請求項2】 同期信号が電源電圧の0クロス点を中心
に前後数百μS間に「H」,「L」の変化がなかったと
き、或いは0クロス点を中心に前後数百μS間以外で
「H」,「L」の変化があったときに停電と判断し、入
力電圧を遮断するステップを有することを特徴とする請
求項1記載の電圧制御方法。
2. When there is no change in “H” and “L” between several hundred μS before and after the zero cross point of the power supply voltage, or between several hundred μS before and after the zero cross point. 2. The voltage control method according to claim 1, further comprising the step of judging a power failure when there is a change in "H" and "L" and cutting off the input voltage.
【請求項3】 変圧器の1次巻線をチョッパ回路を介在
させて単相3線電路の両電圧線間に接続すると共に、該
変圧器の2次巻線を前記両電圧線と負荷の間に直列接続
し、チョッパ回路のPWM制御によりチョッピングした
電圧を前記1次巻線に印加して負荷印加電圧を制御する
電圧制御装置であって、PWM信号発生手段と、入力電
圧の周期に同期した信号を発生する同期信号発生手段
と、前記PWM信号と該同期信号発生手段からの同期信
号を組み合わせて前記チョッパ回路のスイッチング信号
を出力する制御手段とを有することを特徴とする電圧制
御装置。
3. A primary winding of a transformer is connected between both voltage lines of a single-phase three-wire circuit via a chopper circuit, and a secondary winding of the transformer is connected between the two voltage lines and a load. A voltage control device, which is connected in series between the first and second coils and controls a load applied voltage by applying a chopped voltage to the primary winding by PWM control of a chopper circuit, wherein the voltage control device is synchronized with a PWM signal generating means and a cycle of the input voltage. A voltage control device comprising: a synchronizing signal generating means for generating a converted signal; and a control means for outputting a switching signal of the chopper circuit by combining the PWM signal and a synchronizing signal from the synchronizing signal generating means.
【請求項4】 同期信号発生手段の発生信号が、電源電
圧の半周期毎に「H」,「L」を繰り返し、制御手段が
該同期信号を受けて、電源電圧の0クロス点を中心に前
後数百μSの間は常に「L」信号となるよう加工し、該
加工信号とPWM信号を組み合わせてスイッチング信号
を出力する請求項3記載の電圧制御装置。
4. A signal generated by the synchronizing signal generating means repeats "H" and "L" every half cycle of the power supply voltage. 4. The voltage control device according to claim 3, wherein the signal is processed so as to be always an "L" signal during several hundreds of seconds before and after, and a switching signal is output by combining the processed signal and the PWM signal.
【請求項5】 チョッパ回路の電源側電圧線に第1開閉
手段を、更に1次巻線の両端間に第2開閉手段を設ける
と共に、停電検出手段を設け、停電を検出した際に第1
開閉手段を開動作させると共に第2開閉手段を閉動作さ
せる請求項4記載の電圧制御装置。
5. A power supply side voltage line of a chopper circuit, a first switching means, a second switching means between both ends of a primary winding, and a power failure detection means are provided.
5. The voltage control device according to claim 4, wherein the opening / closing means is opened and the second opening / closing means is closed.
【請求項6】 停電検出手段は、同期信号発生手段から
の同期信号が電源電圧の0クロス点を中心に前後数百μ
S間に「H」,「L」の変化がなかったとき、或いは0
クロス点を中心に前後数百μS間以外で「H」,「L」
の変化があったときに停電と判断することを特徴とする
請求項5記載の電圧制御装置。
6. A power failure detection means, wherein the synchronization signal from the synchronization signal generation means is several hundred μm around a zero cross point of the power supply voltage.
When there is no change of “H” and “L” between S, or 0
"H", "L" except for a few hundred μS before and after the cross point
6. The voltage control device according to claim 5, wherein it is determined that a power failure has occurred when the power supply has changed.
JP2000186780A 2000-06-21 2000-06-21 Voltage control method and apparatus Expired - Fee Related JP4647752B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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JP4647752B2 JP4647752B2 (en) 2011-03-09

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002165454A (en) * 2000-11-27 2002-06-07 Kawamura Electric Inc Ac voltage regulator
JP2014093900A (en) * 2012-11-06 2014-05-19 Toshiba Mitsubishi-Electric Industrial System Corp Electric power conversion system
CN112134546A (en) * 2020-10-12 2020-12-25 四川英杰电气股份有限公司 Chopping drive circuit, method and electronic equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219987A (en) * 1996-02-14 1997-08-19 Mitsubishi Electric Corp Single-phase motor control device and actuator using the single-phase motor control device
JP2000056842A (en) * 1998-06-01 2000-02-25 Fuji Electric Co Ltd Power supply for lighting load
JP2001100850A (en) * 1999-09-29 2001-04-13 Kawamura Electric Inc Ac voltage regulator
JP2001175342A (en) * 1999-12-17 2001-06-29 Kawamura Electric Inc Ac voltage regulating device and method for controlling the device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09219987A (en) * 1996-02-14 1997-08-19 Mitsubishi Electric Corp Single-phase motor control device and actuator using the single-phase motor control device
JP2000056842A (en) * 1998-06-01 2000-02-25 Fuji Electric Co Ltd Power supply for lighting load
JP2001100850A (en) * 1999-09-29 2001-04-13 Kawamura Electric Inc Ac voltage regulator
JP2001175342A (en) * 1999-12-17 2001-06-29 Kawamura Electric Inc Ac voltage regulating device and method for controlling the device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002165454A (en) * 2000-11-27 2002-06-07 Kawamura Electric Inc Ac voltage regulator
JP2014093900A (en) * 2012-11-06 2014-05-19 Toshiba Mitsubishi-Electric Industrial System Corp Electric power conversion system
CN112134546A (en) * 2020-10-12 2020-12-25 四川英杰电气股份有限公司 Chopping drive circuit, method and electronic equipment

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