JP2002016259A - Semiconductor substrate manufacturing method, electro-optical device manufacturing method, semiconductor substrate and electro-optical device - Google Patents

Abstract

(57) Abstract: In a method of manufacturing a semiconductor substrate or an electro-optical device having a structure in which a semiconductor layer and a conductive layer including a refractory metal silicide layer are electrically connected, even if a high heating step is performed, A manufacturing method capable of reducing the contact resistance between the layer and the refractory metal silicide layer. SOLUTION: A semiconductor layer 202 is formed on a substrate 201, and an insulating film 2 patterned on the semiconductor substrate 202 is provided.
Heat treatment at 900 ° C. or more is performed in a state where the doped amorphous silicon film 209 and the refractory metal silicide film 206 a are sequentially formed on the semiconductor layer 202 and the insulating film 203. As a result, a doped polysilicon film 204 containing a high-concentration impurity is formed between the semiconductor layer 202 and the refractory metal silicide film 206, so that the semiconductor layer 202 and the refractory metal silicide film 206
Contact resistance with the contact can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate having a semiconductor and a thin film transistor (Thin) as the semiconductor substrate.
Film Transistor: an active matrix driving type electro-optical device having a TFT array substrate on which a TFT (hereinafter referred to as TFT) is disposed, and a method for manufacturing the same, particularly, a conductive layer including a semiconductor layer and a refractory metal silicide. It belongs to the technical field of lowering the resistance of a contact with a layer.

[0002]

2. Description of the Related Art Conventionally, in an electro-optical device of an active matrix driving system by TFT driving, a large number of scanning lines and data lines arranged vertically and horizontally and a large number of TFTs corresponding to their intersections are provided on a TFT array substrate. It is provided above. In each TFT, a gate electrode is connected to a scanning line, a source region of a semiconductor layer is connected to a data line, and a drain region of the semiconductor layer is connected to a pixel electrode.

[0003] The pixel electrode is disposed on an interlayer insulating film for insulating the various layers constituting the TFT and the wiring and the pixel electrode from each other. Therefore, recently, in order to improve the connection between the pixel electrode and the drain region, a conductive layer is arranged between the pixel electrode and the drain region, and the pixel layer and the drain region are electrically connected using the conductive layer as a relay. Technology has been developed. In detail, a relay conductive layer electrically connected to a drain region of the semiconductor layer through a contact hole formed in the gate insulating film is provided over a gate insulating film formed to cover the semiconductor layer, A data line is arranged on an insulating film formed to cover the conductive layer, an interlayer insulating film is arranged on the data line and the insulating film, and an insulating film and an interlayer insulating film are formed on the interlayer insulating film. It has a structure in which a pixel electrode electrically connected to a conductive layer through a contact hole is arranged. Further, by using a refractory metal silicide as the conductive layer, for example, the conductive layer can be used as a light-shielding film for partially defining a pixel opening region.

The connection structure between the semiconductor layer and the conductive layer of the TFT array substrate having such a structure is formed, for example, by the following manufacturing method.

[0005] First, as shown in FIG.
01, a semiconductor layer 202 in which impurity ions are implanted is arranged, a gate insulating film 203 made of a patterned silicon oxide film is arranged on the semiconductor layer 202, and further as a conductive layer electrically connected to the semiconductor layer. In which the high melting point metal silicide layer 306a is disposed.

Next, in this state, a heat treatment is performed at a temperature of 900 ° C. or more to activate the impurity ions in the semiconductor layer 202.

[0007]

However, as shown in FIG. 10 (b), the substrate after the above-described heat treatment has a high melting point under the high melting point metal silicide layer 306 and the semiconductor layer 202. Melting point metal silicide layer 306a
Is formed in a region in which a high-purity silicon layer 304 containing no impurity ions is formed.
In a region where the high melting point metal silicide layer 306a is in contact with the high melting point metal silicide layer 306a, the silicon oxide film 305 is formed. Further, in the upper layer of the refractory metal silicide layer 306,
The structure is such that a silicon film 307 is formed on the surface of the refractory metal silicide layer 306a. Note that when a film containing oxygen is formed over the high-melting metal silicide layer 306a, the silicon film 307 becomes a silicon oxide layer.

As a result, the high-purity silicon layer 304 is interposed between the semiconductor layer 202 and the high-melting-point metal silicide layer 306, and the contact resistance between the semiconductor layer 202 and the high-melting-point metal silicide layer 306 increases. There has been a problem that the response speed of the optical device is slow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-described problems, and provides a method of manufacturing a semiconductor substrate and a method of manufacturing an electro-optical device having a low contact resistance between a semiconductor layer and a conductive layer. It is an object to provide an electro-optical device.

[0010]

According to the present invention, there is provided a method for manufacturing a semiconductor substrate, comprising the steps of: (a) forming a semiconductor layer on a substrate; and (b) forming a semiconductor layer on the semiconductor layer.
Forming an insulating film having a contact hole corresponding to a part of the semiconductor layer; (c) forming an impurity-implanted silicon film on the insulating film and the semiconductor layer; A step of forming a refractory metal silicide film on the silicon film; and (e) a step of heat-treating the substrate at a temperature of 900 ° C. or more after the step (d).

According to the structure of the present invention, the semiconductor layer and the refractory metal silicide film are formed by performing a heat treatment in a state where the impurity-implanted silicon film is formed under the refractory metal silicide film. Between the semiconductor layer and the high-melting-point metal silicide layer, which has the effect of reducing the contact resistance between the semiconductor layer and the refractory metal silicide layer. In particular, even when a heating step at a high temperature of 900 ° C. or more is performed, the semiconductor layer and the high melting point metal silicide film are formed by interposing the impurity-containing silicon film between the semiconductor layer and the high melting point metal silicide film. Can be reduced.

Further, an impurity is implanted into the semiconductor layer, and the impurity is activated in the step (e). With such a configuration, even when it is necessary to perform a step of activating impurity ions that require a high-temperature treatment, a reduction in contact resistance between the semiconductor layer and the refractory metal silicide film can be realized. Has an effect.

(F) After the step (d) and before the step (e), the method further comprises a step of patterning the silicon film and the refractory metal silicide film into a predetermined shape to form a wiring. It is characterized by doing. With such a configuration, even when a wiring including a high-melting metal silicide film is used, there is an effect that the resistance of the contact between the semiconductor layer and the wiring can be reduced.

Further, the silicon film formed in the step (c) is an amorphous silicon film. By using an amorphous silicon film in this way, when the polysilicon film is formed in a later step, the crystal grain size of the polysilicon film can be increased, and as a result, a low-resistance impurity-containing silicon film can be obtained. It has the effect of being able to

Further, the amorphous silicon film is turned into polysilicon by the step (e). With such a configuration, the crystal grain size of the polysilicon film can be increased, and as a result, there is an effect that a low-resistance impurity-containing silicon film can be obtained. Further, there is an effect that activation of impurities in the semiconductor layer and conversion of the amorphous silicon film into polysilicon can be performed simultaneously.

According to the method of manufacturing an electro-optical device of the present invention, there are provided a plurality of scanning lines, a plurality of data lines intersecting the scanning lines, a thin film transistor connected to each of the scanning lines and the data line; (A) forming a semiconductor layer to be a source region, a channel region, and a drain region of the thin film transistor on a substrate; and (b) forming a semiconductor layer on a substrate. Forming a gate insulating film covering the semiconductor layer; (c) forming the scanning line on the gate insulating film; and (d) forming a first contact hole in the gate insulating film corresponding to the drain region. (E) forming an impurity-implanted silicon film on the scanning lines and the gate insulating film; and (f) forming a high-melting silicon film on the silicon film. Forming a metal silicide film; (g) patterning the silicon film and the refractory metal silicide film to form a conductive layer electrically connected to the first contact hole; g) after the step, performing a heat treatment at a temperature of 900 ° C. or higher; and (i) having a second contact hole corresponding to the source region on the gate insulating film including the conductive layer that has undergone the heat treatment. Forming an insulating film; (j) forming the data line electrically connected to the source region through the second contact hole on the insulating film; and (k) forming the data line. On the insulating film containing
Forming an interlayer insulating film having a third contact hole corresponding to the conductive layer; and (l) forming an interlayer insulating film on the interlayer insulating film through the third contact hole and electrically connected to the conductive layer. Forming a pixel electrode.

According to the structure of the present invention, the semiconductor layer and the refractory metal silicide are heated as a result of performing the heat treatment in a structure in which the silicon layer doped with impurities is arranged below the refractory metal silicide layer. A structure in which a silicon layer containing a high-concentration impurity is interposed between the layers, which has an effect that the contact resistance between the semiconductor layer and the refractory metal silicide layer can be reduced. Thus, 900 ° C
Even after the high-temperature heating step described above, the contact resistance between the semiconductor layer and the high-melting-point metal silicide film is obtained by adopting a structure in which the impurity-containing silicon film is interposed between the semiconductor layer and the high-melting-point metal silicide film. Can be reduced. Accordingly, a thin film transistor having a high response speed can be obtained, and an electro-optical device with improved display quality can be obtained. In addition, since the conductive layer contains a high-melting-point metal silicide, the light-shielding property is high, and together with the data lines and a light-shielding film formed on a counter substrate that is disposed to face a TFT array substrate usually called a black matrix, the pixel is formed. Can be defined. In particular, if the opening area is defined without forming a light shielding film on the opposite substrate,
Advantageously, it is possible to reduce the number of steps in the manufacturing process, and it is also possible to prevent the pixel aperture ratio from being lowered or varied due to misalignment between a pair of substrates.

Further, the semiconductor layer is formed by implanting an impurity, and the impurity is activated in the step (h). With such a configuration, even when it is necessary to perform an impurity ion activation step that requires a high temperature treatment, an effect that a low resistance of the contact between the semiconductor layer and the high melting point metal silicide film can be realized is achieved. .

Further, the silicon film formed in the step (e) is an amorphous silicon film. By using an amorphous silicon film in this way, when the polysilicon film is formed in a later step, the crystal grain size of the polysilicon film can be increased, and as a result, a low-resistance impurity-containing silicon film can be obtained. It has the effect that can be done.

Further, the amorphous silicon film is converted into polysilicon by the step (h). With such a configuration, the crystal grain size of the polysilicon film can be increased, and as a result, there is an effect that a low-resistance impurity-containing silicon film can be obtained. Further, there is an effect that activation of impurities in the semiconductor layer and conversion of the amorphous silicon film into polysilicon can be performed simultaneously.

Further, the refractory metal silicide film is a light shielding film. With such a configuration, for example, by arranging the conductive layer along the scanning line, it is also possible to define the pixel opening area on the side along the scanning line.

Further, the electro-optical device further includes a capacitance line disposed in the same layer and in parallel with the scanning line, and a dielectric layer formed so as to cover the capacitance line. A capacitance is formed by the capacitance line and the conductive layer arranged via a dielectric layer. According to such a configuration, there is an effect that the conductive layer can be configured to also serve as a capacitor electrode.

Further, the electro-optical device further includes a capacitance electrode having the semiconductor layer extended, and a capacitance is formed by the capacitance electrode and the capacitance line arranged via the gate electrode. It is characterized by becoming. With such a configuration, since two capacitors can be formed by being stacked, there is an effect that the capacitance can be increased while maintaining the pixel aperture ratio.

In the step (k), the step of forming the interlayer insulating film on the insulating film including the data line includes the step of forming the interlayer insulating film with a stopper using the high melting point metal silicide layer of the conductive layer as a stopper. Forming the third contact hole by etching. As described above, the etching is performed using a solution that etches only the interlayer insulating film without etching the metal silicide layer as an etchant, so that the metal silicide layer functions as a stopper, and the etching can be efficiently performed. Have.

Further, the pixel electrode is made of indium-tin-tin.
It is characterized by being made of an oxide film. The use of the indium tin oxide film as the pixel electrode has an effect that the contact resistance with the conductive layer can be reduced.

Further, the refractory metal silicide film comprises:
It is a silicide film of a metal selected from at least one of W, Ti, Ta, Mo, and V. As described above, as the refractory metal silicide film, a refractory metal silicide containing at least one of Ti (titanium), W (tungsten), Ta (tantalum), Mo (molybdenum), and V (vanadium) is used. Can be used.

(M) after the step (k),
Before the step (l), a step of treating the substrate with a hydrofluoric acid-based treatment liquid is provided. Thus, the hydrofluoric acid-based treatment liquid, for example, diluted hydrofluoric acid (hydrofluoric acid: water = 1: 3
By treating the substrate using (0-50), dust and SiO2 remaining in the third contact hole can be removed, and the contact resistance between the pixel electrode formed later and the conductive layer can be reduced. Having. Furthermore, when a conventional conductive layer made of a high-melting-point metal silicide layer is used, there is a problem in that the above-mentioned hydrofluoric acid treatment causes cracks in the conductive layer. Since a high-concentration impurity-containing silicon layer is formed on the silicide layer, cracks are not generated by the hydrofluoric acid-based treatment liquid, and a high-quality conductive layer can be obtained.

A semiconductor substrate according to the present invention is manufactured by the above-described method for manufacturing a semiconductor substrate.

According to this structure of the present invention, since the high-concentration impurity silicon layer is interposed between the refractory metal silicide layer and the semiconductor layer, the contact between the refractory metal silicide layer and the semiconductor layer is formed. This has the effect that the resistance can be reduced.

An electro-optical device according to the present invention is manufactured by the above-described method for manufacturing an electro-optical device.

According to this structure of the present invention, since the high-concentration impurity silicon layer is interposed between the high-melting-point metal silicide layer and the semiconductor layer, the contact between the high-melting-point metal silicide layer and the semiconductor layer is formed. This has the effect that the resistance can be reduced. Accordingly, a thin film transistor having a high response speed can be obtained, and an electro-optical device with improved display quality can be obtained. In addition, since the conductive layer contains a high-melting-point metal silicide, the light-shielding property is high, and together with the data lines and a light-shielding film formed on a counter substrate that is disposed to face a TFT array substrate usually called a black matrix, the pixel is formed. Can be defined. In particular, if the opening area is defined without forming a light-shielding film on the opposing substrate, it is possible to reduce the number of steps in the manufacturing process and to prevent a reduction or variation in the pixel aperture ratio due to misalignment between the pair of substrates. Is advantageous.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment of Semiconductor Substrate) Regarding the configuration of an embodiment of a semiconductor substrate having a semiconductor layer according to the present invention,
It is formed using FIG.

FIG. 1 is a partial sectional view showing a connection structure between a semiconductor layer and a conductive layer of a semiconductor substrate.

As shown in FIG. 1, a semiconductor layer 202 made of polysilicon containing phosphorus (P) is arranged on a substrate 201 such as a quartz substrate. Semiconductor layer 20
An insulating film 203 made of, for example, a silicon oxide film and patterned in a predetermined shape is disposed on the surface 2. Further, a conductive layer is provided over the semiconductor layer 202 including the insulating film 203. This conductive layer has a three-layer structure,
A doped polysilicon film 204 as a high-concentration impurity-containing silicon film containing P ions as an impurity, a tungsten silicide (WSi) film 206 as a refractory metal silicide film, and a silicon oxide (SiO ₂ ) film 207
Are sequentially laminated.

In the semiconductor substrate manufactured by the manufacturing method of this embodiment, a doped polysilicon film 204 containing P ions at a high concentration is interposed between the semiconductor layer 202 and the tungsten silicide film 206. The contact resistance between the semiconductor layer 202 and the tungsten silicide film 206 can be reduced. By using a semiconductor substrate having such a structure in, for example, a computer, high-speed processing can be performed.

(Manufacturing Process in Embodiment of Semiconductor Substrate) Next, a method of manufacturing the semiconductor substrate shown in FIG. 1 will be described with reference to FIG.

First, as shown in the step (1) of FIG. 2, 201 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the substrate 201 in a high-temperature process performed later is reduced. deep. Then, on the substrate 201 thus processed, about 450 to
In a relatively low temperature environment of 550 ° C., preferably about 500 ° C., the amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min. Form. Then, in a nitrogen atmosphere, about 600
Annealing is performed at a temperature of about 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film 202 has a thickness of about 50 to 200 nm, preferably about 10 to 200 nm.
Solid phase growth is performed to a thickness of 0 nm. As a method for solid phase growth, annealing using RTA (Rapid Thermal Anneal) may be used, or laser annealing using an excimer laser or the like may be used. Then, Sb (antimony) is added to the polysilicon film 202 in the channel region.
Group V elements such as As (arsenic) and P (phosphorus), and here P ions are implanted as impurities. Note that the polysilicon film 202 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 202 may be formed by implanting P ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the polysilicon film once amorphous (amorphized), and then recrystallize by annealing or the like.

Next, as shown in step (2), low pressure CVD
About 50 nm insulating film made of silicon oxide
Is deposited to a relatively small thickness, and is patterned into a predetermined shape to form an insulating film 203.

Next, as shown in step (3), while introducing P ions as impurities, an amorphous silicon film is deposited by a low pressure CVD method or the like to form a doped amorphous silicon film 209 into which P ions are introduced. I do. The thickness of the doped amorphous silicon film 209 is about 10
It is formed to a thickness of 0 to 1000 nm, preferably about 500 nm. Here, a polysilicon film may be formed instead of the amorphous silicon film. However, when the amorphous silicon film is formed and then the polysilicon film is formed, the crystal grain system can be increased and the resistance can be reduced.

Next, as shown in step (4), a tungsten silicide film 206a as a refractory metal silicide is
The film is formed to a thickness of about 4000 nm.

Next, in order to activate P ions implanted into the polysilicon film 202, heat treatment is performed for 20 minutes in an atmosphere of an inert gas such as N ₂ (nitrogen) and a high temperature of about 900 to 1300 ° C. . As a result, the doped amorphous silicon film 209 and the tungsten silicide film 206a
At the interface with silicon, silicon and phosphorus are precipitated from the tungsten silicide film to form a deposited layer 205 made of a polysilicon film containing high-concentration impurities. Further, at the same time, the doped amorphous silicon film 209 is converted into polysilicon, and becomes a polysilicon film 208 containing high-concentration impurities. The deposited layer 205 and the polysilicon film 208 containing a high concentration impurity are polysilicon films having the same impurity concentration. Therefore, they are actually configured as the same layer, and the same layer is configured as the doped polysilicon film 204 containing impurities at a high concentration.

Therefore, as shown in FIG. 2 (5), on the insulating film 203 and the polysilicon film 202, a doped polysilicon film 204 containing P ions at a high concentration, a tungsten silicide film 206, a silicon oxide film 207 are sequentially stacked to form a conductive layer having a three-layer structure.

As described above, in the present embodiment, the tungsten silicide film 206 and the semiconductor layer 2 are formed by performing high-temperature processing in a state where the silicon film containing impurity ions is disposed under the tungsten silicide film 206a.
Since the doped polysilicon film 204 containing a high-concentration impurity is formed between the tungsten silicide film 206 and the semiconductor layer 202, the contact resistance between the tungsten silicide film 206 and the semiconductor layer 202 can be reduced.

That is, conventionally, in the high-temperature processing step,
Since a silicon layer containing no impurity ions was formed between the tungsten silicide layer and the semiconductor layer, the contact resistance between the tungsten silicide film and the semiconductor layer was increased. On the other hand, in the present embodiment, since the silicon layer containing impurity ions is formed, the silicon layer containing no impurity ions is not formed as in the related art, and the contact resistance value does not decrease.

(Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is an embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. Note that, in the present embodiment, the contact structure between the conductive layer and the semiconductor layer in the above-described embodiment of the semiconductor substrate is the same as the conductive structure arranged for relaying when the pixel electrode and the drain region of the semiconductor layer are electrically connected. It is applied to the contact structure between the layer and the drain region.

FIG. 3 is an equivalent circuit diagram of various elements, wiring, etc. in a plurality of pixels formed in a matrix forming an image display area of the liquid crystal device. FIG. 4 is a diagram showing data lines, scanning lines, pixel electrodes, FIG. 5 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a light-shielding film and the like are formed, and FIG. 5 is a cross-sectional view taken along line AA ′ of FIG. In the drawings, in order to make each layer and each member a size recognizable in the drawing,
The scale is different for each layer and each member.

In FIG. 3, a plurality of pixels formed in a matrix and constituting a pixel display area of the liquid crystal device according to the present embodiment are provided with TFTs 3 for controlling a pixel electrode 9a.
A plurality of 0s are formed in a matrix, and the data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Also, T
The scanning line 3a is electrically connected to the gate of the FT 30, and is configured to apply the scanning signals G1, G2,..., Gm in a pulsed manner to the scanning line 3a in this order at a predetermined timing. ing. The pixel electrode 9a is a TFT 30
Of the TFT 30 which is a switching element and is closed by a switch for a predetermined period, so that the image signal S supplied from the data line 6a is provided.
1, S2,..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are supplied to a counter substrate (described later).
Is maintained for a certain period of time with a counter electrode (to be described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. As a whole, light having a contrast corresponding to the image signal is emitted from the liquid crystal device. here,
In order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 4, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected to a source region described later in the semiconductor layer 1 made of a polysilicon film or the like via the contact hole 5, and the pixel electrode 9a is connected to a region shown by oblique lines rising to the right in the figure. The semiconductor layer 1 is electrically connected to a later-described drain region of the semiconductor layer 1 via the first contact hole 8a and the third contact hole 8b via the conductive layer 80 which is formed and functions as a buffer.
Further, the scanning line 3a is arranged so as to face the channel region 1a (the hatched region on the right in the figure) of the semiconductor layer 1, and the scanning line 3a functions as a gate electrode. As described above, at the intersections of the scanning lines 3a and the data lines 6a, the TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a are provided.

The capacitance line 3b includes a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the drawing) along the data line 6a from a location intersecting the data line 6a. And

Further, a first light-shielding film 11 a is provided in a region indicated by a thick line in the drawing so as to pass under the scanning line 3 a, the capacitor line 3 b and the TFT 30, respectively. More specifically, in FIG. 4, the first light-shielding films 11a
Are formed in a striped shape along with the data line 6a, and a portion intersecting the data line 6a is formed wide downward in the figure, and the channel portion 1a of each TFT is formed by this wide portion.
It is provided at a position to cover each as viewed from the array substrate side.

As shown in the sectional view of FIG.
Reference numeral 0 denotes a TFT array substrate 90 as a semiconductor substrate forming an example of one transparent substrate, an opposing substrate 60 forming an example of the other transparent substrate disposed opposite to the TFT array substrate 90, and a liquid crystal layer between the two substrates. 50 are sandwiched. TFT
The array substrate 90 is made of, for example, a quartz substrate, and the counter substrate 60 is made of, for example, a glass substrate or a quartz substrate. TFT
In the array substrate 90, a pixel electrode 9a is provided on a quartz substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is, for example,
It is made of an organic thin film such as a polyimide thin film. Liquid crystal layer 50
Takes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed.

Hereinafter, the structure of the TFT array substrate 90 will be described in detail.

Each of the pixel electrodes 9 is provided on the TFT array substrate 90.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a. As shown in FIG.
A first light-shielding film 11a is provided between the quartz substrate 10 and each pixel switching TFT 30 at a position facing each other. The first light-shielding film 11a is preferably composed of a simple metal, an alloy, or the like, including at least one of Ti, Cr, W, Ta, Mo, and Pd, which are preferably opaque refractory metals.
It is composed of metal silicide or the like. With such a material, the first light shielding film 11 on the TFT array substrate 90 can be formed.
TFT for pixel switching performed after the step of forming a
The first light-shielding film 1 is formed by high-temperature processing in the
1a can be prevented from being broken or melted. Since the first light shielding film 11a is formed, the TFT array substrate 70
It is possible to prevent a situation in which reflected light (return light) or the like from the side enters the channel region 1a, the source-side LDD region 1b, and the drain-side LDD 1c of the pixel switching TFT 30, which easily excites light. The characteristics of the pixel switching TFT 30 do not deteriorate due to the generation of the photocurrent due to the above.

A base insulating film 12 is provided between the first light-shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 is a pixel switching TFT
The semiconductor layer 30 is provided to electrically insulate the semiconductor layer from the first light shielding film 11a. Further, the base insulating film 12 also functions as a base film for the pixel switching TFT 30 by being formed on the entire surface of the quartz substrate 10. The base insulating film 12 is made of, for example, NS.
It is made of a highly insulating glass such as G (non-doped silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon oxide film, a silicon nitride film, or the like.

The pixel switching TFT 30 is an LDD
A scanning line 3a, a channel region 1a of a semiconductor layer 1 in which a channel is formed by an electric field from the scanning line 3a, a gate insulating film 2 insulating the scanning line 3a from the semiconductor layer 1, a semiconductor layer 1 low-concentration source region (source side L
DD region) 1b and a lightly doped drain region (drain side L
DD region 1c, a high concentration source region 1d of the semiconductor layer 1, and a high concentration drain region 1e. The high-concentration drain region 1e is electrically connected to a conductive layer 80 disposed on the second dielectric film 81 via a contact hole 8a, and is electrically connected to the corresponding pixel electrode 9a via the conductive layer 80. The detailed cross-sectional structure will be described later. Source regions 1b and 1d and drain region 1
As described later, c and 1e are formed by doping the semiconductor layer 1 with a predetermined concentration of n-type or p-type dopants depending on whether an n-type or p-type channel is to be formed. . An n-type channel TFT has the advantage of a high operating speed, and is often used as a pixel switching TFT 30 that is a pixel switching element.

The gate insulating film 2 is provided on the semiconductor film 1. A scanning line 3a and a capacitance line 3b are arranged on the gate insulating film 2, and a gate electrode which is a part of the scanning line 3a is arranged corresponding to the channel region 1a of the semiconductor layer. The high-concentration drain region 1e of the semiconductor layer 1 extends below the data line 6a and the scanning line 3a to form a pixel switching TF.
T30 is formed. Further, a part of the semiconductor layer 1 is extended from the high-concentration drain region 1e to form a first storage capacitor electrode 1f.
A part of the capacitance line 3b opposed thereto is used as a second storage capacitance electrode, the gate insulating film 2 is extended from a position facing the scanning line 3a, and the gate insulating film 2 is sandwiched between these electrodes. By using a part as the first dielectric film, the first
A storage capacity is configured. This first dielectric film is formed on the gate insulating film 2 of the TFT 30 formed on the polysilicon film.
Therefore, it is possible to form a thin and high-breakdown-voltage insulating film, and the first storage capacitor can be configured as a large-capacity storage capacitor having a relatively small area.

Further, a first silicon oxide film is formed on the gate insulating film 2 so as to cover the scanning lines 3a and the capacitance lines 3b.
An insulating film 81 is provided. A conductive layer 80 is disposed on the first insulating film 81, and the conductive layer 80 is formed on the first contact hole 8 formed in the gate insulating film 2 and the first insulating film 81.
a, it is electrically connected to the high concentration drain region 1e of the semiconductor layer 1.

The conductive layer 80 has a structure in which a doped polysilicon film 83 as a silicon film containing a high-concentration impurity, a tungsten silicide layer 84 as a high melting point metal silicide, and a silicon oxide layer 85 are sequentially laminated. I have.
The specific resistance of the doped polysilicon film 204 is 6 × 10 ⁻⁴ to
It is preferably 8 × 10 ⁻⁴ Ω · cm, and the film thickness is 50
0-2000 nm is preferred. Further, the thickness of the semiconductor layer is preferably 400 nm, the thickness of the tungsten silicide film 206 is preferably 1000 to 4000 nm, and the thickness of the silicon oxide film 207 is preferably 800 to 1000 nm. The impurity ions implanted into the doped polysilicon film 83 are the same as the impurity ions implanted into the semiconductor layer 1.
A part of the conductive layer 80 facing the second storage capacitor electrode also functions as a third storage capacitor electrode, and the first insulating film 81 disposed between the third storage capacitor electrode and the second storage capacitor electrode has It functions as a two-dielectric film, and a second storage capacitor is formed by these electrodes and the second dielectric film. Second dielectric film 81
Since the second storage capacitor can be formed as thin as the gate insulating film 2, the second storage capacitor can be configured as a large-capacity storage capacitor having a relatively small area. The storage capacitor 70 is formed by connecting the second storage capacitor and the first storage capacitor in parallel. Since the storage capacitor 70 formed three-dimensionally from the first and second storage capacitors can form a large-capacity storage capacitor with a small area, the storage capacitor 70 extends along the region below the data line 6a or along the scanning line 3a. (That is, the area where the capacitance line 3b is formed) outside the pixel opening area can be effectively used.

Further, the second insulating film 4 is disposed so as to cover the conductive layer 80 and the first insulating film 81. On the second insulating film 4,
Data line 6 composed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide.
a, and a source electrode 6 which is a part of the data line 6a.
“a” is electrically connected to the high-concentration source region 1 d of the semiconductor layer 1 via the second contact hole 5 formed in the first insulating film 81, the gate insulating film 2, and the second insulating film 4.

Further, a pixel electrode 9a is arranged on the interlayer insulating film 7 arranged so as to cover the data line 6a and the second insulating film 4. The pixel electrode 9a includes a silicon oxide film 85, a second
It is electrically connected to the conductive layer 80 via a third contact hole 8b formed in the insulating film 4 and the interlayer insulating film 7.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c.
A self-aligned TFT in which impurity ions are implanted at a high concentration using the gate electrode 3a as a mask to form self-aligned high-concentration source and drain regions may be used.

Further, in the present embodiment, a single gate structure in which only one gate electrode 3a of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e is provided. May be arranged. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced.
If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced,
A stable switching element can be obtained.

As shown in FIGS. 4 and 5, in the liquid crystal device 200 of this embodiment, the data lines 6 a and the scanning lines 3 a are three-dimensionally arranged on the TFT array substrate 90 via the second insulating film 4. It is provided so as to intersect. The conductive layer 80 is interposed between the semiconductor layer 1 and the pixel electrode 9a, and electrically connects the high-concentration drain region 1e and the pixel electrode 9a via the first and third contact holes 8a and 8b. Connecting. For this reason, compared with the case where one contact hole is opened from the pixel electrode 9a to the drain region of the semiconductor layer 1, the first and third contact holes 8a and 8
The diameter of b can be reduced.

On the other hand, the glass substrate 20
A counter electrode 21 is provided over the entire surface thereof,
An alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the alignment film 22. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film. On the counter substrate 60, a second light-shielding film 23 called a black mask or a black matrix is provided in a non-opening region of each pixel.
May be provided. Accordingly, incident light does not enter the channel region 1a, the source-side LDD region 1b, and the drain-side LDD region 1c of the semiconductor layer 1 of the pixel switching TFT 30 from the side of the counter substrate 60. Further, the second light-shielding film 23 has functions such as improvement of contrast and prevention of color mixing of coloring materials when a color filter is formed.

In the present embodiment, in particular, the first dielectric film 2 and the second dielectric film 81 in the storage capacitor 70 which is three-dimensionally formed with the conductive layer 80 at the center are both three-dimensionally crossed. This is a dielectric film different from the second insulating film 4 interposed between the data line 6a and the scanning line 3a. Therefore, in order to suppress the parasitic capacitance between the data line 6a and the scanning line 3a which causes a voltage drop of the image signal which causes flicker or the like, the conductive layer 80 is provided via a layer different from the second insulating film 4 to accumulate the data. In order to add capacity, in the case of this embodiment,
The first dielectric film 2 and the second dielectric film 81 can be formed as thin as technically possible. As a result,
In particular, it is possible to extremely efficiently increase the capacitance value of the second storage capacitor, which is inversely proportional to the thickness of the second dielectric film 81. In particular, if the gate insulating film 2 in the pixel switching TFT 30 is configured to be too thin, a unique phenomenon such as a tunnel effect does not occur. 10 nm or more and 50 nm thinner than the insulating film 2
By forming the extremely thin second dielectric film 81 having the following thickness, a very large second storage capacitor can be formed in a relatively small region. Accordingly, not only the occurrence of flicker can be suppressed, but also the voltage holding ability can be increased, so that a high-contrast liquid crystal device can be provided.

According to experiments and studies conducted by the inventors of the present application, in a technology in which the conductive layer 80 is formed from the same conductive layer as the data line 6a, the conductive layer 80 is used as one electrode of the storage capacitor. Assuming that an insulating film between the data line 6a and the scanning line 3a is used as a dielectric film, in order to prevent the parasitic capacitance between the data line 6a and the scanning line 3a from becoming a problem, a dielectric film (this embodiment) is used. The film corresponding to the second insulating film 4 in the form) requires a thickness of about 800 nm. Therefore, in the present embodiment, the second storage capacitor having a capacitance value several times to ten and several times or more in the same area can be realized, which is extremely advantageous.

The thickness of the conductive layer 80 is, for example, 50 n
It is preferable that the thickness be not less than m and not more than 500 nm. 50n
If the contact hole 8b has a thickness of about m, the likelihood of the contact hole 8b piercing when the contact hole 8b is opened in the manufacturing process is reduced,
Further, if the thickness is about 500 nm, the unevenness on the surface of the pixel electrode 9a does not pose a problem or can be relatively easily planarized.

In the liquid crystal device of the present embodiment, in the contact structure between the conductive layer 80 and the semiconductor layer 1, between the tungsten silicide layer 84 and the semiconductor layer 1, doped polysilicon containing P ions at a high concentration is provided. Since the layer 83 is interposed, the contact resistance between the semiconductor layer 1 and the tungsten silicide layer 84 can be reduced. Thereby, a TFT having a high response speed can be obtained.

Further, when the conductive layer 80 is used as an electrode for a storage capacitor, a low-resistance doped polysilicon and a low-concentration impurity silicon film are included. Thus, it also has a function of increasing the storage capacity 70. Further, by including the doped polysilicon layer 83 having low resistance, stress due to heat or the like is less likely to be generated with the second insulating film 4, which helps to prevent cracks in the conductive layer 80 and its surroundings.

The conductive layer 80 has a light-shielding property because it contains a high-melting-point metal silicide layer. Therefore, the conductive layer 8
0 makes it possible to at least partially define each pixel aperture region. Further, by defining the pixel openings by the conductive layer 80 or by combining light-shielding wiring such as the data lines 6 a with a light-shielding film formed on the TFT array substrate 90, the opposing substrate 60 side is defined. It is also possible to omit the second light shielding film. Counter substrate 60
The configuration in which the conductive layer 80 is provided as a built-in light-shielding film on the TFT array substrate 90 instead of the upper second light-shielding film 23 can reduce the pixel aperture ratio due to misalignment between the TFT array substrate 90 and the counter substrate 60 in the manufacturing process. This is extremely advantageous in that it is not invited. The second light-shielding film 23 on the opposite substrate 60
For the purpose of suppressing the temperature rise of the liquid crystal device mainly due to the incident light, the pixel may be formed to be small (narrow) so as not to define the pixel opening region. In this case, if the second light-shielding film 23 is formed of a material having a high reflectance such as an Al film, the temperature rise can be suppressed more efficiently. If the second light-shielding film 23 is formed to be smaller than the light-shielding region in the TFT array substrate, the pixel opening region does not need to be reduced due to a slight displacement between the two substrates in the manufacturing process.

As the refractory metal silicide, for example,
A metal silicide containing at least one of Ti, W, Ta, Mo, and V, which is a high melting point metal, can be used. These refractory metal silicides form the pixel electrode 9a.
Since the refractory metal silicide does not corrode even if it comes into contact with the ITO film constituting the third contact hole 8
A good contact can be made between the conductive layer 80 and the pixel electrode 9a via b.

As described above, in the electro-optical device according to the present embodiment, since the contact resistance between the semiconductor layer and the conductive layer can be reduced, an electro-optical device having a TFT capable of high-speed response can be obtained. A high quality electro-optical device can be obtained.

(Manufacturing Process in Embodiment of Electro-Optical Device) Next, a manufacturing process of the liquid crystal device in the embodiment having the above configuration will be described with reference to FIGS. 6 to 9 show T in each step.
Each of the layers on the FT array substrate side is the same as that shown in FIG.
It is a process drawing shown corresponding to A 'section.

First, as shown in step (1) of FIG. 6, a substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the substrate 10 in a high-temperature process performed later is reduced. deep. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest processing temperature at the highest temperature in the manufacturing process. Then, on the entire surface of the TFT array substrate 10 thus treated, Ti, Cr, W,
A metal such as Ta, Mo and Pd or a metal alloy film such as metal silicide is formed by sputtering to a thickness of 100 to 500 nm.
Light-shielding film 1 having a thickness of about 200 nm, preferably about 200 nm.
Form one. Note that an anti-reflection film such as a polysilicon film may be formed on the light-shielding film 11 to reduce surface reflection.

Next, as shown in step (2), a resist mask corresponding to the pattern of the first light-shielding film 11a (see FIG. 4) is formed on the formed light-shielding film 11 by photolithography. The first light-shielding film 11a is formed by etching the light-shielding film 11 through the step.

Next, as shown in step (3), a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl)・ Boat rate) Gas, T
The underlying insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using MOP (tetramethyl oxyphosphate) gas or the like. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm. When the return light from the back surface of the substrate 10 does not matter, it is not necessary to form the first light shielding film 11a.

Next, as shown in step (4), a temperature of about 450 to 550 ° C., preferably about 500
Flow rate of about 400 to 600 cc /
An amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like for min. Thereafter, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 100 is solid-phase grown to a thickness of about 50 to 200 nm, preferably about 100 nm, by performing an annealing process for 4 to 6 hours. As a method for solid phase growth, RTA (Rapid
Thermal annealing may be used, or laser annealing using an excimer laser or the like may be used.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG.
V such as b (antimony), As (arsenic), and P (phosphorus)
The dopant of the group element may be implanted slightly by ion implantation or the like. When the pixel switching TFT 30 is a p-channel type, a dopant of a group III element such as B (boron), Ga (gallium), or In (indium) may be implanted slightly by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, silicon ions are implanted into a polysilicon film deposited by a low pressure CVD method or the like, and the polysilicon film is once made amorphous.
Then, the polysilicon film 100 may be formed by recrystallization by annealing or the like.

Next, as shown in a step (5), a semiconductor layer 1 having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 4 is formed by a photolithography step, an etching step and the like.

Next, as shown in the step (6), the first layer is formed together with the semiconductor layer 1a constituting the pixel switching TFT 30.
By thermally oxidizing the storage capacitor electrode 1f at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C., a relatively thin thermally oxidized silicon film 2 of about 30 nm is formed.
a, and then, as shown in step (7),
An insulating film 2b made of a high-temperature silicon oxide film (HTO film) is deposited to a relatively thin thickness of about 50 nm by a method or the like, and the gate of the pixel switching TFT 30 having a multilayer structure including the thermal silicon oxide film 2a and the insulating film 2b is deposited. A first dielectric film 2 for forming a storage capacitor is formed simultaneously with the insulating film 2. As a result, the thickness of the first storage capacitor electrode 1f is about 30 to 15
0 nm, preferably about 35 to 50 nm, and the gate insulating film 2 (first dielectric film) has a thickness of about 20 nm.
A thickness of 150 nm, preferably a thickness of about 30-100 nm. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the gate insulating film 2 having a single-layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Next, as shown in a step (8), a resist layer 50 is formed by a photolithography step, an etching step and the like.
0 is the semiconductor layer 1 excluding the portion serving as the first storage capacitor electrode 1f
After forming on P.a, for example, P ions are dosed at about 3 × 1
Implantation may be performed at 0 ¹² / cm ² to lower the resistance of the first storage capacitor electrode 1f.

Next, as shown in step (9), after removing the resist layer 500, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to form the polysilicon film 3. It becomes conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The thickness of the polysilicon film 3 is about 100 to 50.
Deposit to a thickness of 0 nm, preferably about 300 nm.

Next, as shown in a step (10) of FIG. 7, by a photolithography step using a resist mask, an etching step, and the like, a scanning line 3a having a predetermined pattern as shown in FIG. 4 and a capacitance line 3b are formed. . The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, the semiconductor layer 1 first includes the low-concentration source region 1b and the low-concentration source region 1b. In order to form the concentration drain region 1c, a dopant of a group V element such as P is used at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ / cm ^{2 using} the scanning line 3a (gate electrode) as a mask. Dope in amount). Thereby, the semiconductor layer 1 under the scanning line 3a
Becomes the channel region 1a. The resistance of the capacitance line 3b and the scanning line 3a is also reduced by the doping of the impurity.

Next, as shown in step (12), the high-concentration source region 1d constituting the pixel switching TFT 30
After forming the resist layer 600 on the scanning line 3a with a mask wider than the scanning line 3a in order to form the high-concentration drain region 1e, a dopant of a group V element such as P is also added at a high concentration (for example, , P ions from 1 to 3 × 10 ¹⁵ /
(dose at a dose of cm ² ). When the pixel switching TFT 30 is of a p-channel type, B or the like is used to form the low-concentration source region 1b and the low-concentration drain region 1c and the high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a. Using a Group III element dopant. Incidentally, for example, a TFT having an offset structure may be used without performing low concentration doping.
Using the scanning line 3a as a mask, a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like. The resistance of the capacitance line 3b and the scanning line 3a is further reduced by the doping of the impurity.

Incidentally, in parallel with the element forming process of the TFT 30, an n-channel TFT and a p-channel TFT are formed.
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of the TFT array substrate 10 may be formed in a peripheral portion on the TFT array substrate 10. As described above, if the semiconductor layer 1 forming the pixel switching TFT 30 in this embodiment is formed of polysilicon, the pixel switching TFT 30 can be formed.
Peripheral circuits can be formed in almost the same steps when forming the FT 30, which is advantageous in manufacturing.

Next, as shown in step (13), scan line 3
a on the gate insulating film 2 including the capacitor line 3a and the capacitor line 3b.
A first insulating film 81 made of a high-temperature silicon oxide film (HTO film) having a thickness of 10 nm or more
Deposit to a relatively thin thickness of less than 00 nm. The first insulating film 81 may be composed of a multilayer film, or the first insulating film 81 can be formed by various known techniques generally used for forming a gate insulating film of a TFT. In the case of the first insulating film 81, if the thickness is too small as in the case of the second insulating film 4, the parasitic capacitance between the data line 6a and the scanning line 3a does not increase, and the gate insulating film 2 in the TFT 30 does not increase. When the thickness is set to be too thin as described above, no peculiar phenomenon such as a tunnel effect occurs. Further, the first insulating film 81 functions as a second dielectric film between the second storage capacitor electrode, which is a part of the capacitor line, and the conductive layer 80.

Next, as shown in step (14), contact holes 8a are formed in the gate insulating film 2 and the first insulating film 81 in order to electrically connect the conductive layer 80 to be formed later and the high concentration drain region 1e. And dry etching such as reactive ion etching and reactive ion beam etching. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be formed. Alternatively, wet etching which is advantageous for preventing the contact hole 8a from penetrating the semiconductor layer 1 may be used together. This wet etching is also effective from the viewpoint of providing a taper for making better contact with the first contact hole 8a.

Next, as shown in step (15), an amorphous silicon film was deposited on the entire surface of the substrate by a reduced pressure CVD method or the like while introducing a dopant of a group V element such as P as an impurity, and the P was doped. A doped amorphous silicon film 101 is formed. The thickness of the doped amorphous silicon film 101 is about 100 to 1000 nm, preferably about 500 nm.

Next, as shown in step (16), a metal silicide film of tungsten silicide is deposited on the doped amorphous silicon film 101 by sputtering to form a conductive film 104 having a thickness of about 50 to 500 nm. I do. With a thickness of about 50 nm, there is almost no possibility that the contact hole 8b will penetrate when the contact hole 8b is later formed.

Next, as shown in step (17) of FIG. 8, a resist mask corresponding to the pattern of the conductive layer 80 (see FIG. 4) is formed on the formed conductive film 104 by photolithography. Conductive film 10 through mask
By performing etching on 4, a doped amorphous silicon layer 101 a and a conductive layer 104 a including a third storage capacitor electrode are formed.

[0094] Next, as shown in step (18), to activate the heavily doped source region 1d and the heavily doped drain region 1e, N ₂ (nitrogen) inert gas atmosphere and about 100, such as
Annealing at 0 ° C. is performed for about 20 minutes. As a result of this annealing, a high-concentration impurity-containing polysilicon layer is deposited at the interface between the doped amorphous silicon layer 101a and the conductive layer 104a, and the doped amorphous silicon layer 101a is converted into polysilicon to form a high-concentration impurity-containing polysilicon layer. Becomes Thereby, the doped amorphous silicon layer 101a and the conductive layer 104a become the conductive layer 80 having a three-layer structure of the doped polysilicon layer 83, the tungsten silicide layer 84, and the silicon oxide layer 85 as the polysilicon layer containing the high-concentration impurities. .

Next, as shown in step (19), the NSG, PS, and the like are used to cover the first insulating film 81 and the conductive layer 80 using, for example, normal pressure or reduced pressure CVD, TEOS gas, or the like.
A second insulating film 4 made of a silicate glass film such as G, BSG, BPSG or the like, a silicon nitride film, a silicon oxide film or the like is formed, and a second contact hole 5 for a data line 6a to be formed later is opened. The thickness of the second insulating film 4 is about 5
00 to 1500 nm is preferred. If the thickness of the second insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a causes little or no problem. Further, the contact holes for connecting the scanning lines 3a and the capacitance lines 3b to the wiring (not shown) in the peripheral region of the substrate are also formed in the second insulating film 4 in the same process as the second contact holes 5.
Can be opened.

Next, as shown in step (20), a light-shielding Al is formed on the second insulating film 4 by sputtering or the like.
A low resistance metal such as a metal silicide or the like is deposited here as a metal film 6 of Al in a thickness of about 100 to 500 nm, preferably about 300 nm.

Next, as shown in a step (21), the data lines 6 are formed by a photolithography step, an etching step and the like.
a is formed.

Next, as shown in step (22) of FIG. 9, for example, normal pressure or reduced pressure CV is applied to cover the data line 6a.
NSG, PSG, BS using D method or TEOS gas
An interlayer insulating film 7 made of a silicate glass film such as G or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the interlayer insulating film 7 is preferably about 500 to 1500 nm.

Next, as shown in step (23), a third contact hole 8b for electrically connecting the pixel electrode 9a and the conductive layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. Thereby, the silicon oxide film 85, the second insulating film 81, and the interlayer insulating film 7 are formed by etching. Further, wet etching may be used to form a tapered shape. Here, in the case of performing etching using wet etching, a metal silicide layer acts as a stopper by using a liquid that does not etch the metal silicide layer but etches only the interlayer insulating film, thereby efficiently etching. It can be performed.

Thereafter, dilute hydrofluoric acid (hydrofluoric acid: water = 1: 30)
50), the substrate is wet-processed to remove dust and SiO2 remaining in the third contact hole. Thus, the contact resistance between the pixel electrode formed later and the conductive layer can be reduced. Here, conventionally, when a high-melting-point metal silicide layer was used as the conductive layer, there was a problem that the conductive layer was cracked by hydrofluoric acid treatment. Since a high-concentration impurity-containing silicon layer is formed thereon, cracks are not generated by the hydrofluoric acid-based treatment liquid, and a high-quality conductive layer can be obtained.

Next, as shown in step (24), a transparent conductive thin film 9 such as an ITO film is deposited on the interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm.
Further, as shown in the step (25), the pixel electrode 9a is formed by a photolithography step, an etching step, or the like. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 5) is formed.

On the other hand, as for the counter substrate 60 shown in FIG. 5, a glass substrate or the like is first prepared, and the second light-shielding film 23 and the third light-shielding film as a frame are formed by, for example, sputtering metal chromium. , Through an etching process. Incidentally, these second and third light shielding films are:
In addition to metallic materials such as Cr, Ni and Al, carbon and Ti
May be formed from a material such as resin black dispersed in a photoresist. If the light-shielding region is defined by the data line 6a, the conductive layer 80, the first light-shielding film 11a, and the like on the TFT array substrate 90, the second light-shielding film 23 and the third light-shielding film on the counter substrate 90 can be omitted. it can.

Thereafter, a transparent conductive thin film of ITO or the like is applied to the entire surface of
The counter electrode 21 is formed by depositing to a thickness of 00 nm. Further, after applying a coating liquid for a polyimide-based alignment film on the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 5) is formed. It is formed.

Finally, the T on which each layer is formed as described above
The FT array substrate 90 and the opposing substrate 60 are bonded together with a sealing material disposed on the peripheral edge of the substrate such that the alignment films 16 and 22 face each other. Thereafter, the liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into the space between the two substrates by vacuum suction or the like, and the liquid crystal layer 50 having a predetermined thickness is formed.

In the present embodiment of the electro-optical device, the switching element provided in each pixel is described as a normal stagger type polysilicon TFT. However, other switching elements such as a reverse stagger type TFT and an amorphous silicon TFT are used. It is needless to say that the present invention can be applied to a type TFT. That is, the present invention can be applied to any semiconductor substrate as long as it has a structure for electrically connecting a semiconductor layer and a conductive layer containing a refractory metal silicide. Specifically, a silicon film having impurity ions and a high melting point metal silicide film are sequentially arranged in contact with the semiconductor layer.
By processing at a high temperature of not less than ℃, a high impurity concentration polysilicon film and a low impurity concentration silicon film are interposed between the semiconductor layer and the high melting point metal silicide, and the semiconductor layer and the high melting point metal silicide Can be reduced in contact resistance.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor substrate according to an embodiment.

FIG. 2 is a process chart for sequentially explaining a manufacturing process of the semiconductor substrate of the embodiment.

FIG. 3 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in the liquid crystal device according to the first embodiment of the electro-optical device.

FIG. 4 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light-shielding film, and the like are formed in the liquid crystal device according to the embodiment.

FIG. 5 is a sectional view taken along line A-A ′ of FIG. 4;

FIG. 6 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the liquid crystal device of the embodiment.

FIG. 8 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the liquid crystal device of the embodiment.

FIG. 9 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the liquid crystal device of the embodiment.

FIG. 10 is a schematic process diagram illustrating a conventional method for manufacturing a semiconductor substrate.

[Explanation of symbols]

1, 202 semiconductor layer 1a channel region 1b low concentration source region (source side LDD region) 1c low concentration drain region (drain side LDD region) 1d high concentration source region 1e high concentration drain region 1f first Storage capacitance electrode 2 ... Gate insulating film (first dielectric film) 3a ... Scan line 3b ... Capacitance line (second storage capacitance electrode) 4 ... Second insulating film 5 ... Contact hole 6a ... Data line 7 ... Interlayer insulating film 8a ... contact hole 8b ... contact hole 9a ... pixel electrode 10, 20, 201 ... substrate 30 ... pixel switching TFT 60 ... counter substrate 70 ... storage capacitor 80 ... conductive layer 81 ... first insulating film (second dielectric film) 83 ... doped polysilicon layer 84 ... refractory metal silicide layer 85 ... silicon oxide layer 90 ... TFT array substrate 101 ... doping before the activation process Amorphous silicon film 101a: doped amorphous silicon layer patterned before activation processing step 104: refractory metal silicide film 104 before activation processing step 104a: patterned refractory metal silicide layer before activation processing step 200: Liquid crystal device 204 ... Doped polysilicon film 205 ... Precipitation layer 206a ... High melting point metal silicide film before activation process 206 ... Tungsten silicide film 207 ... Silicon oxide film 208 ... Polysilicon film containing high concentration impurities 209 ... Doped amorphous silicon film before activation process

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 612C 616K 619B F term (Reference) 2H092 GA29 HA04 HA06 JA25 JA26 KA04 KA05 KA12 KA18 MA18 MA30 NA28 PA02 PA09 4M104 AA09 BB01 BB40 CC01 DD79 DD83 FF13 FF14 GG09 HH15 5F033 GG04 HH04 HH08 HH25 HH26 HH27 HH28 HH29 HH30 HH38 KK01 KK04 JJ30 KK13 KK14 QS04 HL05 HL08 HL09 HL11 HL14 HL23 HL24 HL27 HM14 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN45 NN46 NN47 NN54 NN72 NN73 PP02 PP03 PP10 PP13 PP33 QQ04 QQ05 QQ11

Claims (18)

[Claims] (A) forming a semiconductor layer on a substrate; and (b) forming an insulating film having a contact hole corresponding to a part of the semiconductor layer on the semiconductor layer. c) a step of forming a silicon film into which impurities are implanted on the insulating film and the semiconductor layer; (d) a step of forming a refractory metal silicide film on the silicon film; After the step, a step of heat-treating the substrate at a temperature of 900 ° C. or higher. 2. The method according to claim 1, wherein an impurity is implanted into the semiconductor layer, and the impurity is activated in the step (e). And (f) after the step (d) and before the step (e), further comprising a step of patterning the silicon film and the refractory metal silicide film into a predetermined shape to form a wiring. The method for manufacturing a semiconductor substrate according to claim 1, wherein the method is performed. 4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the silicon film formed in the step (c) is an amorphous silicon film. 5. The method according to claim 4, wherein the amorphous silicon film is converted into polysilicon by the step (e). 6. A semiconductor device comprising: a plurality of scanning lines; a plurality of data lines intersecting the scanning lines; a thin film transistor connected to each of the scanning lines and the data line; and a pixel electrode connected to the thin film transistor. In the method for manufacturing an electro-optical device, (a) a source region of the thin film transistor is provided on a substrate;
Forming a semiconductor layer to be a channel region and a drain region; (b) forming a gate insulating film covering the semiconductor layer; and (c) forming the scanning line on the gate insulating film. (D) forming a first contact hole in the gate insulating film corresponding to the drain region; and (e) forming a silicon film doped with impurities on the scanning line and the gate insulating film. (F) forming a refractory metal silicide film on the silicon film; and (g) patterning the silicon film and the refractory metal silicide film to form a conductive layer electrically connected to the first contact hole. A step of forming a layer; (h) a step of performing a heat treatment at a temperature of 900 ° C. or more after the step (g); and (i) the gate insulation including the conductive layer subjected to the heat treatment. Forming an insulating film having a second contact hole corresponding to the source region thereon; and (j) electrically connecting to the source region via the second contact hole on the insulating film. Forming the data line; (k) forming an interlayer insulating film having a third contact hole corresponding to the conductive layer on the insulating film including the data line; Forming the pixel electrode electrically connected to the conductive layer via the third contact hole on the film. 7. The method according to claim 6, wherein the semiconductor layer is formed by implanting an impurity, and the impurity is activated in the step (h). 8. The method according to claim 6, wherein the silicon film formed in the step (e) is an amorphous silicon film. 9. The method according to claim 8, wherein the amorphous silicon film is converted into polysilicon by the step (h). 10. The method according to claim 6, wherein the refractory metal silicide film is a light shielding film. 11. The electro-optical device further includes: a capacitor line disposed in the same layer and in parallel with the scanning line; and a dielectric layer formed to cover the capacitor line. The method according to any one of claims 6 to 10, wherein a capacitance is formed by the capacitance line and the conductive layer arranged via a dielectric layer. . 12. The electro-optical device further includes a capacitance electrode having the semiconductor layer extended, and a capacitance is formed by the capacitance electrode and the capacitance line disposed via the gate electrode. The method of manufacturing an electro-optical device according to claim 11, wherein: 13. The step (k) includes: forming the interlayer insulating film on the insulating film including the data line; and using the interlayer insulating film as a stopper with the refractory metal silicide layer of the conductive layer. The method of manufacturing an electro-optical device according to any one of claims 6 to 12, further comprising: forming the third contact hole by etching. 14. The method according to claim 6, wherein the pixel electrode is made of an indium tin oxide film. 15. The method according to claim 15, wherein the refractory metal silicide film comprises W,
The method according to any one of claims 6 to 14, wherein the method is a silicide film of a metal selected from at least one of Ti, Ta, Mo, and V. 16. The method according to claim 16, further comprising the step of: (m) treating the substrate with a hydrofluoric acid-based treatment liquid after the step (k) and before the step (l). A method for manufacturing an electro-optical device according to any one of claims 6 to 15. 17. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1. Description: 18. An electro-optical device manufactured by the method of manufacturing an electro-optical device according to claim 6. Description: